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Reviewed-by: Konrad Dybcio Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya --- Changes in V5: - No change arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index adc3fefcb469..31244b1d8c25 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -110,12 +110,29 @@ }; }; + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq9574"; + qcom,glink-channels = "rpm_requests"; + }; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x6000>; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; From patchwork Wed May 17 17:25:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 95443 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1309995vqo; Wed, 17 May 2023 10:38:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5YACtQBx77DkG46UuMlFwGXBwAsh5lrg7Fk2BN+nLgffPG9NsODismImE+hyqV0atdSygo X-Received: by 2002:a05:6a00:134b:b0:62d:8376:3712 with SMTP id k11-20020a056a00134b00b0062d83763712mr495847pfu.28.1684345132038; Wed, 17 May 2023 10:38:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684345132; cv=none; d=google.com; s=arc-20160816; b=0mCWWpOaIfQM+drpRFd+uzsGuK7JY9lA7eOxaNk7bXbhWE97VWeqgNIqyXus2P6dCT lESkT4FVg6f1B8M8Y3R7oeYVlt50w09UIw8xlzx+ai0Y0UgA4qQaGoEzbhI/di6Z6we0 9lxpQUgGNed4G4momSYLcgQrLIM7q9/ODKm0hjGi5MicwBdlwnEUwmszNjyf7b4v1on/ aAfr4lfuHnS6QTlN7vNj4ncDsGBG2ICxGADa5rcAbTg3y+c0uWEWifkaQ9I4A2hF23Kh TTtmbXsrAkRR7btWxgjIi+fenkPY+iY7u/1sCsRuz2kIA0iDLmZABenvyDdzSHt8dnoh vV6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=50vZCR6Um2Af56k3OG0fh7z188sheFTXoHEhV8QJNv0=; b=QjcXV0VBVoMcOOlVX9Y7nv9lzkwPiBOq9COcyr4K1J8PKjSpa2KAQHV0dyMHtLa1oK 4TfOIipTny3Z/Ya9R5mIveqZb543LYsPhdgG31lSOLEqGot8g0b+V6aZPUpY3yoFzifB Ps2wOGtjvhLAO8lXmkf7PpayFOkpv/NwL888xfbNq5IIiR8ydkbC6LNnuCqBGfv2Bb31 pgF1k98vOmnIb6aMoymQcKh+h+UK/JZhIxFLxU7a00wqXlANKsYfuI9SP39HlXspNkgS k+QUCn+Ow4vbB2vbT7oZmEuIx7t22JWno6jW+DAy0hB0ZSrSfoAQfADtF29kYnieNFI7 1ohw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=hdZKPh2D; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Konrad Dybcio Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya --- Changes in V5: - Picked up the R-b tag arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 7be578017bf7..1a35fbc42f8c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -43,6 +43,25 @@ }; }; +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; From patchwork Wed May 17 17:25:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 95441 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1304333vqo; Wed, 17 May 2023 10:29:09 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4XX+d6xQiAIJDq+WtQq/l9mlfSL+Ai2JvyIrZ/knQy9Da5jJC+l8vq2W9aNldh67Mw03nT X-Received: by 2002:a05:6a20:a10d:b0:101:4d10:e40a with SMTP id q13-20020a056a20a10d00b001014d10e40amr38935096pzk.12.1684344548772; Wed, 17 May 2023 10:29:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684344548; cv=none; d=google.com; s=arc-20160816; b=f1B838+JiKNcFG6oZGqu69tSPiUozli2tIzjGL+500bzTzvcAEvNcG8wzM7sCIMjsH DNyKK/K3wBbel9+G1Fltx+dru24BkTiKT7SWtsFBrsFcbe79NX65JdXQUJ4wLhHp9sYD lDATB0WktZ2eTwFsbMZ+kh3yE20jka64j7jQTBLKvX/mTZYKkJW7cveeGUUWK/9cjgl9 KOmYxO6ugLR4xSX4daEIMY5Zbw6aMDQZDPklmCw6J5T7yP5fUJl2zfUfpVMMx5BjCfHP 2t27d0+D2LDNFkA8XVLCDpo0CxHMMtpeb8d0ljRmZtubp5hWqRZYTuteImLOGDkNoZdf BvNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=jGXX9lnReOzc9h/R39hgS5rI53YOA/sU83/rJyiiLyw=; b=Ix+yDRoGSDK9ZQV0m0twte0mZHFcPy0+bTKzljpPUY3mAAImrxGwaGjXppDxUJ0L8L ythvqGrvhkK76QiOFi92CVhPLiIrdgCHMcI7qwv+qaZwU1yhlqsf44O9SqOA5Ww32j+g +IhnBcRAOmsj0u82fCmuVX+O/6N6fI3OEQMp0hUmc3mLw8PJoVTu3zzp6N7HaNVj+dCY e1phGpKW1h9aRdkYolKfDYObB5AZQrejfCxigVS0yoxG9FxyTX4VxxKb0fRNOKgAl4g1 yjg8lRJLBcDMSG0JM1r6rIp/Wnx7FZg9xbJ/Os1fME9MVAqHbFhBDVue1nV5j1AUTedb O3UQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=HIbEsN3U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Konrad Dybcio Co-developed-by: Praveenkumar I Signed-off-by: Praveenkumar I Signed-off-by: Devi Priya --- Changes in V5: - Sorted the includes alphabetically arch/arm64/boot/dts/qcom/ipq9574.dtsi | 60 ++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 31244b1d8c25..16edffe53c8b 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -6,8 +6,9 @@ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ -#include +#include #include +#include #include / { @@ -37,6 +38,10 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU1: cpu@1 { @@ -45,6 +50,10 @@ reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU2: cpu@2 { @@ -53,6 +62,10 @@ reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; CPU3: cpu@3 { @@ -61,6 +74,10 @@ reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq9574_s1>; }; L2_0: l2-cache { @@ -82,6 +99,47 @@ reg = <0x0 0x40000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <725000>; + clock-latency-ns = <200000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <787500>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <862500>; + clock-latency-ns = <200000>; + }; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1062500>; + clock-latency-ns = <200000>; + }; + }; + pmu { compatible = "arm,cortex-a73-pmu"; interrupts = ;