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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p5-20020a17090ab90500b001fdd2a56d6dsi9923021pjr.43.2022.10.24.23.00.31; Mon, 24 Oct 2022 23:00:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=qAGmpm7e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbiJYFmw (ORCPT + 99 others); Tue, 25 Oct 2022 01:42:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbiJYFms (ORCPT ); Tue, 25 Oct 2022 01:42:48 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B212C7062 for ; Mon, 24 Oct 2022 22:42:43 -0700 (PDT) X-UUID: 8caf731b86b142259e8db0faf5819e59-20221025 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=XIEKHeBnDpf8qnQLc78wkKjbYdk1bbgIcbqYREQemf4=; b=qAGmpm7edeIP5GS9s7QKsIsBD02FH8I1aboPf4W+deUjzrBZ2228h6VrEkIVTMBsOJfKQCZPPbcLZUeA7wxLgBszocEpmKVM+8GiYAcQeDXP+wtr9FwMYW9XVIOXPLr4EzKRoychbL6c59U/wbHX6fGGqeJCRwuOWVpZWXWDFK4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:18cf1d0b-b721-45d1-a344-55c2f096ec07,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.12,REQID:18cf1d0b-b721-45d1-a344-55c2f096ec07,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:62cd327,CLOUDID:3e3a006d-89d3-4bfa-baad-dc632a24bca3,B ulkID:221025134238KYBXWPNT,BulkQuantity:0,Recheck:0,SF:28|17|19|48,TC:nil, Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 8caf731b86b142259e8db0faf5819e59-20221025 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 893644; Tue, 25 Oct 2022 13:42:36 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 25 Oct 2022 13:42:35 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 25 Oct 2022 13:42:34 +0800 From: Chunfeng Yun To: Vinod Koul CC: Chunfeng Yun , Kishon Vijay Abraham I , Matthias Brugger , , , , , AngeloGioacchino Del Regno , "Eddie Hung" Subject: [PATCH RESEND v3 1/2] phy: core: add debugfs root Date: Tue, 25 Oct 2022 13:42:32 +0800 Message-ID: <20221025054233.9763-1-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747638179242180714?= X-GMAIL-MSGID: =?utf-8?q?1747638179242180714?= Add a debugfs root for phy class, then phy drivers can add debugfs files under this folder. Signed-off-by: Chunfeng Yun --- v2~v3: no changes --- drivers/phy/phy-core.c | 6 ++++++ include/linux/phy/phy.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index d93ddf1262c5..2f9f69190519 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1204,6 +1205,9 @@ void devm_of_phy_provider_unregister(struct device *dev, } EXPORT_SYMBOL_GPL(devm_of_phy_provider_unregister); +struct dentry *phy_debug_root; +EXPORT_SYMBOL_GPL(phy_debug_root); + /** * phy_release() - release the phy * @dev: the dev member within phy @@ -1233,6 +1237,8 @@ static int __init phy_core_init(void) phy_class->dev_release = phy_release; + phy_debug_root = debugfs_create_dir("phy", NULL); + return 0; } device_initcall(phy_core_init); diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index b1413757fcc3..c398749d49b9 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -205,6 +205,8 @@ struct phy_lookup { #define devm_of_phy_provider_register_full(dev, children, xlate) \ __devm_of_phy_provider_register(dev, children, THIS_MODULE, xlate) +extern struct dentry *phy_debug_root; + static inline void phy_set_drvdata(struct phy *phy, void *data) { dev_set_drvdata(&phy->dev, data); From patchwork Tue Oct 25 05:42:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 10503 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp823834wru; Mon, 24 Oct 2022 22:44:01 -0700 (PDT) X-Google-Smtp-Source: AMsMyM47KRf6m05X1SKYXILSwSry2x0TWBDK+9TlWkHQFiSPDB1HKGa7zct33PO/XnXe134bQzNo X-Received: by 2002:a17:906:da85:b0:741:40a7:d08d with SMTP id xh5-20020a170906da8500b0074140a7d08dmr32508796ejb.263.1666676641042; Mon, 24 Oct 2022 22:44:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666676641; cv=none; d=google.com; s=arc-20160816; b=Trb7ZcgWfG6eUxtNDPyktmqEvkM2fDWjnpinrJLqsQfxkss+y13t75onZTEBMpLCTg F/oEVrRL6m1RtqGxU8DNzecd0U2e+VAoJhwSFcpENfXWkGZISY3ktFvjTeqNvsbmDuK2 kopNpreBmcNFx5aYYBFfs7qmRCjBbviMsZN2tyHBi+ltUrYuKx17kGxGMHQ0ohS/mxrh uPz3VJ+9cE9TGlRaSGmT1T2n0fIi1R7hpKcp02u7QN3p2c44gLDVn0n5wbe8ZtGstWbC KVGkMquhRl/kUMpETBQt77wZqHp9+0I2iHhGOTWdG4T8cCzX1pPT8yQxD2lbOY1gjfG0 QYWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=M4cFnQsOUE50z1rkShmdIOYQvG3w/5mCx097ILZ15fU=; b=qymFLHwvyp+ZtgGmAMFq9pzOg3eHH6s+kMmG7oEFbHuUkuYlOrdN4yVHVIY/aqWH2o hzjwWpB8wyJJTAZ70eH0bl4/ThYk4Q3yMvT1osr3UAnx2XmFHsDwJiKuU9MTCuvlaNCK QMyn7ZSsOjKkGM6S5zfpZy3V8BCNe6xDVnHQOeiEHERSODt+Mht48+LSD5LudK4eEJr3 oFQxfPkl2Hi9WxxdS+/5rXUe7rmVr0pI/xeO33eYy5gLI75HP/AufSwOELDmw7VJ3pNA NMsSzW6DtCSjR/Gl7NUoEHS0hy3bITvhQxSXzu9yeGy9VNBxBWT7LXp/ItLc//JI5cgZ 7N5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=ge+4Qpya; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Chunfeng Yun --- v3: fix typo of "debugfs" suggested by AngeloGioacchino v2: add CONFIG_PHY_MTK_TPHY_DEBUGFS suggested by AngeloGioacchino --- drivers/phy/mediatek/Kconfig | 5 + drivers/phy/mediatek/phy-mtk-tphy.c | 403 +++++++++++++++++++++++++++- 2 files changed, 407 insertions(+), 1 deletion(-) diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig index 3125ecb5d119..e9fdfe9f519f 100644 --- a/drivers/phy/mediatek/Kconfig +++ b/drivers/phy/mediatek/Kconfig @@ -27,6 +27,11 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second version, so you can easily distinguish them by banks layout. +config PHY_MTK_TPHY_DEBUGFS + bool "Add T-PHY Debugfs Files" + help + Say Y here to add debugfs files mainly for T-PHY HQA test. + config PHY_MTK_UFS tristate "MediaTek UFS M-PHY driver" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index e906a82791bd..99677665a9c4 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -264,6 +265,8 @@ #define TPHY_CLKS_CNT 2 +#define USER_BUF_LEN(count) min_t(size_t, 8, (count)) + enum mtk_phy_version { MTK_PHY_V1 = 1, MTK_PHY_V2, @@ -310,6 +313,7 @@ struct mtk_phy_instance { struct clk_bulk_data clks[TPHY_CLKS_CNT]; u32 index; u32 type; + struct dentry *dbgfs; struct regmap *type_sw; u32 type_sw_reg; u32 type_sw_index; @@ -332,10 +336,389 @@ struct mtk_tphy { const struct mtk_phy_pdata *pdata; struct mtk_phy_instance **phys; int nphys; + struct dentry *dbgfs_root; int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ int src_coef; /* coefficient for slew rate calibrate */ }; +#if IS_ENABLED(CONFIG_PHY_MTK_TPHY_DEBUGFS) + +enum u2_phy_params { + U2P_EYE_VRT = 0, + U2P_EYE_TERM, + U2P_EFUSE_EN, + U2P_EFUSE_INTR, + U2P_DISCTH, + U2P_PRE_EMPHASIS, +}; + +enum u3_phy_params { + U3P_EFUSE_EN = 0, + U3P_EFUSE_INTR, + U3P_EFUSE_TX_IMP, + U3P_EFUSE_RX_IMP, +}; + +static const char *const u2_phy_files[] = { + [U2P_EYE_VRT] = "vrt", + [U2P_EYE_TERM] = "term", + [U2P_EFUSE_EN] = "efuse", + [U2P_EFUSE_INTR] = "intr", + [U2P_DISCTH] = "discth", + [U2P_PRE_EMPHASIS] = "preemph", +}; + +static const char *const u3_phy_files[] = { + [U3P_EFUSE_EN] = "efuse", + [U3P_EFUSE_INTR] = "intr", + [U3P_EFUSE_TX_IMP] = "tx-imp", + [U3P_EFUSE_RX_IMP] = "rx-imp", +}; + +static int u2_phy_params_show(struct seq_file *sf, void *unused) +{ + struct mtk_phy_instance *inst = sf->private; + const char *fname = file_dentry(sf->file)->d_iname; + struct u2phy_banks *u2_banks = &inst->u2_banks; + void __iomem *com = u2_banks->com; + u32 max = 0; + u32 tmp = 0; + u32 val = 0; + int ret; + + ret = match_string(u2_phy_files, ARRAY_SIZE(u2_phy_files), fname); + if (ret < 0) + return ret; + + switch (ret) { + case U2P_EYE_VRT: + tmp = readl(com + U3P_USBPHYACR1); + val = FIELD_GET(PA1_RG_VRT_SEL, tmp); + max = FIELD_MAX(PA1_RG_VRT_SEL); + break; + + case U2P_EYE_TERM: + tmp = readl(com + U3P_USBPHYACR1); + val = FIELD_GET(PA1_RG_TERM_SEL, tmp); + max = FIELD_MAX(PA1_RG_TERM_SEL); + break; + + case U2P_EFUSE_EN: + if (u2_banks->misc) { + tmp = readl(u2_banks->misc + U3P_MISC_REG1); + max = 1; + } + + val = !!(tmp & MR1_EFUSE_AUTO_LOAD_DIS); + break; + + case U2P_EFUSE_INTR: + tmp = readl(com + U3P_USBPHYACR1); + val = FIELD_GET(PA1_RG_INTR_CAL, tmp); + max = FIELD_MAX(PA1_RG_INTR_CAL); + break; + + case U2P_DISCTH: + tmp = readl(com + U3P_USBPHYACR6); + val = FIELD_GET(PA6_RG_U2_DISCTH, tmp); + max = FIELD_MAX(PA6_RG_U2_DISCTH); + break; + + case U2P_PRE_EMPHASIS: + tmp = readl(com + U3P_USBPHYACR6); + val = FIELD_GET(PA6_RG_U2_PRE_EMP, tmp); + max = FIELD_MAX(PA6_RG_U2_PRE_EMP); + break; + + default: + seq_printf(sf, "invalid, %d\n", ret); + break; + } + + seq_printf(sf, "%s : %d [0, %d]\n", fname, val, max); + + return 0; +} + +static int u2_phy_params_open(struct inode *inode, struct file *file) +{ + return single_open(file, u2_phy_params_show, inode->i_private); +} + +static ssize_t u2_phy_params_write(struct file *file, const char __user *ubuf, + size_t count, loff_t *ppos) +{ + const char *fname = file_dentry(file)->d_iname; + struct seq_file *sf = file->private_data; + struct mtk_phy_instance *inst = sf->private; + struct u2phy_banks *u2_banks = &inst->u2_banks; + void __iomem *com = u2_banks->com; + ssize_t rc; + u32 val; + int ret; + + rc = kstrtouint_from_user(ubuf, USER_BUF_LEN(count), 0, &val); + if (rc) + return rc; + + ret = match_string(u2_phy_files, ARRAY_SIZE(u2_phy_files), fname); + if (ret < 0) + return (ssize_t)ret; + + switch (ret) { + case U2P_EYE_VRT: + mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, val); + break; + + case U2P_EYE_TERM: + mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, val); + break; + + case U2P_EFUSE_EN: + if (u2_banks->misc) + mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1, + MR1_EFUSE_AUTO_LOAD_DIS, !!val); + break; + + case U2P_EFUSE_INTR: + mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, val); + break; + + case U2P_DISCTH: + mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, val); + break; + + case U2P_PRE_EMPHASIS: + mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, val); + break; + + default: + break; + } + + return count; +} + +static const struct file_operations u2_phy_fops = { + .open = u2_phy_params_open, + .write = u2_phy_params_write, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void u2_phy_dbgfs_files_create(struct mtk_phy_instance *inst) +{ + u32 count = ARRAY_SIZE(u2_phy_files); + int i; + + for (i = 0; i < count; i++) + debugfs_create_file(u2_phy_files[i], 0644, inst->dbgfs, inst, &u2_phy_fops); +} + +static int u3_phy_params_show(struct seq_file *sf, void *unused) +{ + struct mtk_phy_instance *inst = sf->private; + const char *fname = file_dentry(sf->file)->d_iname; + struct u3phy_banks *u3_banks = &inst->u3_banks; + u32 val, tmp, max; + int ret; + + ret = match_string(u3_phy_files, ARRAY_SIZE(u3_phy_files), fname); + if (ret < 0) + return ret; + + switch (ret) { + case U3P_EFUSE_EN: + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); + val = !!(tmp & P3D_RG_EFUSE_AUTO_LOAD_DIS); + max = 1; + break; + + case U3P_EFUSE_INTR: + tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); + val = FIELD_GET(P3A_RG_IEXT_INTR, tmp); + max = FIELD_MAX(P3A_RG_IEXT_INTR); + break; + + case U3P_EFUSE_TX_IMP: + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); + val = FIELD_GET(P3D_RG_TX_IMPEL, tmp); + max = FIELD_MAX(P3D_RG_TX_IMPEL); + break; + + case U3P_EFUSE_RX_IMP: + tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); + val = FIELD_GET(P3D_RG_RX_IMPEL, tmp); + max = FIELD_MAX(P3D_RG_RX_IMPEL); + break; + + default: + seq_printf(sf, "invalid, %d\n", ret); + break; + } + + seq_printf(sf, "%s : %d [0, %d]\n", fname, val, max); + + return 0; +} + +static int u3_phy_params_open(struct inode *inode, struct file *file) +{ + return single_open(file, u3_phy_params_show, inode->i_private); +} + +static ssize_t u3_phy_params_write(struct file *file, const char __user *ubuf, + size_t count, loff_t *ppos) +{ + const char *fname = file_dentry(file)->d_iname; + struct seq_file *sf = file->private_data; + struct mtk_phy_instance *inst = sf->private; + struct u3phy_banks *u3_banks = &inst->u3_banks; + void __iomem *phyd = u3_banks->phyd; + ssize_t rc; + u32 val; + int ret; + + rc = kstrtouint_from_user(ubuf, USER_BUF_LEN(count), 0, &val); + if (rc) + return rc; + + ret = match_string(u3_phy_files, ARRAY_SIZE(u3_phy_files), fname); + if (ret < 0) + return (ssize_t)ret; + + switch (ret) { + case U3P_EFUSE_EN: + mtk_phy_update_field(phyd + U3P_U3_PHYD_RSV, + P3D_RG_EFUSE_AUTO_LOAD_DIS, !!val); + break; + + case U3P_EFUSE_INTR: + mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR, val); + break; + + case U3P_EFUSE_TX_IMP: + mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, val); + mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); + break; + + case U3P_EFUSE_RX_IMP: + mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, val); + mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); + break; + + default: + break; + } + + return count; +} + +static const struct file_operations u3_phy_fops = { + .open = u3_phy_params_open, + .write = u3_phy_params_write, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void u3_phy_dbgfs_files_create(struct mtk_phy_instance *inst) +{ + u32 count = ARRAY_SIZE(u3_phy_files); + int i; + + for (i = 0; i < count; i++) + debugfs_create_file(u3_phy_files[i], 0644, inst->dbgfs, inst, &u3_phy_fops); +} + +static int tphy_type_show(struct seq_file *sf, void *unused) +{ + struct mtk_phy_instance *inst = sf->private; + const char *type; + + switch (inst->type) { + case PHY_TYPE_USB2: + type = "USB2"; + break; + case PHY_TYPE_USB3: + type = "USB3"; + break; + case PHY_TYPE_PCIE: + type = "PCIe"; + break; + case PHY_TYPE_SGMII: + type = "SGMII"; + break; + case PHY_TYPE_SATA: + type = "SATA"; + break; + default: + type = ""; + } + + seq_printf(sf, "%s\n", type); + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(tphy_type); + +static void tphy_debugfs_init(struct mtk_tphy *tphy, struct mtk_phy_instance *inst) +{ + char name[16]; + + snprintf(name, sizeof(name) - 1, "phy.%d", inst->index); + inst->dbgfs = debugfs_create_dir(name, tphy->dbgfs_root); + + debugfs_create_file("type", 0444, inst->dbgfs, inst, &tphy_type_fops); + + switch (inst->type) { + case PHY_TYPE_USB2: + u2_phy_dbgfs_files_create(inst); + break; + case PHY_TYPE_USB3: + case PHY_TYPE_PCIE: + u3_phy_dbgfs_files_create(inst); + break; + default: + break; + } +} + +static void tphy_debugfs_exit(struct mtk_phy_instance *inst) +{ + debugfs_remove_recursive(inst->dbgfs); + inst->dbgfs = NULL; +} + +static void tphy_debugfs_root_create(struct mtk_tphy *tphy) +{ + tphy->dbgfs_root = debugfs_create_dir(dev_name(tphy->dev), phy_debug_root); +} + +static void tphy_debugfs_root_remove(struct mtk_tphy *tphy) +{ + debugfs_remove_recursive(tphy->dbgfs_root); + tphy->dbgfs_root = NULL; +} + +#else + +static void tphy_debugfs_init(struct mtk_tphy *tphy, struct mtk_phy_instance *inst) +{} + +static void tphy_debugfs_exit(struct mtk_phy_instance *inst) +{} + +static void tphy_debugfs_root_create(struct mtk_tphy *tphy) +{} + +static void tphy_debugfs_root_remove(struct mtk_tphy *tphy) +{} + +#endif + static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { @@ -1032,6 +1415,8 @@ static int mtk_phy_init(struct phy *phy) return -EINVAL; } + tphy_debugfs_init(tphy, instance); + return 0; } @@ -1068,6 +1453,8 @@ static int mtk_phy_exit(struct phy *phy) struct mtk_phy_instance *instance = phy_get_drvdata(phy); struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); + tphy_debugfs_exit(instance); + if (instance->type == PHY_TYPE_USB2) u2_phy_instance_exit(tphy, instance); @@ -1295,15 +1682,29 @@ static int mtk_tphy_probe(struct platform_device *pdev) } provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); + if (IS_ERR(provider)) + return dev_err_probe(dev, PTR_ERR(provider), "probe failed\n"); + + tphy_debugfs_root_create(tphy); + return 0; - return PTR_ERR_OR_ZERO(provider); put_child: of_node_put(child_np); return retval; } +static int mtk_tphy_remove(struct platform_device *pdev) +{ + struct mtk_tphy *tphy; + + tphy = platform_get_drvdata(pdev); + tphy_debugfs_root_remove(tphy); + return 0; +} + static struct platform_driver mtk_tphy_driver = { .probe = mtk_tphy_probe, + .remove = mtk_tphy_remove, .driver = { .name = "mtk-tphy", .of_match_table = mtk_tphy_id_table,