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[8.43.85.97]) by mx.google.com with ESMTPS id gz9-20020a170907a04900b0094e7f8172besi16819747ejc.875.2023.05.16.18.52.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 18:52:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A407138323E3 for ; Wed, 17 May 2023 01:52:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id 90ADE3857733 for ; Wed, 17 May 2023 01:51:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 90ADE3857733 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp86t1684288308tehcjccg Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 17 May 2023 09:51:47 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: qcKkmz/zJhy0hcN8HtxGvhHCp5pwISgcFJu98ozY3Tpks/59Jli0cCC5bYHDg hDRwbTDfXCyWDTyRsDFUF6GbHKuHDe5yPhwyj7/RmnZRfIMJ1DyDQYRrOji/Sw/KkQWdeAu IvvuzvL+es5mSFgZ/pbjTWxUftbOFRcyXLl0cHJl/qXsx52XNi9DpgYplTQpPoRuIvaKkwH QaB+qDfAtrtu07r7IyF6XChY+C8xhkzJKcKy0EPAgDE19Zg3uOwUJdiGd2eMcuD4yg/OhzP Bhn+nruFvtiiXtygfA3w4yRdG649NiI4PM8Io2k036wywqrzw0zQZiDYXmMGvcDZvap0g8l PSZ5KkHn+0VNN+Bg/WwVJrQM4A4wOmw3UXZsvjxfpZzAWh1q1dNsbBWdfjor0pHQ4Kmap4e X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5306445030174597347 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics Date: Wed, 17 May 2023 09:51:43 +0800 Message-Id: <20230517015143.4023434-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766104356581005390?= X-GMAIL-MSGID: =?utf-8?q?1766104356581005390?= From: Juzhe-Zhong Hi, since fixed-point with modeling rounding mode intrinsics are coming: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222 I am adding vxrm rounding mode enum to user first before the API intrinsic. This patch is simple && obvious. Ok for trunk ? gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (register_vxrm): New function. (DEF_RVV_VXRM_ENUM): New macro. (handle_pragma_vector): Add vxrm enum register. * config/riscv/riscv-vector-builtins.def (DEF_RVV_VXRM_ENUM): New macro. (RNU): Ditto. (RNE): Ditto. (RDN): Ditto. (ROD): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vxrm-1.c: New test. --- gcc/config/riscv/riscv-vector-builtins.cc | 16 ++++++++++ gcc/config/riscv/riscv-vector-builtins.def | 11 +++++++ .../gcc.target/riscv/rvv/base/vxrm-1.c | 29 +++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index b7458aaace6..bcabf1ea1a6 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3740,6 +3740,19 @@ verify_type_context (location_t loc, type_context_kind context, const_tree type, gcc_unreachable (); } +/* Register the vxrm enum. */ +static void +register_vxrm () +{ + auto_vec values; +#define DEF_RVV_VXRM_ENUM(NAME, VALUE) \ + values.quick_push (string_int_pair ("VXRM_" #NAME, VALUE)); +#include "riscv-vector-builtins.def" +#undef DEF_RVV_VXRM_ENUM + + lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM", &values); +} + /* Implement #pragma riscv intrinsic vector. */ void handle_pragma_vector () @@ -3755,6 +3768,9 @@ handle_pragma_vector () for (unsigned int type_i = 0; type_i < NUM_VECTOR_TYPES; ++type_i) register_vector_type ((enum vector_type_index) type_i); + /* Define the enums. */ + register_vxrm (); + /* Define the functions. */ function_table = new hash_table (1023); function_builder builder; diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 0a387fd1617..2a1a9dbc903 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -83,6 +83,11 @@ along with GCC; see the file COPYING3. If not see X64_VLMUL_EXT, TUPLE_SUBPART) #endif +/* Define RVV_VXRM rounding mode enum for fixed-point intrinsics. */ +#ifndef DEF_RVV_VXRM_ENUM +#define DEF_RVV_VXRM_ENUM(NAME, VALUE) +#endif + /* SEW/LMUL = 64: Only enable when TARGET_MIN_VLEN > 32. Machine mode = VNx1BImode when TARGET_MIN_VLEN < 128. @@ -643,6 +648,11 @@ DEF_RVV_BASE_TYPE (vlmul_ext_x64, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (size_ptr, build_pointer_type (size_type_node)) DEF_RVV_BASE_TYPE (tuple_subpart, get_tuple_subpart_type (type_idx)) +DEF_RVV_VXRM_ENUM (RNU, VXRM_RNU) +DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE) +DEF_RVV_VXRM_ENUM (RDN, VXRM_RDN) +DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD) + #include "riscv-vector-type-indexer.gen.def" #undef DEF_RVV_PRED_TYPE @@ -651,3 +661,4 @@ DEF_RVV_BASE_TYPE (tuple_subpart, get_tuple_subpart_type (type_idx)) #undef DEF_RVV_TUPLE_TYPE #undef DEF_RVV_BASE_TYPE #undef DEF_RVV_TYPE_INDEX +#undef DEF_RVV_VXRM_ENUM diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c new file mode 100644 index 00000000000..0d364787ad0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +size_t f0 () +{ + return VXRM_RNU; +} + +size_t f1 () +{ + return VXRM_RNE; +} + +size_t f2 () +{ + return VXRM_RDN; +} + +size_t f3 () +{ + return VXRM_ROD; +} + +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */ +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*1} 1} } */ +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*2} 1} } */ +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*3} 1} } */