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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id sb31-20020a1709076d9f00b00780805b99ccsi1630901ejc.648.2022.10.24.20.23.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Oct 2022 20:23:26 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B3B8938582BE for ; Tue, 25 Oct 2022 03:23:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id 1DF883858418 for ; Tue, 25 Oct 2022 03:22:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1DF883858418 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp84t1666668161tlaqdk5g Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 25 Oct 2022 11:22:40 +0800 (CST) X-QQ-SSF: 01400000000000D0K000000A0000000 X-QQ-FEAT: 6aXALTFZqPteqaQSckM8fDOn8Aal7eKMixqfr8jxn2XqnpUX65PKa1gmYCgHl Q05qvOHRzbjt+ogvdxeeB2jHpZlFGezBJgB+S4b3q6spjUPiEVoQ+ma5uW+CIURMQJsoKfs /7XwNMecUazqPENJqyteVEkkpKCyEriUVCuZYxMY9iDnFbwIiBRP0BdA/p0iZbrShCyj1W4 a8jh16t87jkfoL7A06tuN51/C4DRQbV5AMXJ4ternscmhPeHfwBqBFRvAI9YVcxR9Ze/g2l 3we2ak+chMiK8DhTdNiHd2jdIiyNNAImQtqu7bEW9Lql769UY155xN+Ylb6+275Hk0wldcT Opr4QEy4l/LhuzpoH+nDYR5KcIypZfuHYQruNHv31A79oFOazZo4wzG6m7ZcHSpw+ttbyT0 X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: ADJUST_NUNITS according to -march. Date: Tue, 25 Oct 2022 11:22:38 +0800 Message-Id: <20221025032238.322211-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747628281773956413?= X-GMAIL-MSGID: =?utf-8?q?1747628281773956413?= From: Ju-Zhe Zhong This patch fixed PR107357: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107357 gcc/ChangeLog: * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Set to minimum size. (ADJUST_NUNITS): Adjust according to -march. (ADJUST_BYTESIZE): Ditto. * config/riscv/riscv-protos.h (riscv_v_ext_enabled_vector_mode_p): Remove. (riscv_v_ext_vector_mode_p): Change function implementation. * config/riscv/riscv-vector-builtins.cc (rvv_switcher::rvv_switcher): Change to riscv_v_ext_vector_mode_p. (register_builtin_type): Ditto. * config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): Change to enabled modes. (ENTRY): Ditto. (riscv_v_ext_enabled_vector_mode_p): Remove. (riscv_v_adjust_nunits): New function. (riscv_vector_mode_supported_p): Use riscv_v_ext_vector_mode_p instead. * config/riscv/riscv.h (riscv_v_adjust_nunits): New function. --- gcc/config/riscv/riscv-modes.def | 63 ++++++++++++----------- gcc/config/riscv/riscv-protos.h | 2 +- gcc/config/riscv/riscv-vector-builtins.cc | 4 +- gcc/config/riscv/riscv.cc | 33 +++++------- gcc/config/riscv/riscv.h | 1 + 5 files changed, 50 insertions(+), 53 deletions(-) diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index ea88442e117..556b5c55253 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -37,21 +37,24 @@ FLOAT_MODE (TF, 16, ieee_quad_format); | VNx32BI | 1 | 2 | | VNx64BI | N/A | 1 | */ -VECTOR_BOOL_MODE (VNx1BI, 1, BI, 8); -VECTOR_BOOL_MODE (VNx2BI, 2, BI, 8); -VECTOR_BOOL_MODE (VNx4BI, 4, BI, 8); -VECTOR_BOOL_MODE (VNx8BI, 8, BI, 8); -VECTOR_BOOL_MODE (VNx16BI, 16, BI, 8); -VECTOR_BOOL_MODE (VNx32BI, 32, BI, 8); +/* For RVV modes, each boolean value occupies 1-bit. + 4th argument is specify the minmial possible size of the vector mode, + and will adjust to the right size by ADJUST_BYTESIZE. */ +VECTOR_BOOL_MODE (VNx1BI, 1, BI, 1); +VECTOR_BOOL_MODE (VNx2BI, 2, BI, 1); +VECTOR_BOOL_MODE (VNx4BI, 4, BI, 1); +VECTOR_BOOL_MODE (VNx8BI, 8, BI, 1); +VECTOR_BOOL_MODE (VNx16BI, 16, BI, 2); +VECTOR_BOOL_MODE (VNx32BI, 32, BI, 4); VECTOR_BOOL_MODE (VNx64BI, 64, BI, 8); -ADJUST_NUNITS (VNx1BI, riscv_vector_chunks * 1); -ADJUST_NUNITS (VNx2BI, riscv_vector_chunks * 2); -ADJUST_NUNITS (VNx4BI, riscv_vector_chunks * 4); -ADJUST_NUNITS (VNx8BI, riscv_vector_chunks * 8); -ADJUST_NUNITS (VNx16BI, riscv_vector_chunks * 16); -ADJUST_NUNITS (VNx32BI, riscv_vector_chunks * 32); -ADJUST_NUNITS (VNx64BI, riscv_vector_chunks * 64); +ADJUST_NUNITS (VNx1BI, riscv_v_adjust_nunits (VNx1BImode, 1)); +ADJUST_NUNITS (VNx2BI, riscv_v_adjust_nunits (VNx2BImode, 2)); +ADJUST_NUNITS (VNx4BI, riscv_v_adjust_nunits (VNx4BImode, 4)); +ADJUST_NUNITS (VNx8BI, riscv_v_adjust_nunits (VNx8BImode, 8)); +ADJUST_NUNITS (VNx16BI, riscv_v_adjust_nunits (VNx16BImode, 16)); +ADJUST_NUNITS (VNx32BI, riscv_v_adjust_nunits (VNx32BImode, 32)); +ADJUST_NUNITS (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 64)); ADJUST_ALIGNMENT (VNx1BI, 1); ADJUST_ALIGNMENT (VNx2BI, 1); @@ -67,7 +70,7 @@ ADJUST_BYTESIZE (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx64BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); +ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8)); /* | Mode | MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 | @@ -101,13 +104,13 @@ ADJUST_BYTESIZE (VNx64BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); VECTOR_MODES_WITH_PREFIX (VNx, INT, 8 * NVECS, 0); \ VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 8 * NVECS, 0); \ \ - ADJUST_NUNITS (VB##QI, riscv_vector_chunks * NVECS * 8); \ - ADJUST_NUNITS (VH##HI, riscv_vector_chunks * NVECS * 4); \ - ADJUST_NUNITS (VS##SI, riscv_vector_chunks * NVECS * 2); \ - ADJUST_NUNITS (VD##DI, riscv_vector_chunks * NVECS); \ - ADJUST_NUNITS (VH##HF, riscv_vector_chunks * NVECS * 4); \ - ADJUST_NUNITS (VS##SF, riscv_vector_chunks * NVECS * 2); \ - ADJUST_NUNITS (VD##DF, riscv_vector_chunks * NVECS); \ + ADJUST_NUNITS (VB##QI, riscv_v_adjust_nunits (VB##QI##mode, NVECS * 8)); \ + ADJUST_NUNITS (VH##HI, riscv_v_adjust_nunits (VH##HI##mode, NVECS * 4)); \ + ADJUST_NUNITS (VS##SI, riscv_v_adjust_nunits (VS##SI##mode, NVECS * 2)); \ + ADJUST_NUNITS (VD##DI, riscv_v_adjust_nunits (VD##DI##mode, NVECS)); \ + ADJUST_NUNITS (VH##HF, riscv_v_adjust_nunits (VH##HF##mode, NVECS * 4)); \ + ADJUST_NUNITS (VS##SF, riscv_v_adjust_nunits (VS##SF##mode, NVECS * 2)); \ + ADJUST_NUNITS (VD##DF, riscv_v_adjust_nunits (VD##DF##mode, NVECS)); \ \ ADJUST_ALIGNMENT (VB##QI, 1); \ ADJUST_ALIGNMENT (VH##HI, 2); \ @@ -128,9 +131,9 @@ RVV_MODES (8, VNx64, VNx32, VNx16, VNx8) VECTOR_MODES_WITH_PREFIX (VNx, INT, 4, 0); VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 4, 0); -ADJUST_NUNITS (VNx4QI, riscv_vector_chunks * 4); -ADJUST_NUNITS (VNx2HI, riscv_vector_chunks * 2); -ADJUST_NUNITS (VNx2HF, riscv_vector_chunks * 2); +ADJUST_NUNITS (VNx4QI, riscv_v_adjust_nunits (VNx4QImode, 4)); +ADJUST_NUNITS (VNx2HI, riscv_v_adjust_nunits (VNx2HImode, 2)); +ADJUST_NUNITS (VNx2HF, riscv_v_adjust_nunits (VNx2HFmode, 2)); ADJUST_ALIGNMENT (VNx4QI, 1); ADJUST_ALIGNMENT (VNx2HI, 2); ADJUST_ALIGNMENT (VNx2HF, 2); @@ -139,28 +142,28 @@ ADJUST_ALIGNMENT (VNx2HF, 2); So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1SImode and VNx1SFmode. */ VECTOR_MODE_WITH_PREFIX (VNx, INT, SI, 1, 0); VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, SF, 1, 0); -ADJUST_NUNITS (VNx1SI, riscv_vector_chunks); -ADJUST_NUNITS (VNx1SF, riscv_vector_chunks); +ADJUST_NUNITS (VNx1SI, riscv_v_adjust_nunits (VNx1SImode, 1)); +ADJUST_NUNITS (VNx1SF, riscv_v_adjust_nunits (VNx1SFmode, 1)); ADJUST_ALIGNMENT (VNx1SI, 4); ADJUST_ALIGNMENT (VNx1SF, 4); VECTOR_MODES_WITH_PREFIX (VNx, INT, 2, 0); -ADJUST_NUNITS (VNx2QI, riscv_vector_chunks * 2); +ADJUST_NUNITS (VNx2QI, riscv_v_adjust_nunits (VNx2QImode, 2)); ADJUST_ALIGNMENT (VNx2QI, 1); /* 'VECTOR_MODES_WITH_PREFIX' does not allow ncomponents < 2. So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1HImode and VNx1HFmode. */ VECTOR_MODE_WITH_PREFIX (VNx, INT, HI, 1, 0); VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, HF, 1, 0); -ADJUST_NUNITS (VNx1HI, riscv_vector_chunks); -ADJUST_NUNITS (VNx1HF, riscv_vector_chunks); +ADJUST_NUNITS (VNx1HI, riscv_v_adjust_nunits (VNx1HImode, 1)); +ADJUST_NUNITS (VNx1HF, riscv_v_adjust_nunits (VNx1HFmode, 1)); ADJUST_ALIGNMENT (VNx1HI, 2); ADJUST_ALIGNMENT (VNx1HF, 2); /* 'VECTOR_MODES_WITH_PREFIX' does not allow ncomponents < 2. So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1QImode. */ VECTOR_MODE_WITH_PREFIX (VNx, INT, QI, 1, 0); -ADJUST_NUNITS (VNx1QI, riscv_vector_chunks); +ADJUST_NUNITS (VNx1QI, riscv_v_adjust_nunits (VNx1QImode, 1)); ADJUST_ALIGNMENT (VNx1QI, 1); /* TODO: According to RISC-V 'V' ISA spec, the maximun vector length can diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 386c0027ff4..5a718bb62b4 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -75,8 +75,8 @@ extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *); extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *); extern bool riscv_gpr_save_operation_p (rtx); extern void riscv_reinit (void); -extern bool riscv_v_ext_enabled_vector_mode_p (machine_mode); extern poly_uint64 riscv_regmode_natural_size (machine_mode); +extern bool riscv_v_ext_vector_mode_p (machine_mode); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index caeb97211f9..06a4a85087d 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -202,7 +202,7 @@ rvv_switcher::rvv_switcher () memcpy (m_old_have_regs_of_mode, have_regs_of_mode, sizeof (have_regs_of_mode)); for (int i = 0; i < NUM_MACHINE_MODES; ++i) - if (riscv_v_ext_enabled_vector_mode_p ((machine_mode) i)) + if (riscv_v_ext_vector_mode_p ((machine_mode) i)) have_regs_of_mode[i] = true; } @@ -271,7 +271,7 @@ register_builtin_type (vector_type_index type, tree eltype, machine_mode mode) builtin_types[type].scalar = eltype; builtin_types[type].scalar_ptr = build_pointer_type (eltype); builtin_types[type].scalar_const_ptr = build_const_pointer (eltype); - if (!riscv_v_ext_enabled_vector_mode_p (mode)) + if (!riscv_v_ext_vector_mode_p (mode)) return; tree vectype = build_vector_type_for_mode (eltype, mode); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1fd34f6ae8d..08354a19c05 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -944,30 +944,12 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode, return true; } -/* Return true if mode is the RVV mode. */ - -static bool -riscv_v_ext_vector_mode_p (machine_mode mode) -{ -#define ENTRY(MODE, REQUIREMENT) \ - case MODE##mode: \ - return true; - switch (mode) - { -#include "riscv-vector-switch.def" - default: - return false; - } - - return false; -} - /* Return true if mode is the RVV enabled mode. For example: 'VNx1DI' mode is disabled if MIN_VLEN == 32. 'VNx1SI' mode is enabled if MIN_VLEN == 32. */ bool -riscv_v_ext_enabled_vector_mode_p (machine_mode mode) +riscv_v_ext_vector_mode_p (machine_mode mode) { #define ENTRY(MODE, REQUIREMENT) \ case MODE##mode: \ @@ -982,6 +964,17 @@ riscv_v_ext_enabled_vector_mode_p (machine_mode mode) return false; } +/* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct + NUNITS size for corresponding machine_mode. */ + +poly_int64 +riscv_v_adjust_nunits (machine_mode mode, int scale) +{ + if (riscv_v_ext_vector_mode_p (mode)) + return riscv_vector_chunks * scale; + return scale; +} + /* Return true if X is a valid address for machine mode MODE. If it is, fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */ @@ -6423,7 +6416,7 @@ static bool riscv_vector_mode_supported_p (machine_mode mode) { if (TARGET_VECTOR) - return riscv_v_ext_enabled_vector_mode_p (mode); + return riscv_v_ext_vector_mode_p (mode); return false; } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 9dbc8463591..1385f0a16dc 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1019,6 +1019,7 @@ extern bool riscv_slow_unaligned_access_p; extern unsigned riscv_stack_boundary; extern unsigned riscv_bytes_per_vector_chunk; extern poly_uint16 riscv_vector_chunks; +extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); /* The number of bits and bytes in a RVV vector. */ #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8)) #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))