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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s5-20020a170902ea0500b001aad6d5f016si18598225plg.536.2023.05.15.14.16.25; Mon, 15 May 2023 14:16:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sberdevices.ru header.s=mail header.b="I5ov/cXh"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=sberdevices.ru Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245498AbjEOVGs (ORCPT + 99 others); Mon, 15 May 2023 17:06:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245483AbjEOVGk (ORCPT ); Mon, 15 May 2023 17:06:40 -0400 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8CA812E88; Mon, 15 May 2023 14:06:11 -0700 (PDT) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id 624C75FD1F; Tue, 16 May 2023 00:06:08 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1684184768; bh=qNExD4cQVfgTPKIe0gFBsDPUw9gYWD9Zk/g1cOXZaFk=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=I5ov/cXhqYiL1J8zNnOI/6TNi2wc/Nd7IKNzZTfbBDZkVIFgBPwqWrGWeXQ0wpuI/ SoEpM3sYnGbE+oguu3pssXaN9y4J3JYwE8heN6pRLl6AmSJD48sHXugKvPk3AX7Uyx LvNsR0EXS8Ro9lMIlCi6CgJrA07AvNXMKm9d8DLzMTQdmm1PXsJLvc1Lx1C/h1MQSm vp3i/637DlXl5rvowVo0Oy2w5JK8g+2OvswRdJ0uPJOLwgunxySInidRMKzVzkhfg7 W9VaCIq4vLk7Ke+hTfrlnyRgjaO9MqCHWjid+w+fmpPWThOZv0T5XPXco+jjq1HWCX U1D8ATr8iTL9Q== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Tue, 16 May 2023 00:06:06 +0300 (MSK) From: George Stark To: , , , , , , , CC: , , , , , Subject: [PATCH v1] meson saradc: fix clock divider mask length Date: Tue, 16 May 2023 00:05:45 +0300 Message-ID: <20230515210545.2100161-1-gnstark@sberdevices.ru> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2023/05/15 16:03:00 #21311645 X-KSMG-AntiVirus-Status: Clean, skipped X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765996390252092970?= X-GMAIL-MSGID: =?utf-8?q?1765996390252092970?= From: George Stark According to datasheets of supported meson SOCs length of ADC_CLK_DIV field is 6 bits long Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs") Signed-off-by: George Stark Reviewed-by: Neil Armstrong Reviewed-by: Martin Blumenstingl --- drivers/iio/adc/meson_saradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 85b6826cc10c..b93ff42b8c19 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -72,7 +72,7 @@ #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5 + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)