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Mon, 15 May 2023 13:16:30 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v14 1/8] dt-bindings: arm: add AMD Pensando boards Date: Mon, 15 May 2023 11:15:59 -0700 Message-ID: <20230515181606.65953-2-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230515181606.65953-1-blarson@amd.com> References: <20230515181606.65953-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT090:EE_|DM4PR12MB5198:EE_ X-MS-Office365-Filtering-Correlation-Id: 1e55fe76-910d-4256-3c8d-08db5570848e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: husvFtKWHgTDhSoT67CNj1jGvZg1++p5Of6XB45h37GNtE7An0jwVJHa+Udj5khZa1WPCGyKA26THU+6QV+yOPsdV+CVj07XmXavwBXYPzBLNBA6y/964FZKPy2dLdy72XOpL4zxVZcuEQUXx6aSFC3EKLMgYMbgAQPK5nXOMPnZY59cogiGTI2vESPn5g3cFWoywbqMiyZoTpqdJLbiJsO28/iGbDyEvWxDe0J8WE05Jn4wQZTeqr4pDwc9hL2gsllretqQmYEREvhO74P6FEaZUQa4J65+b/U9Sho/Zs+D1JFiCqyA+UmQ8MLec5svArCIW/Jbc7thNRDb/7Bw7Fu1KQkPKUQb3hq99PgmzzVNaE1OkUpPFJPylw4ugvZt57uVnIo6crZ/g25B01OgFDJRm4vqSy5Yxep/VPWJyOOZYWQ+sPAJmhgJ98sHwQ6AZSa2ZlRBZ+VoC4unBW+t0EysebDZtEAAzUSoR/jBmE7BuAsB1TEZ8mt7YW/hq5rjrsM7JpV3wiQS0+RrI1OFs8KXUrL19zOBdQ/SdmhVnNtETREczCUmZbQRC0RoFEEKSqw/4VbKpnctuyjplMMjROk+2jfNd5ybZ3/kMYTCrSfRVMDyT2m9eQjTZ/AvfONfABAFH2dZf0l9Mj3kUYQMOXcqJSnUaOoXiB+vQp4iHlKkN7TkaVHOrmlJZCgS3NsEEExDvYUdA1vntJCwfGR6xSQGeLRnRYl0QuOXPQnnu7BOeqW2EBsATlRFNlqZ+ll/3CRr+xjeXikg/x86tL0nEzTOospDZ8iW8f3EhjNXh0o= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(346002)(396003)(39860400002)(451199021)(40470700004)(46966006)(36840700001)(356005)(6916009)(82740400003)(4326008)(6666004)(8936002)(8676002)(316002)(40480700001)(41300700001)(70586007)(478600001)(70206006)(81166007)(54906003)(40460700003)(186003)(36756003)(16526019)(82310400005)(2616005)(1076003)(2906002)(26005)(47076005)(336012)(36860700001)(426003)(966005)(7406005)(5660300002)(7416002)(36900700001);DIR:OUT;SFP:1101; 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Signed-off-by: Brad Larson Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Documentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..e5c2591834a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... 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Mon, 15 May 2023 13:16:44 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v14 2/8] dt-bindings: spi: cdns: Add compatible for AMD Pensando Elba SoC Date: Mon, 15 May 2023 11:16:00 -0700 Message-ID: <20230515181606.65953-3-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230515181606.65953-1-blarson@amd.com> References: <20230515181606.65953-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT043:EE_|SN7PR12MB6744:EE_ X-MS-Office365-Filtering-Correlation-Id: 299b1ebc-ac28-447b-ca77-08db55708c65 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fTY8uVGAlXOXqXPes3TcLFaQ0nV56ZHZ4MKwAyqf0Qpa/Q325BXDUA3tH+5evvpTF9i0wpAsjSTjz05XnBIWxRsTH1M8gUKnfCWa61vrk3H+VjEYFhQwCPujJSLcIbrmsZQcwohRPYoyozqXZUKghZYmNmgiEXGKOlPHNCH7T2FERrVRh2VRZOGAgXKISQ3kvxenbx2Qlm1yIS7Ek1Qy9Tg8oXAds7AIq7HE/fm9IWuaGubW18+0sd1bb2oNgNyk44Xe8TbLgxOvn1XoVvcFA5iZnoHHr0SzoJ5flqxiZNTC/yWbUq3ZIA9dQu2aPLPqEa7l4hDyHVIv/pREZ8DrA/LgXFxtsG30pgb6zczc7ri26VnKwm76ZQgx8DkYTzcHqQO6i0cZEBUZKl5ckDGZCsJNTVN8KLtHta1c3jms1EQ3DAdnBMATgEHg18sn4myAwx47uXMhKPxJ9c6TcY4qMdjm81+8SFJ+EaDZbimVo2wjo8j/qHgeptAvLBA6U95D7McR9jqhGu0bXP64+OXfkDZ2z6r11gKceI2EVBvsgbZOIsACvGEe00pMpuSA9i74jAKMpLYC08WrIfs9Dp/cafapF1sF9Zhnk7fDU5uRelRWthzB78ISCdsMDg7phjJf2WY5s0aDF7RPiYP1aMOwPwXxij4eEmI7YItCUoeHUbgQK9Yv0FUjpbIUXVqws2svaY1afyD7jEW/VGkaIjE8wcZWTQ4V5b/bg8sxTtuDWs+I4DZFkhFE73uVogtHNzmvVISh/Xdo7kZFcxN7rAwipA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199021)(40470700004)(46966006)(36840700001)(36860700001)(70586007)(41300700001)(70206006)(47076005)(4326008)(6916009)(82740400003)(6666004)(26005)(82310400005)(1076003)(426003)(356005)(336012)(81166007)(316002)(2616005)(7406005)(7416002)(5660300002)(83380400001)(8676002)(8936002)(2906002)(478600001)(54906003)(40460700003)(40140700001)(186003)(40480700001)(16526019)(36756003)(36900700001);DIR:OUT;SFP:1101; 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The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski --- v14 changes: - Rebase to 6.4.0-rc1 v11 changes: - Removed redundant if/then for amd,pensando-elba-qspi v10 changes: - Fix cdns,fifo-depth, only amd,pensando-elba-qspi is 1024 bytes v9 changes: - Add 1024 to cdns,fifo-depth property to resolve dtbs_check error --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index b310069762dd..4f15f9a0cc34 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -46,12 +46,28 @@ allOf: maxItems: 2 items: enum: [ qspi, qspi-ocp ] + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + else: + properties: + cdns,fifo-depth: + enum: [ 128, 256 ] + default: 128 properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi @@ -76,8 +92,6 @@ properties: description: Size of the data FIFO in words. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [ 128, 256 ] - default: 128 cdns,fifo-width: $ref: /schemas/types.yaml#/definitions/uint32 From patchwork Mon May 15 18:16:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 94281 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp7108980vqo; Mon, 15 May 2023 11:21:43 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7QGWT6tcjPjZWFanaYWCrWfY8oLuq3VmxqUmuKV/7TxGvbJz8p1KBFeZRzyrha1kemYcS1 X-Received: by 2002:a17:902:c40b:b0:1aa:fd48:f5e2 with SMTP id k11-20020a170902c40b00b001aafd48f5e2mr46413972plk.32.1684174902760; Mon, 15 May 2023 11:21:42 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1684174902; cv=pass; d=google.com; s=arc-20160816; b=vM7XXol6XzV9CuTGOGdyV/ChdDhmyDA533H0hx/0K4R/nmwJDroTakQcBNk2s3AbMk IMYGLwq1mr4FIP/YJE3ch5xRktch2F6yKEfaxbqR46gWjdxFP2R4fZrUj68RIvsAT08X zw8GgX+nw0jWC+wU192LlAMl15iAIJpSIidsiV+mIV2vB6k7I93ErQxsuwwJQgS+uNN0 r4zo+O2sODAgl83vZmBHUMwg836BvnFu5+qhhgb5F7zwEJTI6MKGooemb4cpbAlzQ5z8 Ot/kVD4ympHFK8UOpzA2yZ+yg7OhhoTMSkmrapppPkruP5Xrqtprwzp2cf0suKO2q+n9 c/gg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=KIULXGIP/9zE9qKKh15P7DwPq8RDJ2/MG8LkZS1UI14=; b=S075Cr2GWZHQFEj8F175FoP68EnpzkJF8moffHVPWgBRjY3K6LFEqTjPTnTTMBchs1 EA3SB3gK0iBnBU+XD2rDgsCQpDnNp8f7szd8ACDPelVPUWvAjdoWHu7LegZs18M9863x ZYPHM3WzZapeDaKSwwJ7vFWqlFQrLlsgwOwdGkPYic3F+P1ggXJ3D4bH7nAB4b8MddNn 7CbeHT712Sk0j0CJo7x4c1mVFxfT7l1qBrR8gjfP1hK4BZ9n3gZD6GxuS2RZtWqkiSyE BDHeSDEzeczwdz86WF2Rl8n2WVUr4Hiyobso/awfY1J7Xc0UjYRnyy+lCgWnMDCmC4AP ULlw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=qrD0LIf7; arc=pass (i=1 spf=pass spfdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 15 May 2023 13:16:55 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v14 3/8] dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller Date: Mon, 15 May 2023 11:16:01 -0700 Message-ID: <20230515181606.65953-4-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230515181606.65953-1-blarson@amd.com> References: <20230515181606.65953-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT113:EE_|CH2PR12MB5018:EE_ X-MS-Office365-Filtering-Correlation-Id: 7137c1bb-4e8a-42e8-c313-08db55709385 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: e81CYaKJQW8SvGKyKnXh0mJBjgnfJq1T1Xxr+fCnV1RjRR3njUzOTaE0I+RwLNmQltAWrFpI8YnpJEehU5ORxE8uEKGxokydOHJamCgOcsIlXXK/k/Y5K/JfUTpucl+nBElDY9LggYzWri6IBPey49A01HESC58ZiGqrWJHdrocWBUnPHIJqRIFRZMSIDb6UlUJSTBbtfcp//M4v2r1H5ru3+ntzzhOc7oRThdhig9XDNo2XIv9kHfBVHupE9bVaij71imP8Kt4lz4Zjn49QRfX53slx/oSUDGTS26CQf8VGuiSRTrhMv7wsndmGIXqwgB04pPWkfO2TqOm4LTPZO49DJKI0dqt701VINe/ec8U9IiZOJYgM7a5BI+W9VZQPufVustM6b1OBVzMsm4jPLA4TgSqNszTKDcQjZlTSDJik45ldItvIcW4Dpl3ewM34fVRnaCqVry+xmgdjFtgFwdyPrN4YpQ7M+0N8GI6Xa/1DAcSwICjkhZMeKXexkrOLGt3iH9By3ATOQgWbCp8Aj5hSARX5n0NSvCwkUL22Qd84ZkO/BAKL15U/csRCV9tNr7iNzkKXpo4/Xai+rqTteArp67f3oB0688bA9wQlPq/zir/2n4Kodv59/VoezOvUl6wzN6XzZTe3/c9Iz2KgDC1OUbU9or5EmlMTBCl/USWNqx/4Hd8sC5skXY7vAnWJsDTTSzZAWvknboJmZW8aVCLbKOG/c7yLv7aYrniCZngWwNIOAjOp06U9u3bbvJ2hz8wxKqHphNFAkzA/aoWy7dvUcaaM4Nj9FszwN+J6YBU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(346002)(376002)(396003)(451199021)(46966006)(40470700004)(36840700001)(36756003)(54906003)(316002)(4326008)(6916009)(70206006)(70586007)(966005)(478600001)(426003)(81166007)(82310400005)(40480700001)(5660300002)(8676002)(8936002)(6666004)(2906002)(7406005)(7416002)(356005)(82740400003)(41300700001)(16526019)(2616005)(1076003)(186003)(26005)(36860700001)(83380400001)(336012)(47076005)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2023 18:17:00.1366 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7137c1bb-4e8a-42e8-c313-08db55709385 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT113.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5018 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765985382804950825?= X-GMAIL-MSGID: =?utf-8?q?1765985382804950825?= Support the AMD Pensando Elba SoC Controller which is a SPI connected device providing a miscellaneous set of essential board control/status registers. This device is present in all Pensando SoC based designs. Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski --- v14 changes: - Change GPL-2.0-only or BSD-2-Clause to GPL-2.0-only OR BSD-2-Clause v11 changes: - Fixed the compatible which should have stayed as 'amd,pensando-elba-ctrl', the commit message, and the filename - Reference spi-peripheral-props - Delete spi-max-frequency - Remove num-cs from example v10 changes: - Property renamed to amd,pensando-ctrl - Driver is renamed and moved to soc/drivers/amd affecting binding - Delete cs property, driver handles device node creation from parent num-cs fixing schema reg error in a different way v9 changes: - Instead of four nodes, one per chip-select, a single node is used with reset-cells in the parent. - No MFD API is used anymore in the driver so it made sense to move this to drivers/spi. - This driver is common for all Pensando SoC based designs so changed the name to pensando-sr.c to not make it Elba SoC specific. - Added property cs for the chip-select number which is used by the driver to create /dev/pensr0. --- .../soc/amd/amd,pensando-elba-ctrl.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml new file mode 100644 index 000000000000..e96978ad1e37 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amd/amd,pensando-elba-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Controller + +description: + The AMD Pensando Elba SoC Controller is a SPI connected device with essential + control/status registers accessed on chip select 0. This device is present + in all Pensando SoC based designs. + +maintainers: + - Brad Larson + +properties: + compatible: + enum: + - amd,pensando-elba-ctrl + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - '#reset-cells' + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + system-controller@0 { + compatible = "amd,pensando-elba-ctrl"; + reg = <0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; + }; + +... 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Signed-off-by: Brad Larson --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..3510daaabe27 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -236,6 +236,18 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 A-72 CPU cores, 144 programmable P4 + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Mon May 15 18:16:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 94283 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp7109902vqo; Mon, 15 May 2023 11:23:19 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ64yJHcsnaSguvaxl+5c5gSxYY8eBooglQ6wy0/Lz52BKpAoigk5HwkFzcWziLm8YmVy/yT X-Received: by 2002:a17:90b:1884:b0:250:c789:b133 with SMTP id mn4-20020a17090b188400b00250c789b133mr20121331pjb.1.1684174998886; Mon, 15 May 2023 11:23:18 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1684174998; cv=pass; d=google.com; s=arc-20160816; b=DYz82bQtZPurm1pqHJLoDML3PDu9p+sn/SllLyUJIzp8IFTjmcCNYeparnFyOEmsCu uKGLvtt4JNcOhJfykDxrT0OHMqCX3tRm83jVPSACBtnzfALaVP23ow0Hqj9mUOZgCyqk AZrIjXeuXhR1h07dp+3L//xsZd69AavnNFTo//ygVSEHqYFhNXOklDhYHd0jQb4WVygD l4c0KPuzc2aKnbB5Rp6CGVx51ZL9VV4nJKDyS9yPs2fX4tDiIu44YO3EhE2jeN7qEfIP zdjl3LX7wReOkWyXDullavdqKDrabnHtqdoQudZx2dfjA4/GNjAfQZx9nTvgcM07zwhe DmYQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qAHdgB+A196SFVe6rqviRZlvvt2tg6gjoxto4HHlJi0=; b=Ys9+j4ANnhq16aKmqoawH7meP8knm3I8tq3dY3UliYZ6I/xOxHV5z4tnYRDXGXDdTe 4ox+LRAZq354IyAFxrQr878V08BoQv16Mbajq8Hdg5F1rMtm7odxslVaN6FHKGa410nl ZFRIDdaDeVsjGzh9Cxx0QLa29itsm7SU7nY64rqZcsips+17p7X1XfXtJM/14aN9ciws FHsRTUuFvhYHSrRGgVeOVIGygLgPdGZU0XdNdRnXlEmhQSdJ+rsu5XXUHKw+95kHfJpo am1xIU5sZ8H2PfcbbE8n6amsAIlxWoSuTQx2XbiLrGua5haLlkf2+/RcdaeDJRvbuaRa ZpvQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=r7gT14ZD; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2023 18:17:35.8176 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73ed3e4d-1d1e-44fb-54f8-08db5570a8be X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4522 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765985483454261345?= X-GMAIL-MSGID: =?utf-8?q?1765985483454261345?= Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski --- v14 changes: - Fix dtbs_check l2-cache* property issue by adding required cache-level and cache-unified properties - Observed the issue after updating dtschema from 2023.1 to 2023.4 and yamllint from 1.26.3 to 1.30.0 v11 changes: - Delete reset-names - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl' v9 changes: - Single node for spi0 system-controller and squash the reset-controller child into parent --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 197 ++++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 +++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++++++++++ 6 files changed, 603 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile index 68103a8b0ef5..8502cc2afbc5 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi new file mode 100644 index 000000000000..f9f9f5fd5f69 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x0>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x1>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x2>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x3>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x100>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x101>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x102>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x103>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x200>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x201>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x202>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x203>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x300>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x301>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x302>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x303>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..1a615788f54e --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&ahb_clk { + clock-frequency = <400000000>; +}; + +&emmc_clk { + clock-frequency = <200000000>; +}; + +&flash_clk { + clock-frequency = <400000000>; +}; + +&ref_clk { + clock-frequency = <156250000>; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-hw-reset; + resets = <&rstc 0>; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + rstc: system-controller@0 { + compatible = "amd,pensando-elba-ctrl"; + reg = <0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts new file mode 100644 index 000000000000..c3f4da2f7449 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model = "AMD Pensando Elba Board"; + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..734893fef2c3 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "flash"; + reg = <0x10000 0xfff0000>; + }; + + partition@f0000 { + label = "golduenv"; + reg = <0xf0000 0x10000>; + }; + + partition@100000 { + label = "boot0"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "golduboot"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "brdcfg0"; + reg = <0x380000 0x10000>; + }; + + partition@390000 { + label = "brdcfg1"; + reg = <0x390000 0x10000>; + }; + + partition@400000 { + label = "goldfw"; + reg = <0x400000 0x3c00000>; + }; + + partition@4010000 { + label = "fwmap"; + reg = <0x4010000 0x20000>; + }; + + partition@4030000 { + label = "fwsel"; + reg = <0x4030000 0x20000>; + }; + + partition@4090000 { + label = "bootlog"; + reg = <0x4090000 0x20000>; + }; + + partition@40b0000 { + label = "panicbuf"; + reg = <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label = "uservars"; + reg = <0x40d0000 0x20000>; + }; + + partition@4200000 { + label = "uboota"; + reg = <0x4200000 0x400000>; + }; + + partition@4600000 { + label = "ubootb"; + reg = <0x4600000 0x400000>; + }; + + partition@4a00000 { + label = "mainfwa"; + reg = <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label = "mainfwb"; + reg = <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label = "diaguboot"; + reg = <0x6a00000 0x400000>; + }; + + partition@8000000 { + label = "diagfw"; + reg = <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label = "ubootenv"; + reg = <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi new file mode 100644 index 000000000000..674890cf2a34 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model = "Elba ASIC Board"; + compatible = "amd,pensando-elba"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + emmc_clk: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + flash_clk: oscillator3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ref_clk: oscillator4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@400 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x400 0x0 0x100>; + clocks = <&ahb_clk>; + #address-cells = <1>; + #size-cells = <0>; + i2c-sda-hold-time-ns = <480>; + interrupts = ; + status = "disabled"; + }; + + wdt0: watchdog@1400 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1400 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + + qspi: spi@2400 { + compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg = <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&flash_clk>; + cdns,fifo-depth = <1024>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x7fff0000>; + status = "disabled"; + }; + + spi0: spi@2800 { + compatible = "amd,pensando-elba-spi"; + reg = <0x0 0x2800 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + amd,pensando-elba-syscon = <&syscon>; + clocks = <&ahb_clk>; + interrupts = ; + num-cs = <2>; + status = "disabled"; + }; + + gpio0: gpio@4000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x4000 0x0 0x78>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + + uart0: serial@4800 { + compatible = "ns16550a"; + reg = <0x0 0x4800 0x0 0x100>; + clocks = <&ref_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + gic: interrupt-controller@800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + ranges; + interrupt-controller; + interrupts = ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells = <1>; + socionext,synquacer-pre-its = + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks = <&emmc_clk>; + interrupts = ; + cdns,phy-input-delay-sd-highspeed = <0x4>; + cdns,phy-input-delay-legacy = <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; + mmc-ddr-1_8v; + status = "disabled"; + }; + + syscon: syscon@307c0000 { + compatible = "amd,pensando-elba-syscon", "syscon"; + reg = <0x0 0x307c0000 0x0 0x3000>; + }; + }; +}; From patchwork Mon May 15 18:16:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 94282 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp7109462vqo; Mon, 15 May 2023 11:22:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6MW3STCsF2YpKA/WbDrTfsUfGTXIXo65gLj9lOhsrnRt+vhu+UTEL+UaNoKBtTeV/y3rT9 X-Received: by 2002:a05:6a00:1581:b0:646:59e4:9514 with SMTP id u1-20020a056a00158100b0064659e49514mr34850937pfk.7.1684174955216; Mon, 15 May 2023 11:22:35 -0700 (PDT) ARC-Seal: i=2; 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Mon, 15 May 2023 13:17:43 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v14 7/8] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Mon, 15 May 2023 11:16:05 -0700 Message-ID: <20230515181606.65953-8-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230515181606.65953-1-blarson@amd.com> References: <20230515181606.65953-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT071:EE_|IA1PR12MB7592:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fafd6c0-7389-4e27-f381-08db5570af98 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Uxysr0xdNe4uJ9ETbgW0IpQSKqgQn75WlDwPtev7xoQ7ihux+oNceRVsvNWUfFu495BhlbiDNLdsyZrZH1L1fmBtIK7BsgYT5+cDhYUrMsyGEZZiU5yLIbWnAm9hdnyvcod4aUgKvL9yHmQVJMghsmeOAN65dnuWesq+y/FwaJka3sNHnsu2NTSMdLlvvcvIiLmhJZAilU2l6Y/ejhe/blv0lIuvJh4rbtqqSCEXo48nLXG+eeA1P/2vCl+jOBG0PT8s24FB6ShoBJDT89DfZ/Wo4ZQjH4yQsMK169SeoEXnnE74SUfwe2dsC8F15bdu38cQO4kJeiG6kh5zmgYulQ1hSNg2QjO00/GxQCX+9EvAKVptKO3VtMuVAGTOX55mAcU46O2it6O/2JaDUu1yQGudAcnHQYBRDSBCt9Brtjx1OKhQ/dh9Lom3w0DMp67lhCI2MqLxEBnEBkDKBhz39gR2TpKKN9hSClJBUvo9XkeKqGDA4FEarcXM7gI2IDqg37ghHwHfe5kZmQIDZDR74wzBMz2zB6+yS0d+ZgPzSYb14ggAl40y1tjssrF6iPqft3WwPmC450D4+krA6XjE6nDg66uewAHVKDK0xexB6f7aSmTW32zbwQKjbns3PWuR1XZPmsJwpfsfnl6jnVKp+ZLijFA2txY4TS20Q/1TXl968W8bIjfg+h3DsQzj80SQKy9amHbcuMc5Z2qRLxbz7uE4FdUVqMFNomIwF3cfhqy2ApXletYAv60L2ACnn2Cc4xX0UywSRuCT5shVDjEzqQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(136003)(39860400002)(376002)(451199021)(46966006)(40470700004)(36840700001)(7406005)(2906002)(40460700003)(356005)(316002)(41300700001)(5660300002)(8936002)(7416002)(8676002)(36756003)(82310400005)(81166007)(40480700001)(6666004)(36860700001)(478600001)(426003)(336012)(1076003)(26005)(16526019)(186003)(2616005)(4326008)(47076005)(6916009)(82740400003)(70206006)(70586007)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2023 18:17:47.3166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8fafd6c0-7389-4e27-f381-08db5570af98 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT071.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7592 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765985437985274585?= X-GMAIL-MSGID: =?utf-8?q?1765985437985274585?= The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- v14 changes: - Rebase to linux-next 6.4.0-rc1 v9 changes: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 6ddb2dfc0f00..620316ab70ef 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -90,6 +91,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -1027,6 +1029,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1754,6 +1763,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1885,6 +1896,10 @@ static const struct cqspi_driver_platdata jh7110_qspi = { .quirks = CQSPI_DISABLE_DAC_MODE, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1914,6 +1929,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "starfive,jh7110-qspi", .data = &jh7110_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } }; From patchwork Mon May 15 18:16:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 94285 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp7111340vqo; Mon, 15 May 2023 11:26:08 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ67gbdxNjF38MK6pHpW62PROX2Et3c3W4PHCDTsgv6YwHV7zmWD2IgYB1E8q06AHW6E7+W1 X-Received: by 2002:a05:6a00:21d0:b0:643:bb16:7ca6 with SMTP id t16-20020a056a0021d000b00643bb167ca6mr44865509pfj.21.1684175168194; Mon, 15 May 2023 11:26:08 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1684175168; cv=pass; d=google.com; s=arc-20160816; b=GbW7+GbpIdlWdOG8uphf+ZxHkcplpidkNw4F8TWE58rYUFchHyl61NaTgl0Ef9AEt5 AMT9gipB3QegjZZxVCxqgpzjlxfgERnqDE0xk5mJ1jzd4rQOZ2BMGcbF7PfhUIMhHhd2 IVVogje/ktyf2Ld0St4bg3Qsz7PAGjMs3LYJW9vZW7H0GzReYB3TaHH86FHAWf9gf9B2 pBKqIMJtxWSUSpr6/9uZDBsVbchudZMHN+wrYC12s4rtc3UJIizJs0UP/EclB7cCwl8r rEJSPeJQG92HB9mTzCivH47XIBdpGNzxQ5TI6QmT9IrvgW7SxvvTmbKvln1Hz/I0JH/m 0ZtQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=5CkIvxNxNTRWPJZJDDm9uvAAIyqFTiT/zmC8YlU8Ql8=; b=TsydWm+4ryXdRozO1T1Qw6oMbNT2kXEallTmPnxuaEu6sThsqUVvOJ2OJje9MxQqB9 JQYtnj/VslOD2/XcCFIaPo0PUWvwSqBwjPG1Rlkk/Ph3EBMWE81wyeCRkdVsgEr1YR8M xkqfya0uLrR+kxSno5zz4Lpc+HvYkYSlGx0SWRodxbMRMehwAhQ7PUgrDpnMs3fhBP/B 4/0K0OyXPklIjNG0LPIjZEvXqh5kkaFlZTnroZ8Fk421pc+zbKq8sYvUfjgvkI/0fdvB 3nzk6QinIy827pOzXbBe0RAwbdLnTkDm3idaLzqMEyybOeu7kGaN7iYctkIpKXfFHQJR 8nYA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=GzLkrjo7; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 15 May 2023 13:17:56 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v14 8/8] soc: amd: Add support for AMD Pensando SoC Controller Date: Mon, 15 May 2023 11:16:06 -0700 Message-ID: <20230515181606.65953-9-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230515181606.65953-1-blarson@amd.com> References: <20230515181606.65953-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT106:EE_|DM4PR12MB6110:EE_ X-MS-Office365-Filtering-Correlation-Id: da4c14bb-570c-4f7e-4350-08db5570b7a8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gNrU24DRmY+C+ZINJs4TGHp2crS5qOBF0tqzdvTibxtujYp52MgmkF/LZTBcdfPn5lwytPoYeFZJcwJhJr4uioUUKrYB4XgLVhwiN7xnXWbf1ZGV4obE1Lraqy33RX8USze0w/Vz00sr5eTJctfJIZnsG6jYQSreefafG8dahhCCEWaGSNytB1z9wtxr3ToYBCLyNZVMWieeMoD85c0D9IpdxBEp47kveN+8MiE2U0Gk7bP3OlJn/BLcpIIUs3ocTZeYbyny8/0B4PoHhag4R+OwPwUUTk3+MNr+KRCpR7l87aF0DL94bEVwEP48p9PTTRYkKYHmLuBs6suWkgYzHG61zw/v1QEJ9+0gsPtXkcLxMdT6U7w9/0/TplfhWneRHp9NuEVFZTGPD7x/r2DQmcWkmct1LG5SUy7o33km+OopR8rGgcjS0/YCSJfwbKpi/SrwmayjO6YmUOJDwIwlxco1P+XmqAUSmjkfTTSXaChm8UMICOoB1SdtklyvMmNfS+W3VIlUIPnQwJumBwDO5ZGfk2iBMdfbtRHn7YIIRsgITW4IpfT3kBB1Jl8oLi7robTOYx1FLOd0l1M36qbpE0akdayA/s9YA+Iq7b78fTiMCtROrpQVP8lptW4rpXrbCW4CIWgkBVYAV8YSvAypSWWEAvKclt5vP5Cy8+poLrR5ngFXFxZ7d4lbxIlxPUCkUlEKWCyxSF0jkGdwAaIgMdIoeolbq8lOVXRizFTWLMDwirFP/kzSYpvKcCH/dfwNqG5TFukDU51YOvRNpIiTEw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(39860400002)(346002)(396003)(451199021)(40470700004)(36840700001)(46966006)(82740400003)(81166007)(356005)(2616005)(426003)(36860700001)(47076005)(1076003)(336012)(186003)(26005)(16526019)(40480700001)(83380400001)(2906002)(30864003)(41300700001)(5660300002)(7406005)(7416002)(8936002)(8676002)(36756003)(966005)(478600001)(6666004)(70586007)(70206006)(6916009)(316002)(4326008)(54906003)(82310400005)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2023 18:18:00.8388 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da4c14bb-570c-4f7e-4350-08db5570b7a8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6110 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765985661122194659?= X-GMAIL-MSGID: =?utf-8?q?1765985661122194659?= The Pensando SoC controller is a SPI connected companion device that is present in all Pensando SoC board designs. The essential board management registers are accessed on chip select 0 with board mgmt IO support accessed using additional chip selects. Signed-off-by: Brad Larson --- v14 changes: - Save 8 bytes of code size by swapping spi_device and reset_controller_dev in penctrl_device - Code simplification and clarity from review inputs - Set penctrl_spi_driver.driver.name to match compatible pensando-elba-ctrl - Remove unused include in amd-pensando-ctrl.h - Rebase to linux-next 6.4.0-rc1 class_create() API change v13 changes: - Update include list in pensando-ctrl.c - Change variable spi_dev to spi throughout - Removed unneeded variable initialization, simplification of error checks, remove extra castings, and use dev_err_probe() - Sort the includes in amd-pensando-ctrl.h - Updates to cleanup if there is an error in penctrl_spi_probe() v12 changes: - Fix gcc-12.1.0 warning: Reported-by: kernel test robot Link: https://lore.kernel.org/oe-kbuild-all/202303120925.SxLjwOd2-lkp@intel.com/ v11 changes: - Fix the compatible to be specific 'amd,pensando-elba-ctrl' v10 changes: - Different driver implementation specific to this Pensando controller device. - Moved to soc/amd directory under new name based on guidance. This driver is of no use to any design other than all Pensando SoC based cards. - Removed use of builtin_driver, can be built as a module. v9 changes: - Previously patch 14/17 - After the change to the device tree node and squashing reset-cells into the parent simplified this to not use any MFD API and move it to drivers/spi/pensando-sr.c. - Change the naming to remove elba since this driver is common for all Pensando SoC designs . - Default yes SPI_PENSANDO_SR for ARCH_PENSANDO --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/amd/Kconfig | 16 ++ drivers/soc/amd/Makefile | 2 + drivers/soc/amd/pensando-ctrl.c | 368 +++++++++++++++++++++++++ include/uapi/linux/amd-pensando-ctrl.h | 29 ++ 6 files changed, 417 insertions(+) create mode 100644 drivers/soc/amd/Kconfig create mode 100644 drivers/soc/amd/Makefile create mode 100644 drivers/soc/amd/pensando-ctrl.c create mode 100644 include/uapi/linux/amd-pensando-ctrl.h diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 4e176280113a..9e023f74e47c 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/actions/Kconfig" +source "drivers/soc/amd/Kconfig" source "drivers/soc/amlogic/Kconfig" source "drivers/soc/apple/Kconfig" source "drivers/soc/aspeed/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 3b0f9fb3b5c8..8914530f2721 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_ARCH_ACTIONS) += actions/ +obj-y += amd/ obj-y += apple/ obj-y += aspeed/ obj-$(CONFIG_ARCH_AT91) += atmel/ diff --git a/drivers/soc/amd/Kconfig b/drivers/soc/amd/Kconfig new file mode 100644 index 000000000000..011d5339d14e --- /dev/null +++ b/drivers/soc/amd/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "AMD Pensando SoC drivers" + +config AMD_PENSANDO_CTRL + tristate "AMD Pensando SoC Controller" + depends on SPI_MASTER=y + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + default ARCH_PENSANDO + select REGMAP_SPI + select MFD_SYSCON + help + Enables AMD Pensando SoC controller device support. This is a SPI + attached companion device in all Pensando SoC board designs which + provides essential board control/status registers and management IO + support. +endmenu diff --git a/drivers/soc/amd/Makefile b/drivers/soc/amd/Makefile new file mode 100644 index 000000000000..a2de0424f68d --- /dev/null +++ b/drivers/soc/amd/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_AMD_PENSANDO_CTRL) += pensando-ctrl.o diff --git a/drivers/soc/amd/pensando-ctrl.c b/drivers/soc/amd/pensando-ctrl.c new file mode 100644 index 000000000000..a7ddd181dfe8 --- /dev/null +++ b/drivers/soc/amd/pensando-ctrl.c @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Pensando SoC Controller + * + * Userspace interface and reset driver support for SPI connected Pensando SoC + * controller device. This device is present in all Pensando SoC designs and + * contains board control/status registers and management IO support. + * + * Copyright 2023 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct penctrl_device { + struct reset_controller_dev rcdev; + struct spi_device *spi; +}; + +static DEFINE_MUTEX(spi_lock); +static dev_t penctrl_devt; +static struct penctrl_device *penctrl; +static struct class *penctrl_class; + +static long +penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + void __user *in_arg = (void __user *)arg; + struct penctrl_device *penctrl; + u8 tx_buf[PENCTRL_MAX_MSG_LEN]; + u8 rx_buf[PENCTRL_MAX_MSG_LEN]; + struct spi_transfer t[2] = {}; + struct penctrl_spi_xfer *msg; + struct spi_device *spi; + unsigned int num_msgs; + struct spi_message m; + u32 size; + int ret; + + /* Check for a valid command */ + if (_IOC_TYPE(cmd) != PENCTRL_IOC_MAGIC) + return -ENOTTY; + + if (_IOC_NR(cmd) > PENCTRL_IOC_MAXNR) + return -ENOTTY; + + if (((_IOC_DIR(cmd) & _IOC_READ)) && !access_ok(in_arg, _IOC_SIZE(cmd))) + return -EFAULT; + + if (((_IOC_DIR(cmd) & _IOC_WRITE)) && !access_ok(in_arg, _IOC_SIZE(cmd))) + return -EFAULT; + + /* Get a reference to the SPI device */ + penctrl = filp->private_data; + if (!penctrl) + return -ESHUTDOWN; + + spi = spi_dev_get(penctrl->spi); + if (!spi) + return -ESHUTDOWN; + + /* Verify and prepare SPI message */ + size = _IOC_SIZE(cmd); + num_msgs = size / sizeof(struct penctrl_spi_xfer); + if (num_msgs > 2 || size == 0 || size % sizeof(struct penctrl_spi_xfer)) { + ret = -EINVAL; + goto out_unlock; + } + msg = memdup_user((struct penctrl_spi_xfer *)arg, size); + if (IS_ERR(msg)) { + ret = PTR_ERR(msg); + goto out_unlock; + } + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret = -EINVAL; + goto out_unlock; + } + + t[0].tx_buf = tx_buf; + t[0].len = msg->len; + if (copy_from_user(tx_buf, (void __user *)msg->tx_buf, msg->len)) { + ret = -EFAULT; + goto out_unlock; + } + if (num_msgs > 1) { + msg++; + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret = -EINVAL; + goto out_unlock; + } + t[1].rx_buf = rx_buf; + t[1].len = msg->len; + } + spi_message_init_with_transfers(&m, t, num_msgs); + + /* Perform the transfer */ + mutex_lock(&spi_lock); + ret = spi_sync(spi, &m); + mutex_unlock(&spi_lock); + + if (ret || (num_msgs == 1)) + goto out_unlock; + + if (copy_to_user((void __user *)msg->rx_buf, rx_buf, msg->len)) + ret = -EFAULT; + +out_unlock: + spi_dev_put(spi); + return ret; +} + +static int penctrl_open(struct inode *inode, struct file *filp) +{ + struct spi_device *spi; + u8 current_cs; + + filp->private_data = penctrl; + current_cs = iminor(inode); + spi = penctrl->spi; + spi->chip_select = current_cs; + spi->cs_gpiod = spi->controller->cs_gpiods[current_cs]; + spi_setup(spi); + return stream_open(inode, filp); +} + +static int penctrl_release(struct inode *inode, struct file *filp) +{ + filp->private_data = NULL; + return 0; +} + +static const struct file_operations penctrl_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = penctrl_ioctl, + .open = penctrl_open, + .release = penctrl_release, + .llseek = no_llseek, +}; + +static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val) +{ + struct spi_device *spi = penctrl->spi; + struct spi_transfer t[2] = {}; + struct spi_message m; + u8 txbuf[3]; + u8 rxbuf[1]; + int ret; + + txbuf[0] = PENCTRL_SPI_CMD_REGRD; + txbuf[1] = reg; + txbuf[2] = 0; + t[0].tx_buf = txbuf; + t[0].len = sizeof(txbuf); + + rxbuf[0] = 0; + t[1].rx_buf = rxbuf; + t[1].len = sizeof(rxbuf); + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret = spi_sync(spi, &m); + if (ret == 0) + *val = rxbuf[0]; + + return ret; +} + +static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val) +{ + struct spi_device *spi = penctrl->spi; + struct spi_transfer t = {}; + struct spi_message m; + u8 txbuf[4]; + + txbuf[0] = PENCTRL_SPI_CMD_REGWR; + txbuf[1] = reg; + txbuf[2] = val; + txbuf[3] = 0; + + t.tx_buf = txbuf; + t.len = sizeof(txbuf); + spi_message_init_with_transfers(&m, &t, 1); + return spi_sync(spi, &m); +} + +static int penctrl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl = + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi = penctrl->spi; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi->chip_select = 0; + spi->cs_gpiod = spi->controller->cs_gpiods[0]; + spi_setup(spi); + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi->dev, "error reading ctrl0 reg\n"); + goto out_unlock; + } + + val |= BIT(6); + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi->dev, "error writing ctrl0 reg\n"); + +out_unlock: + mutex_unlock(&spi_lock); + return ret; +} + +static int penctrl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl = + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi = penctrl->spi; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi->chip_select = 0; + spi->cs_gpiod = spi->controller->cs_gpiods[0]; + spi_setup(spi); + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi->dev, "error reading ctrl0 reg\n"); + goto out_unlock; + } + + val &= ~BIT(6); + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi->dev, "error writing ctrl0 reg\n"); + +out_unlock: + mutex_unlock(&spi_lock); + return ret; +} + +static const struct reset_control_ops penctrl_reset_ops = { + .assert = penctrl_reset_assert, + .deassert = penctrl_reset_deassert, +}; + +static int penctrl_spi_probe(struct spi_device *spi) +{ + struct device *dev; + struct cdev *cdev; + u32 num_cs; + int ret; + u32 cs; + + ret = device_property_read_u32(spi->dev.parent, "num-cs", &num_cs); + if (ret) + return dev_err_probe(&spi->dev, ret, + "number of chip-selects not defined\n"); + + ret = alloc_chrdev_region(&penctrl_devt, 0, num_cs, "penctrl"); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to alloc chrdev region\n"); + + penctrl_class = class_create("penctrl"); + if (IS_ERR(penctrl_class)) { + ret = dev_err_probe(&spi->dev, PTR_ERR(penctrl_class), + "failed to create class\n"); + goto unregister_chrdev; + } + + cdev = cdev_alloc(); + if (!cdev) { + ret = dev_err_probe(&spi->dev, -ENOMEM, + "allocation of cdev failed\n"); + goto destroy_class; + } + cdev->owner = THIS_MODULE; + cdev_init(cdev, &penctrl_fops); + + ret = cdev_add(cdev, penctrl_devt, num_cs); + if (ret) { + ret = dev_err_probe(&spi->dev, ret, + "register of cdev failed\n"); + goto free_cdev; + } + + /* Allocate driver data */ + penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL); + if (!penctrl) { + ret = -ENOMEM; + goto free_cdev; + } + penctrl->spi = spi; + mutex_init(&spi_lock); + + /* Create a device for each chip select */ + for (cs = 0; cs < num_cs; cs++) { + dev = device_create(penctrl_class, + &spi->dev, + MKDEV(MAJOR(penctrl_devt), cs), + penctrl, + "penctrl0.%d", + cs); + if (IS_ERR(dev)) { + ret = dev_err_probe(&spi->dev, PTR_ERR(dev), + "error creating device\n"); + goto destroy_device; + } + dev_dbg(&spi->dev, "created device major %u, minor %d\n", + MAJOR(penctrl_devt), cs); + } + + /* Register reset controller */ + penctrl->rcdev.dev = &spi->dev; + penctrl->rcdev.ops = &penctrl_reset_ops; + penctrl->rcdev.owner = THIS_MODULE; + penctrl->rcdev.of_node = spi->dev.of_node; + penctrl->rcdev.nr_resets = 1; + + ret = reset_controller_register(&penctrl->rcdev); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to register reset controller\n"); + return 0; + +destroy_device: + for (cs = 0; cs < num_cs; cs++) + device_destroy(penctrl_class, MKDEV(MAJOR(penctrl_devt), cs)); + kfree(penctrl); +free_cdev: + cdev_del(cdev); +destroy_class: + class_destroy(penctrl_class); +unregister_chrdev: + unregister_chrdev(MAJOR(penctrl_devt), "penctrl"); + + return ret; +} + +static const struct of_device_id penctrl_dt_match[] = { + { .compatible = "amd,pensando-elba-ctrl" }, + { /* sentinel */ } +}; + +static struct spi_driver penctrl_spi_driver = { + .probe = penctrl_spi_probe, + .driver = { + .name = "pensando-elba-ctrl", + .of_match_table = penctrl_dt_match, + }, +}; +module_spi_driver(penctrl_spi_driver); + +MODULE_AUTHOR("Brad Larson "); +MODULE_DESCRIPTION("AMD Pensando SoC Controller via SPI"); +MODULE_LICENSE("GPL"); diff --git a/include/uapi/linux/amd-pensando-ctrl.h b/include/uapi/linux/amd-pensando-ctrl.h new file mode 100644 index 000000000000..e5f9f0dfe146 --- /dev/null +++ b/include/uapi/linux/amd-pensando-ctrl.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Userspace interface for /dev/penctrl + * + * This file can be used by applications that need to communicate + * with the AMD Pensando SoC controller device via the ioctl interface. + */ +#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H +#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H + +#include + +#define PENCTRL_SPI_CMD_REGRD 0x0b +#define PENCTRL_SPI_CMD_REGWR 0x02 +#define PENCTRL_IOC_MAGIC 'k' +#define PENCTRL_IOC_MAXNR 0 +#define PENCTRL_MAX_MSG_LEN 16 +#define PENCTRL_MAX_REG 0xff +#define PENCTRL_REG_CTRL0 0x10 + +struct penctrl_spi_xfer { + __u64 tx_buf; + __u64 rx_buf; + __u32 len; + __u32 speed_hz; + __u64 compat; +}; + +#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */