From patchwork Mon May 15 09:32:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 94021 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp6790764vqo; Mon, 15 May 2023 02:44:48 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7BUVGY8c1GL/ftDvMjuj+IWUuDru2jX4iqiG/vJjmkX6+OBUO9rlXkp2EI43IfFM6PdUw1 X-Received: by 2002:a05:6a20:8f22:b0:ff:c184:7c6b with SMTP id b34-20020a056a208f2200b000ffc1847c6bmr36599895pzk.10.1684143888598; Mon, 15 May 2023 02:44:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684143888; cv=none; d=google.com; s=arc-20160816; b=PoDScPmPYzxuSmasBmdU2G2R51jUQ9+/NUVfseGfVH/5t98QEzBKgkCG/U80qlaApS IK+xTfe8bW4DjpQAjJzfhqTgk+LXkfqFjeVvxHgfIxfraGeGeludBH1y+fkAUwgrinwi hudY4Ji+Go9+VE/Q/keNJiaHpog1ZmHyPqUnF7sNh+1e6v7tjJihUpNwDmpeNnxqvqVE mDzypHOSzN6nCZeU8Go6SvNGmL9P5SI2+f7YyLks+5O5TdSY4FBH44ziQRjqi+2iYOQ+ 3dQqI9VW2IE6/vGCeoFpiOfqFfL8hJVNGcuXVQVawfr4EhIGoF4nEukzECrHPcOWaFmt GhNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=5SVB2of+oiM6itMzNdFjRlfgyCbdWSn05lTZxyQBgdo=; b=jQ9xZiaL7FGE8fbUDBacy3LjkUrVUfRJOr4EkDswnoMUcHLo/bt9gU4EcmvNl1pmgJ Gmo8KQJVPhVASduGfyMPsjuB2fmuvNeSJG93b4ovDUjj9S4nhp+uxqySkt8UbJzYLw5N /OEtvZGfo9FMwUCw2agEuHGOsPPukcRa4dnP07VWw17pA55JFmrWRjM+I+xSI1e+hG+s tGTdOUzjjHJqdGLCMZAuFhTcMfM8GXslS9Y5nlzJtIrgxQ1yss7Xq/lvONNTMWLsY+zU Si0oonghUA798bfiqgHTcpyEaLL6xZSKdp5tB2/onSMzPZxA7KOPKkPsgJNCpN5JIi5h eLHg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=amlogic.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x26-20020aa7941a000000b006463201bb55si16890420pfo.325.2023.05.15.02.44.36; Mon, 15 May 2023 02:44:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=amlogic.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234709AbjEOJd3 (ORCPT + 99 others); Mon, 15 May 2023 05:33:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234022AbjEOJd1 (ORCPT ); Mon, 15 May 2023 05:33:27 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E401DA7; Mon, 15 May 2023 02:32:43 -0700 (PDT) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 15 May 2023 17:32:32 +0800 From: Xianwei Zhao To: , , , CC: Catalin Marinas , Will Deacon , Neil Armstrong , Kevin Hilman , Rob Herring , Krzysztof Kozlowski , Xianwei Zhao Subject: [PATCH V5] arm64: dts: add support for C3 based Amlogic AW409 Date: Mon, 15 May 2023 17:32:37 +0800 Message-ID: <20230515093237.2203171-1-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765952862393678501?= X-GMAIL-MSGID: =?utf-8?q?1765952862393678501?= Amlogic C3 is an advanced edge AI processor designed for smart IP camera applications. Add basic support for the C3 based Amlogic AW409 board, which describes the following components: CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Xianwei Zhao --- Link: https://lore.kernel.org/all/20230407102704.1055152-1-kelvin.zhang@amlogic.com V4 -> V5: Use string 'meson-s4-uart' instead of 'meson-g12a-uart'. V3 -> V4: Move Link under the --- before the changelog. V2 -> V3: Remove '256m' from filename; Keep alphabetical order of Makefile. V1 -> V2: Remove new arch, and use ARCH_MESON; Modify node name, and delete superfluous blank line. --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/amlogic-c3-c302x-aw409.dts | 29 +++++++ arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 87 +++++++++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi base-commit: ae68fb187b59bc8645974320808ab2d7c41b1833 diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index cd1c5b04890a..6f61798a109f 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts new file mode 100644 index 000000000000..edce8850b338 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-c3.dtsi" + +/ { + model = "Amlogic C302 aw409 Development Board"; + compatible = "amlogic,aw409", "amlogic,c3"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_b; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x10000000>; + }; +}; + +&uart_b { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi new file mode 100644 index 000000000000..60ad4f3eef9d --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + interrupts = ; + }; + + apb4: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_b: serial@7a000 { + compatible = "amlogic,meson-s4-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x7a000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + + }; + }; +};