From patchwork Mon Oct 24 19:36:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 10322 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp667996wru; Mon, 24 Oct 2022 14:53:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4tAqh3/B9Rh7RngUYkJQPYRLiZ0qs3GKieNOii2Rdvvnr1UjTY5Bm2HhXRPEsRZCwl+FGX X-Received: by 2002:a17:90b:4acd:b0:212:fe7a:a05a with SMTP id mh13-20020a17090b4acd00b00212fe7aa05amr11346132pjb.204.1666648408703; Mon, 24 Oct 2022 14:53:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666648408; cv=none; d=google.com; s=arc-20160816; b=rREPmLZz7hOwiOr3c+qNIS6kzRIH3ei7zqDdilfT98oisLy2OfbBqW5800fKpm/kc6 8W3nOUrkm4uid9EwDP1fZ/CDyQd3DEsH4v3PpM8C5pkZ5FjOChxgXE137z/fc5MebxZZ yL0lp/0vgUrCZoQ5ZqI++PAyopy9ZIWw+Y6FzaB/7hXbRtLimFrejhp6pANhPfJ/n7MK V7Ed2rM5IVtu/fm5J6R0WwC/UN6XT6FEyXpYPhBhWWL6aQgaw/veFNvxQNrziK/EhD/E Q5ZeMBSWTnV8f8elHpibvkR1VrQTD8XWdfy+dQ4qzsw+DRPdwbR/B70kTJuaybDWeBER gMkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=TvvUg66FkZA/jlWsd09gLcRXmXmiRfM/nFLTdVpZjhQ=; b=XnFGRelhSOa0zsRQ8T1QCV+J0hg5XphLUVEIg/fMrnNVg4E58D8NPolRhN0Y4OMQMI PGrqnVJfOKy7/MaRFJryiuuwrAatmoPj8x4Po5tFiR56DbEPyl09PPuv0Jo88GQ8eUz0 hmFcyXynHFwks1mvOc1cGf58d5xMzZ5t2M4aSX+U7AsA2vzOyI2Du53ZdyhRdongd/jM o5xi5TbMNYak1nwqH7KcfvqGWIcqBZZQ1CMNXFuLUKgwxdjFVtlaabqTBsNh3RZKrrzX lkTXt5sAoPP8xynTzFXwd2KEzT8ujurMu6gwAjfQasmaoGTHV4dYyrjBWGy8ysduJwVZ fztA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ALITZss1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f6-20020a655906000000b0045135f6da29si692008pgu.581.2022.10.24.14.53.15; Mon, 24 Oct 2022 14:53:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ALITZss1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231965AbiJXVdC (ORCPT + 99 others); Mon, 24 Oct 2022 17:33:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229671AbiJXVcc (ORCPT ); Mon, 24 Oct 2022 17:32:32 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDCA2186DD; Mon, 24 Oct 2022 12:39:24 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D5E8661575; Mon, 24 Oct 2022 19:37:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB923C433C1; Mon, 24 Oct 2022 19:37:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666640271; bh=GTzGyK5ICOdcW3TRbCJOV0+yXyHnU9QoAMm0ZKS8v1c=; h=From:To:Cc:Subject:Date:From; b=ALITZss1pRbrMLdGnnQCScYQIAox+NcvETAU1maabpqGSPYDt06K5VvFXuzFOtgAT jnUpj/4Kf8pzKh4YkR7sbKknASD6DgQJlDKWscUF7ErS2PwmolbpJ9NUFUdmUwPueA IgF7ZhjNzcHl46dHOByqrTfML814kg079KcqiHjuFhr0eCyyMuHY88XK1LI1SosyT8 RmlTXj2E59MkGAh/Mzcf3gbOXYexxeuJM6dfHGmjSxYb//EvbyHfzjWvSzb+x1fBhP b7wI7EEXjwuDvwVeQRYKT5m20PvJ5Knq12gE3A7rfbPy826UEx4gyTJI5LksnTxp+5 h0pKCrJ70TL/g== From: Conor Dooley To: Conor Dooley Cc: Daire McNamara , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Padmarao Begari Subject: [RFC] riscv: dts: microchip: add OPPs to mpfs Date: Mon, 24 Oct 2022 20:36:48 +0100 Message-Id: <20221024193647.1089769-1-conor@kernel.org> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747607521790466175?= X-GMAIL-MSGID: =?utf-8?q?1747607521790466175?= From: Conor Dooley The U-Boot dts for mpfs defines three OPPs which are missing from the Linux dts. For ease of synchronisation of the two, add the missing OPPs to the Linux dt too. CC: Padmarao Begari Signed-off-by: Conor Dooley --- Hey Padmarao, I've been trying to pick off the bits that're different between the Linux & U-Boot dts. Do you remember why we added OPPs to the U-Boot dts but didn't propagate them elsewhere? arch/riscv/boot/dts/microchip/mpfs.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 0a9bb84af438..9d9ff7174341 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -23,6 +23,7 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; clocks = <&clkcfg CLK_CPU>; + operating-points-v2 = <&cluster0_opps>; status = "disabled"; cpu0_intc: interrupt-controller { @@ -51,6 +52,7 @@ cpu1: cpu@1 { clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; + operating-points-v2 = <&cluster0_opps>; status = "okay"; cpu1_intc: interrupt-controller { @@ -79,6 +81,7 @@ cpu2: cpu@2 { clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; + operating-points-v2 = <&cluster0_opps>; status = "okay"; cpu2_intc: interrupt-controller { @@ -107,6 +110,7 @@ cpu3: cpu@3 { clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; + operating-points-v2 = <&cluster0_opps>; status = "okay"; cpu3_intc: interrupt-controller { @@ -136,6 +140,7 @@ cpu4: cpu@4 { tlb-split; next-level-cache = <&cctrllr>; status = "okay"; + operating-points-v2 = <&cluster0_opps>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -166,6 +171,24 @@ core4 { }; }; }; + + cluster0_opps: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000>; + }; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <750000>; + }; + }; }; refclk: mssrefclk {