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Mon, 24 Oct 2022 14:22:06 -0500 From: Hamza Mahfooz To: CC: Roman Li , Hamza Mahfooz , "Harry Wentland" , Leo Li , "Rodrigo Siqueira" , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Nicholas Kazlauskas , Aurabindo Pillai , Fangzhi Zuo , Wayne Lin , Lyude Paul , Ian Chen , Claudio Suarez , Colin Ian King , hersen wu , , Subject: [PATCH 1/3] drm/edid: add a quirk for two LG monitors to get them to work on 10bpc Date: Mon, 24 Oct 2022 15:22:21 -0400 Message-ID: <20221024192224.180507-1-hamza.mahfooz@amd.com> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000C403:EE_|CH0PR12MB5156:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c4de3bf-299e-4077-0122-08dab5f50b2e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 19:22:08.5057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c4de3bf-299e-4077-0122-08dab5f50b2e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000C403.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5156 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747605651218179463?= X-GMAIL-MSGID: =?utf-8?q?1747605651218179463?= The LG 27GP950 and LG 27GN950 have visible display corruption when trying to use 10bpc modes. So, to fix this, cap their maximum DSC target bitrate to 15bpp. Suggested-by: Roman Li Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/drm_edid.c | 12 ++++++++++++ include/drm/drm_connector.h | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index bc43e1b32092..f4f96115dce7 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -91,6 +91,8 @@ static int oui(u8 first, u8 second, u8 third) #define EDID_QUIRK_FORCE_10BPC (1 << 11) /* Non desktop display (i.e. HMD) */ #define EDID_QUIRK_NON_DESKTOP (1 << 12) +/* Cap the DSC target bitrate to 15bpp */ +#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) #define MICROSOFT_IEEE_OUI 0xca125c @@ -151,6 +153,12 @@ static const struct edid_quirk { EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | EDID_QUIRK_DETAILED_IN_CM), + /* LG 27GP950 */ + EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), + + /* LG 27GN950 */ + EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), + /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), @@ -5511,6 +5519,7 @@ drm_reset_display_info(struct drm_connector *connector) info->mso_stream_count = 0; info->mso_pixel_overlap = 0; + info->max_dsc_bpp = 0; } u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) @@ -5595,6 +5604,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi info->non_desktop = true; } + if (quirks & EDID_QUIRK_CAP_DSC_15BPP) + info->max_dsc_bpp = 15; + return quirks; } diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 3ac4bf87f257..7a8fb486b6ab 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -634,6 +634,12 @@ struct drm_display_info { * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels. */ u8 mso_pixel_overlap; + + /** + * @max_dsc_bpp: Maximum DSC target bitrate, if it is set to 0 the + * monitor's default value is used instead. + */ + u32 max_dsc_bpp; }; int drm_display_info_set_bus_formats(struct drm_display_info *info, From patchwork Mon Oct 24 19:22:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hamza Mahfooz X-Patchwork-Id: 10318 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp659201wru; Mon, 24 Oct 2022 14:27:27 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7os/B0ZAddTMvUkWwVZY/hS7a+jTQUdZR4uQqv4K3vd66G+tJcNQhiKjbJ9c4I12NHwD3C X-Received: by 2002:a17:907:e93:b0:78d:b8ff:9b5f with SMTP id ho19-20020a1709070e9300b0078db8ff9b5fmr29739536ejc.12.1666646847252; Mon, 24 Oct 2022 14:27:27 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666646847; cv=pass; d=google.com; s=arc-20160816; b=qAVLzR0IoBzPuvfhhgbEn8eYSPuccb4hVaAW/G+qi2fTASVjZvltxigbD+iJWjAUMq iFszHyaKAu2DQJoU0crRjL93Jkbgo9hsCprW+5nt454MU41Ue5anL2MfhHiDMNNcawGa i1EduV5KYrAt5K/lS4eVOpUJfjqu0ofAYEteoge8pJFLlN8TSrwrQDAYuutt1zklxAQE Y+JhfuN7mgyqn2+/PAZk789kJWdr6GHHFK7JdhOyct8aT11OUQK+BiE5+L0tZsOLmyWh 1TtcQu1ov9Npfw9bmHlbou0Y9ib7yVeQu/8QwpUSNWLT5ZcalGo0NsLe5YcIFH16njff Dmrg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cMnXVaY5RyOYqYXy5gC6NAtXTn+KN1+YVIUuZP1m2vo=; b=nIVCwZwOkEqS6+LQ8KyciWvM2kFDDIH4vSBe5nY2JPLmFPf/dk2xr1h2GxrUFZvWBx mRg4+NPTk039TcJSYL+tEwd4wbqKrxgQ1HrppaaNVX2URT4xryVTZjPqL87TOl2GLq8G Wa8NP4IM10udr5lOWgWpigE43TC5sOwlSIWfm5pzo4jjhPWEf6w2pNHyaJi7HBRrvRq2 MCbm5uAYZhERJh6og/5mIQinaaFaevM5gqbANZIP2L4LIpvleHbgmMPbRvvX0T2z4QdJ sJ14/ZMjTvfi5R5cgz0hgl2P4CB0qQMPXo6CYWUSM3QgPHogIwAaWSA8CMSytyCEUHIk rHyg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="XTW2o5/U"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 24 Oct 2022 14:22:11 -0500 From: Hamza Mahfooz To: CC: Roman Li , Hamza Mahfooz , "Harry Wentland" , Leo Li , "Rodrigo Siqueira" , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Nicholas Kazlauskas , Aurabindo Pillai , Wayne Lin , Fangzhi Zuo , Lyude Paul , Ian Chen , Mikita Lipski , Claudio Suarez , Colin Ian King , hersen wu , , Subject: [PATCH 2/3] drm/amd/display: use max_dsc_bpp in amdgpu_dm Date: Mon, 24 Oct 2022 15:22:22 -0400 Message-ID: <20221024192224.180507-2-hamza.mahfooz@amd.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221024192224.180507-1-hamza.mahfooz@amd.com> References: <20221024192224.180507-1-hamza.mahfooz@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000C403:EE_|SJ0PR12MB5662:EE_ X-MS-Office365-Filtering-Correlation-Id: 92db5140-9e84-4811-f9c3-08dab5f50dea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++---- .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 11 +++++++++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 63f076a46260..9b9cca8cb71a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5618,16 +5618,14 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, { struct drm_connector *drm_connector = &aconnector->base; uint32_t link_bandwidth_kbps; - uint32_t max_dsc_target_bpp_limit_override = 0; struct dc *dc = sink->ctx->dc; uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps; uint32_t dsc_max_supported_bw_in_kbps; + uint32_t max_dsc_target_bpp_limit_override = + drm_connector->display_info.max_dsc_bpp; link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)); - if (stream->link && stream->link->local_sink) - max_dsc_target_bpp_limit_override = - stream->link->local_sink->edid_caps.panel_patch.max_dsc_target_bpp_limit; /* Set DSC policy according to dsc_clock_en */ dc_dsc_policy_set_enable_dsc_when_not_needed( diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ce6929224a6e..eb42c0e21a28 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -670,15 +670,18 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p int count, int k) { + struct drm_connector *drm_connector; int i; for (i = 0; i < count; i++) { + drm_connector = ¶ms[i].aconnector->base; + memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); if (vars[i + k].dsc_enabled && dc_dsc_compute_config( params[i].sink->ctx->dc->res_pool->dscs[0], ¶ms[i].sink->dsc_caps.dsc_dec_caps, params[i].sink->ctx->dc->debug.dsc_min_slice_height_override, - params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit, + drm_connector->display_info.max_dsc_bpp, 0, params[i].timing, ¶ms[i].timing->dsc_cfg)) { @@ -720,12 +723,16 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) struct dc_dsc_config dsc_config; u64 kbps; + struct drm_connector *drm_connector = ¶m.aconnector->base; + uint32_t max_dsc_target_bpp_limit_override = + drm_connector->display_info.max_dsc_bpp; + kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); dc_dsc_compute_config( param.sink->ctx->dc->res_pool->dscs[0], ¶m.sink->dsc_caps.dsc_dec_caps, param.sink->ctx->dc->debug.dsc_min_slice_height_override, - param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit, + max_dsc_target_bpp_limit_override, (int) kbps, param.timing, &dsc_config); return dsc_config.bits_per_pixel; From patchwork Mon Oct 24 19:22:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hamza Mahfooz X-Patchwork-Id: 10316 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp657608wru; Mon, 24 Oct 2022 14:22:02 -0700 (PDT) X-Google-Smtp-Source: AMsMyM69JlPYzuMlrGShLqmmQI/UBilxcQ5/bL52+rfUCqRSMWumVdRA3U6PLqyZvq6biXL1bcdi X-Received: by 2002:a17:902:e545:b0:184:2f27:b34 with SMTP id n5-20020a170902e54500b001842f270b34mr34883369plf.15.1666646521756; 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Mon, 24 Oct 2022 14:22:15 -0500 From: Hamza Mahfooz To: CC: Roman Li , Hamza Mahfooz , "Harry Wentland" , Leo Li , "Rodrigo Siqueira" , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Nicholas Kazlauskas , Aurabindo Pillai , Wayne Lin , Fangzhi Zuo , Lyude Paul , Ian Chen , Bhawanpreet Lakha , Claudio Suarez , Colin Ian King , hersen wu , , Subject: [PATCH 3/3] Revert "drm/amd/display: Limit max DSC target bpp for specific monitors" Date: Mon, 24 Oct 2022 15:22:23 -0400 Message-ID: <20221024192224.180507-3-hamza.mahfooz@amd.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221024192224.180507-1-hamza.mahfooz@amd.com> References: <20221024192224.180507-1-hamza.mahfooz@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000C406:EE_|BY5PR12MB4146:EE_ X-MS-Office365-Filtering-Correlation-Id: 22709067-cc6e-47c9-9188-08dab5f5107d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This quirk is now handled in the DRM core, so we can drop all of the internal code that was added to handle it. Signed-off-by: Hamza Mahfooz Reviewed-by: Harry Wentland --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 35 ------------------- 1 file changed, 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 4956a0118215..a21e2ba77ddb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -41,39 +41,6 @@ #include "dm_helpers.h" #include "ddc_service_types.h" -struct monitor_patch_info { - unsigned int manufacturer_id; - unsigned int product_id; - void (*patch_func)(struct dc_edid_caps *edid_caps, unsigned int param); - unsigned int patch_param; -}; -static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param); - -static const struct monitor_patch_info monitor_patch_table[] = { -{0x6D1E, 0x5BBF, set_max_dsc_bpp_limit, 15}, -{0x6D1E, 0x5B9A, set_max_dsc_bpp_limit, 15}, -}; - -static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param) -{ - if (edid_caps) - edid_caps->panel_patch.max_dsc_target_bpp_limit = param; -} - -static int amdgpu_dm_patch_edid_caps(struct dc_edid_caps *edid_caps) -{ - int i, ret = 0; - - for (i = 0; i < ARRAY_SIZE(monitor_patch_table); i++) - if ((edid_caps->manufacturer_id == monitor_patch_table[i].manufacturer_id) - && (edid_caps->product_id == monitor_patch_table[i].product_id)) { - monitor_patch_table[i].patch_func(edid_caps, monitor_patch_table[i].patch_param); - ret++; - } - - return ret; -} - /* dm_helpers_parse_edid_caps * * Parse edid caps @@ -148,8 +115,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps( kfree(sads); kfree(sadb); - amdgpu_dm_patch_edid_caps(edid_caps); - return result; }