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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d15-20020a50fb0f000000b0050bc357148bsi10092304edq.23.2023.05.14.01.22.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 May 2023 01:22:36 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=DWbj5WCk; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5433C3858408 for ; Sun, 14 May 2023 08:22:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5433C3858408 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684052539; bh=U8/pmSW0VndMw6+TM9gTiyjI+tzZ7nIwXM7Ag9xjrdI=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=DWbj5WCkHPpM1Su+zbiPuvSJhazNTKHUByzPDHrlD6xclSKUxMguRmhJTkjx/29Kp 3kPF9o3LhyDggxYIKk7sJ0e73kGddovj2lHAvBWLPt4v538v9Ta6Jfdrdc07oNk7qC fLOO1ImACvj2gf6KhL6vmm0z0pDgu3KxZtnz8TWw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 8AB263858C2D for ; Sun, 14 May 2023 08:21:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8AB263858C2D X-IronPort-AV: E=McAfee;i="6600,9927,10709"; a="331391138" X-IronPort-AV: E=Sophos;i="5.99,273,1677571200"; d="scan'208";a="331391138" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 01:21:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10709"; a="824811322" X-IronPort-AV: E=Sophos;i="5.99,273,1677571200"; d="scan'208";a="824811322" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 14 May 2023 01:21:16 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7FBF11009147; Sun, 14 May 2023 16:21:15 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Refactor the or pattern to switch cases Date: Sun, 14 May 2023 16:21:13 +0800 Message-Id: <20230514082113.3487198-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765857093933024908?= X-GMAIL-MSGID: =?utf-8?q?1765857093933024908?= From: Pan Li This patch refactor the pattern A or B or C or D, to the switch case for easy add/remove new types, as well as human reading friendly. Before this patch: return A || B || C || D; After this patch: switch (type) { case A: case B: case C: case D: return true; default: return false; } Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (required_extensions_p): Refactor the or pattern to switch cases. --- gcc/config/riscv/riscv-vector-builtins.cc | 37 ++++++++++++++++------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 4117897c6c9..0f56f29f7aa 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -2606,17 +2606,32 @@ register_vector_type (vector_type_index type) static bool required_extensions_p (enum rvv_base_type type) { - return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index - || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index - || type == RVV_BASE_float_vector - || type == RVV_BASE_double_trunc_float_vector - || type == RVV_BASE_double_trunc_vector - || type == RVV_BASE_widen_lmul1_vector - || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret - || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret - || type == RVV_BASE_vlmul_ext_x2 || type == RVV_BASE_vlmul_ext_x4 - || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16 - || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64; + switch (type) + { + case RVV_BASE_eew8_index: + case RVV_BASE_eew16_index: + case RVV_BASE_eew32_index: + case RVV_BASE_eew64_index: + case RVV_BASE_float_vector: + case RVV_BASE_double_trunc_float_vector: + case RVV_BASE_double_trunc_vector: + case RVV_BASE_widen_lmul1_vector: + case RVV_BASE_eew8_interpret: + case RVV_BASE_eew16_interpret: + case RVV_BASE_eew32_interpret: + case RVV_BASE_eew64_interpret: + case RVV_BASE_vlmul_ext_x2: + case RVV_BASE_vlmul_ext_x4: + case RVV_BASE_vlmul_ext_x8: + case RVV_BASE_vlmul_ext_x16: + case RVV_BASE_vlmul_ext_x32: + case RVV_BASE_vlmul_ext_x64: + return true; + default: + return false; + } + + gcc_unreachable (); } static uint64_t