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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id qu21-20020a170907111500b0096a590447f0si4290413ejb.328.2023.05.12.19.09.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 19:09:41 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 388613855587 for ; Sat, 13 May 2023 02:09:35 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id F16D43858CDB for ; Sat, 13 May 2023 02:09:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F16D43858CDB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp63t1683943742tb85ry9n Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 13 May 2023 10:09:00 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: ILHsT53NKPhhfzBZJrjGFY52N4GZhaSFDqcDhYRDKgAxuxowOV9CDVIigCFmR xcv/PDLg+7kjP/atZ15qJqPBepL+Pahh+bwrbCr6R892lGHK8IQdRShPokEz6Rk+ddXqkV8 c0zztq8kGa0I1NVOdkCjFi9Ba6G04XZlfV8C0FhREkCe//hB8egG5wMyEFhYwMaS/bvvh6M kbI1f0bd9tViNAvqiCbX3Qs8kw9Sb5Qp7ExxypWYkJbBCXR6tuUeGdnjLXOGBuJ54M/uY4q VOOgmCewHSLM9KQw+0t3JLONsSwGzvzUze83RFs6/wrUXBfeUtM7tNbJgZV3XS6cT6dIG09 POs/Vk8L5o0ZchT31RtJ1p9SD/kMP8zQLHNP/q0FAMkun7ZtcRWY3dn0F5ZuWn3FnL0vJKH 5WV5A5VOCCo= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6668109334696138872 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization Date: Sat, 13 May 2023 10:08:59 +0800 Message-Id: <20230513020859.13485-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765743034049625573?= X-GMAIL-MSGID: =?utf-8?q?1765743034049625573?= From: Juzhe-Zhong This patch is optimizing the AVL for VLS auto-vectorzation. Consider such case: typedef int8_t vnx2qi __attribute__ ((vector_size (2))); __attribute__ ((noipa)) void f_vnx2qi (int8_t a, int8_t b, int8_t *out) { vnx2qi v = {a, b}; *(vnx2qi *) out = v; } Before this patch: f_vnx2qi: vsetvli a5,zero,e8,mf8,ta,ma vmv.v.x v1,a0 vslide1down.vx v1,v1,a1 vse8.v v1,0(a2) ret After this patch: f_vnx2qi: vsetivli zero,2,e8,mf8,ta,ma vmv.v.x v1,a0 vslide1down.vx v1,v1,a1 vse8.v v1,0(a2) ret gcc/ChangeLog: * config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Change argument type. * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Optimize AVL for vlmax VLS. (emit_vlmax_reg_op): Ditto. * config/riscv/vector.md: Adapt argument. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vf_avl-1.c: New test. --- gcc/config/riscv/riscv-protos.h | 2 +- gcc/config/riscv/riscv-v.cc | 25 +++++++++++++++---- gcc/config/riscv/vector.md | 4 +-- .../gcc.target/riscv/rvv/base/vf_avl-1.c | 15 +++++++++++ 4 files changed, 38 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index bc71f9cbbba..90934d43430 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -164,7 +164,7 @@ bool check_builtin_call (location_t, vec, unsigned int, tree, unsigned int, tree *); bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); bool legitimize_move (rtx, rtx, machine_mode); -void emit_vlmax_vsetvl (machine_mode, rtx); +void emit_vlmax_vsetvl (machine_mode, rtx *); void emit_hard_vlmax_vsetvl (machine_mode, rtx); void emit_vlmax_op (unsigned, rtx, rtx, machine_mode); void emit_vlmax_reg_op (unsigned, rtx, rtx, rtx, machine_mode); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d844c305320..382cc4b6311 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -120,7 +120,9 @@ public: { vlmax_p = true; len = gen_reg_rtx (Pmode); - emit_vlmax_vsetvl (dest_mode, len); + emit_vlmax_vsetvl (dest_mode, &len); + if (CONST_INT_P (len)) + vlmax_p = false; } add_input_operand (len, Pmode); @@ -183,16 +185,29 @@ emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl) } void -emit_vlmax_vsetvl (machine_mode vmode, rtx vl) +emit_vlmax_vsetvl (machine_mode vmode, rtx *vl) { unsigned int sew = get_sew (vmode); enum vlmul_type vlmul = get_vlmul (vmode); unsigned int ratio = calculate_ratio (sew, vlmul); + /* For VLS VLMAX auto-vectorization, we change + VL into const_int value of VF so that we + will emit "vsetivli zero, CONST_INT" instead of + "vsetvli a5, zero". + + TODO: Support VLS min-length in the future. */ + poly_uint64 nunits = GET_MODE_NUNITS (vmode); + if (nunits.is_constant () && IN_RANGE (nunits.to_constant (), 0, 31)) + { + *vl = gen_int_mode (nunits, Pmode); + return; + } + if (!optimize) - emit_hard_vlmax_vsetvl (vmode, vl); + emit_hard_vlmax_vsetvl (vmode, *vl); else - emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode))); + emit_insn (gen_vlmax_avl (Pmode, *vl, gen_int_mode (ratio, Pmode))); } /* Calculate SEW/LMUL ratio. */ @@ -323,7 +338,7 @@ emit_vlmax_reg_op (unsigned icode, rtx dest, rtx src, rtx len, machine_mode mask_mode) { emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode, - /* Force VLMAX */ true); + /* Force VLMAX */ CONST_INT_P (len) ? false : true); } void diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 328fce8d632..b02ecf92c00 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -720,7 +720,7 @@ emit_insn (gen_rtx_SET (operands[0], operands[1])); else { - riscv_vector::emit_vlmax_vsetvl (mode, operands[2]); + riscv_vector::emit_vlmax_vsetvl (mode, &operands[2]); riscv_vector::emit_vlmax_reg_op (code_for_pred_mov (mode), operands[0], operands[1], operands[2], mode); @@ -741,7 +741,7 @@ emit_insn (gen_rtx_SET (operands[0], operands[1])); else { - riscv_vector::emit_vlmax_vsetvl (mode, operands[2]); + riscv_vector::emit_vlmax_vsetvl (mode, &operands[2]); riscv_vector::emit_vlmax_reg_op (code_for_pred_mov (mode), operands[0], operands[1], operands[2], mode); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c new file mode 100644 index 00000000000..11adf6bc611 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */ + +#include + +typedef int8_t vnx2qi __attribute__ ((vector_size (2))); + +__attribute__ ((noipa)) void +f_vnx2qi (int8_t a, int8_t b, int8_t *out) +{ + vnx2qi v = {a, b}; + *(vnx2qi *) out = v; +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 } } */