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Fri, 12 May 2023 12:21:48 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34CCLj5V028989; Fri, 12 May 2023 12:21:45 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3qdy59u1un-1; Fri, 12 May 2023 12:21:45 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34CCLi9Y028984; Fri, 12 May 2023 12:21:45 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-kbajaj-hyd.qualcomm.com [10.147.247.189]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 34CCLiUn028983; Fri, 12 May 2023 12:21:44 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2340697) id 353AC52974D; Fri, 12 May 2023 17:51:44 +0530 (+0530) From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley Cc: Komal Bajaj , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 01/10] nvmem: qfprom: Add support for secure reading Date: Fri, 12 May 2023 17:51:25 +0530 Message-Id: <20230512122134.24339-2-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230512122134.24339-1-quic_kbajaj@quicinc.com> References: <20230512122134.24339-1-quic_kbajaj@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Tj4wnpfm4LZLj-oioTeMjT-Mx1gp-aLE X-Proofpoint-ORIG-GUID: Tj4wnpfm4LZLj-oioTeMjT-Mx1gp-aLE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-12_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 malwarescore=0 bulkscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 spamscore=0 adultscore=0 impostorscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305120103 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765691223802323225?= X-GMAIL-MSGID: =?utf-8?q?1765691223802323225?= For some of the Qualcomm SoC's, it is possible that some of the fuse regions or entire qfprom region is protected from non-secure access. In such situations, linux will have to use secure calls to read the region. With that motivation, add the support of reading secure regions in qfprom driver. Ensuring the address to read is word aligned since our secure I/O only supports word size I/O. Signed-off-by: Komal Bajaj --- drivers/nvmem/Kconfig | 1 + drivers/nvmem/qfprom.c | 69 +++++++++++++++++++++++++++++++++--------- 2 files changed, 55 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index b291b27048c7..3d896ba29b89 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -209,6 +209,7 @@ config NVMEM_QCOM_QFPROM tristate "QCOM QFPROM Support" depends on ARCH_QCOM || COMPILE_TEST depends on HAS_IOMEM + select QCOM_SCM help Say y here to enable QFPROM support. The QFPROM provides access functions for QFPROM data to rest of the drivers via nvmem interface. diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index c1e893c8a247..20662e2d3732 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -16,6 +16,7 @@ #include #include #include +#include /* Blow timer clock frequency in Mhz */ #define QFPROM_BLOW_TIMER_OFFSET 0x03c @@ -59,21 +60,22 @@ struct qfprom_soc_data { /** * struct qfprom_priv - structure holding qfprom attributes * - * @qfpraw: iomapped memory space for qfprom-efuse raw address space. - * @qfpconf: iomapped memory space for qfprom-efuse configuration address - * space. + * @qfpraw: iomapped memory space for qfprom-efuse raw address space. + * @qfpconf: iomapped memory space for qfprom-efuse configuration address space. * @qfpcorrected: iomapped memory space for qfprom corrected address space. - * @qfpsecurity: iomapped memory space for qfprom security control space. - * @dev: qfprom device structure. - * @secclk: Clock supply. - * @vcc: Regulator supply. - * @soc_data: Data that for things that varies from SoC to SoC. + * @qfpsecurity: iomapped memory space for qfprom security control space. + * @qfpseccorrected: starting physical address for qfprom secure corrected address space. + * @dev: qfprom device structure. + * @secclk: Clock supply. + * @vcc: Regulator supply. + * @soc_data: Data that for things that varies from SoC to SoC. */ struct qfprom_priv { void __iomem *qfpraw; void __iomem *qfpconf; void __iomem *qfpcorrected; void __iomem *qfpsecurity; + phys_addr_t qfpseccorrected; struct device *dev; struct clk *secclk; struct regulator *vcc; @@ -99,10 +101,12 @@ struct qfprom_touched_values { * * @keepout: Array of keepout regions for this SoC. * @nkeepout: Number of elements in the keepout array. + * @secure: Is qfprom region for this SoC protected from non-secure access. */ struct qfprom_soc_compatible_data { const struct nvmem_keepout *keepout; unsigned int nkeepout; + bool secure; }; static const struct nvmem_keepout sc7180_qfprom_keepout[] = { @@ -334,6 +338,34 @@ static int qfprom_reg_read(void *context, return 0; } +static int qfprom_sec_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) +{ + struct qfprom_priv *priv = context; + u8 *val = _val; + int buf_start, buf_end, index, i = 0; + char *buffer; + u32 read_val; + + buf_start = ALIGN_DOWN(reg, 4); + buf_end = ALIGN(reg + bytes, 4); + buffer = kzalloc(buf_end - buf_start, GFP_KERNEL); + if (!buffer) + return -ENOMEM; + + for (index = buf_start; index < buf_end; index += 4, i += 4) { + if (qcom_scm_io_readl(priv->qfpseccorrected + index, &read_val)) { + dev_err(priv->dev, "Couldn't access feature register\n"); + kfree_sensitive(buffer); + return -EINVAL; + } + memcpy(buffer + i, &read_val, 4); + } + + memcpy(val, buffer + reg % 4, bytes); + kfree_sensitive(buffer); + return 0; +} + static void qfprom_runtime_disable(void *data) { pm_runtime_disable(data); @@ -373,13 +405,6 @@ static int qfprom_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - /* The corrected section is always provided */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->qfpcorrected = devm_ioremap_resource(dev, res); - if (IS_ERR(priv->qfpcorrected)) - return PTR_ERR(priv->qfpcorrected); - - econfig.size = resource_size(res); econfig.dev = dev; econfig.priv = priv; @@ -390,6 +415,20 @@ static int qfprom_probe(struct platform_device *pdev) econfig.nkeepout = soc_data->nkeepout; } + /* The corrected section is always provided */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (soc_data && soc_data->secure) { + priv->qfpseccorrected = res->start; + econfig.reg_read = qfprom_sec_reg_read; + } else { + priv->qfpcorrected = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->qfpcorrected)) + return PTR_ERR(priv->qfpcorrected); + } + + econfig.size = resource_size(res); + /* * If more than one region is provided then the OS has the ability * to write. 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Signed-off-by: Komal Bajaj Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 8d8503dd934b..59082f6e8c9f 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -26,6 +26,7 @@ properties: - qcom,msm8996-qfprom - qcom,msm8998-qfprom - qcom,qcs404-qfprom + - qcom,qdu1000-qfprom - qcom,sc7180-qfprom - qcom,sc7280-qfprom - qcom,sdm630-qfprom From patchwork Fri May 12 12:21:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 93149 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp5058961vqo; Fri, 12 May 2023 05:22:40 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7i5oLOh0eaYal8hpEAStWbL/LHppjW8JvJSRH7baoG7B/aQOOTlLIrrNnu6cdhw1PpVbtx X-Received: by 2002:a05:6a20:4285:b0:100:7ac0:b32d with SMTP id o5-20020a056a20428500b001007ac0b32dmr22318191pzj.44.1683894160052; Fri, 12 May 2023 05:22:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683894160; cv=none; d=google.com; s=arc-20160816; b=XTfv+Yoyjrj6oSs4Q5oVgCjY12gmmrtxk9ZqGj7DANTYt3i66pRzew6YftWqgZny73 EevbNQqbxxiSH+OLgnUlSoq+WF2wmNP+wxkVSYh0MHQDwmPfh3ypS89+JMwE17NxVqic QBLWLLDpODuqMwKfIepgyFAtXAcSiYBWkAus7fpjVENoHAMAB/Z1vbmeEerolvUL6sfz jY57n5bTm0DUw8ySsZGqldF8KxUPUqZhIBGXSbiGKJKFb8+iCcQAzJ48siuQNObf6kz1 BHyV3vxarpvGnkHNixSJMNfOR55Z2LEYUKlXQE9Ualk8FAP0N8APA9QtGlZJx4OPMuLs LoXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=9Vtvs1JWI9CpOzCswjfVnNlHyj8mCePBW8JfsjPO7yU=; b=qN45ELal/7caWwTBDwcCpujhKpxtWZssiEcx19IBhYSJFBSm2msonJHd7xm2gbQtnQ jYDCn77te7J3jufTAP6lNkX83kubXi5yGrDRNI9fTWvCqvsV63zBodBFkow2mqZCuO08 mu1dpRb66/jEVD/To0BWD8nOO0+SyU4ZZLkhZW7cACaARd6+8aGrVjCi2EifdnLLOqv1 EEkeAFWz8YA/4NVENr6A0BqtRTW80hRkvg+yad+ZQ77C5OPbvl7EkUMGx6RvwsUr/SyW K5xVE9y4e3XwEsAVdcI04SLBM0ZCccJAz0cJXxr5byUY9bCxsA+bKtRK6xIwxb6cReSk DKEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=YOAiwtJB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 734438113bba..418644f396bc 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1333,6 +1333,18 @@ interrupts = ; multi-ch-bit-off = <24 2>; }; + + qfprom: efuse@221c8000 { + compatible = "qcom,qdu1000-qfprom", "qcom,qfprom"; + reg = <0 0x221c8000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + multi_chan_ddr: multi_chan_ddr@12b { + reg = <0x12b 0x1>; + bits = <0 2>; + }; + }; }; timer { From patchwork Fri May 12 12:21:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 93160 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp5062504vqo; Fri, 12 May 2023 05:28:18 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ64WrlCzfjzZc7Fz9In+TAXhZdvNJb5bQavCzWF1iN6i21rxA7QZIAzX6eqVbaMmhmZqHsu X-Received: by 2002:a17:902:c40a:b0:1ab:1624:38cf with SMTP id k10-20020a170902c40a00b001ab162438cfmr36328393plk.60.1683894497762; Fri, 12 May 2023 05:28:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683894497; cv=none; d=google.com; s=arc-20160816; b=V3HSRptXX3ai0eTE25FWlwU3dqMebHDaC8hbuIPfjiLkeEk5hARndwd1Xx4cs3scGQ tRCoscr+8yqX7K+xVmtAWJAWiMQdV0ZeUnoEvVJlwpkPlaAgos88zIpCX3htrlyL5X0b sD7HkquZ2bmgza8WEh8dENzkMtSrMJ3j8LSQH/PmsNbaVubRNiWcKZIOICxshFbnjX+l fiPFMdT26J8l+anBqvIddS4mqjnzjRlYa6Ooa8P4MFiLrD7Q4NOieytuAznr3+r5HBm/ 90pNPkCJ2LCOk10PytXiIZPkfKvo2lfhpi8BLtbBhnlGyaJoa14rj/88W98ggmxnYEBY ePKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=qRWrHVDwbLS+lNdPMcQNCVsVTRkpVonMCQUakS2Yv+k=; b=QVEMixdj2arGD+43WUoXsAzwdDb28urBl/GyQZd+SD/ygJo/eOO67ui+YtyWmNouiI Yw4U5u+WyrhgcgHbBL8lgD3LJp21JnDVo6X/35iS1nSWZZzWpT/GPdk3lWvtLOR15TlX t1t1MJOxoYXBhsx3K+oWoHJJG3YkgCFV0mnozS6l0u7zTbjIMUbkcsNlQP3IRsmF8mj0 CoCbNftZ/CBVMuRIe6Ih3YEKSgW+yja3AdYyPGh/OmHIApyfMciwEAEV4HSDDO2ry1BF UHfo15v4zRnUnWIsRss8PctHDPwSgp1MiI9h58eyqptIlvDk2zf23Ay1h3+H9LlcNiG/ N2yA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=KzcjMaJh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Komal Bajaj --- drivers/nvmem/qfprom.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.17.1 diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index 20662e2d3732..12a7981a8a71 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -109,6 +109,10 @@ struct qfprom_soc_compatible_data { bool secure; }; +static const struct qfprom_soc_compatible_data qdu1000_qfprom = { + .secure = true +}; + static const struct nvmem_keepout sc7180_qfprom_keepout[] = { {.start = 0x128, .end = 0x148}, {.start = 0x220, .end = 0x228} @@ -490,6 +494,7 @@ static int qfprom_probe(struct platform_device *pdev) static const struct of_device_id qfprom_of_match[] = { { .compatible = "qcom,qfprom",}, + { .compatible = "qcom,qdu1000-qfprom", .data = &qdu1000_qfprom}, { .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom}, { .compatible = "qcom,sc7280-qfprom", .data = &sc7280_qfprom}, {/* sentinel */}, From patchwork Fri May 12 12:21:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 93162 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp5062816vqo; Fri, 12 May 2023 05:28:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5lo2IGWuf/kCtHsEY7ukLcuwUczhzlun0FfjleVN5NQSnCfgiYmMc3JtiUbB4YtlO0GNw1 X-Received: by 2002:a05:6a20:8f13:b0:101:3fe5:8776 with SMTP id b19-20020a056a208f1300b001013fe58776mr16245402pzk.17.1683894532097; Fri, 12 May 2023 05:28:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683894532; cv=none; d=google.com; s=arc-20160816; b=QpOMpgoco5BJWYvyPp4vANE3Rdk6X+O0IhM6k9VC4gl8dcBZWn6dIJy8IgqO+kbzqO AdfNG9GiRiXHB+mDVZHP1OQz8k92CTzqdVjyJ6nLqXtMDW36fD1G6vfyE6UmWyPfPWZS ann6dNF1t/Mr1luI15BYYJYp9e9NIYsGnfZwrCt+f65fw4m/zkFrS6ulK1mrzNrLEGc5 kFW7Db/9nH/Z1s7H880zh/LwldyaSA4Jr5vNZO12OkkpLadNbDRtG6z38d2RtdGAWgpX GkurLxf5UDFfU7ufNv/4innNJCllmfHUkwwJ9xL2DknzmMJq6V5S4mSwBuW1/uzUMf5X wV0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=yfzJYZu/9y46Q70PlmxBlI8FMOuVHr/VsKH79cgMxDA=; b=ZuPuJJE7CNtvyeQxC3of1DbzDt3kBAjNuPR86p2EZmcketXaMTkNUC+VjCahoXglIZ OyAnF/6uOZn24d13dQ63BRa6k9qU9ZP2B8KtmnzGfuz5sKwzrTbaY5L/xfihyEFYXvOC k0pA+FQS1lbb0G4M7Aw+s6Y4N5MduBlZMQADU/BnzZ4GLgEgr1qIeCsmeQWJ02LpBK0h fuKxvF/EADh3jlA1LIIOqTV1HpFyYXwktZZjcZz8sNkCvpUxNVd7USH63ZdgZZYr4+/M xuOeTTEMSTNVgHEBkzGO9Vw8ii4I5SjBtLcCjeTN+/xywVZUlZ1sTYr6kD4VuGWgR5O+ bs7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=YGozAFgE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Fri, 12 May 2023 12:21:52 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34CCLnBt029054; Fri, 12 May 2023 12:21:49 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3qdy59u1v9-1; Fri, 12 May 2023 12:21:49 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34CCLnWx029048; Fri, 12 May 2023 12:21:49 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-kbajaj-hyd.qualcomm.com [10.147.247.189]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 34CCLnTV029047; Fri, 12 May 2023 12:21:49 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2340697) id EB25E52974D; Fri, 12 May 2023 17:51:48 +0530 (+0530) From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley Cc: Komal Bajaj , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 05/10] soc: qcom: llcc: Refactor llcc driver to support multiple configuration Date: Fri, 12 May 2023 17:51:29 +0530 Message-Id: <20230512122134.24339-6-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230512122134.24339-1-quic_kbajaj@quicinc.com> References: <20230512122134.24339-1-quic_kbajaj@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MXLh4kCF2tYlDrFYvc9F98wbbRufUNal X-Proofpoint-ORIG-GUID: MXLh4kCF2tYlDrFYvc9F98wbbRufUNal X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-12_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305120103 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765691392667553935?= X-GMAIL-MSGID: =?utf-8?q?1765691392667553935?= Refactor driver to support multiple configuration for llcc on a target. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 210 ++++++++++++++++++++--------------- 1 file changed, 123 insertions(+), 87 deletions(-) -- 2.17.1 diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 67c19ed2219a..6cf373da5df9 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -423,101 +423,137 @@ static const u32 llcc_v2_1_reg_offset[] = { [LLCC_COMMON_STATUS0] = 0x0003400c, }; -static const struct qcom_llcc_config sc7180_cfg = { - .sct_data = sc7180_data, - .size = ARRAY_SIZE(sc7180_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7180_cfg[] = { + { + .sct_data = sc7180_data, + .size = ARRAY_SIZE(sc7180_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc7280_cfg = { - .sct_data = sc7280_data, - .size = ARRAY_SIZE(sc7280_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7280_cfg[] = { + { + .sct_data = sc7280_data, + .size = ARRAY_SIZE(sc7280_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc8180x_cfg = { - .sct_data = sc8180x_data, - .size = ARRAY_SIZE(sc8180x_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8180x_cfg[] = { + { + .sct_data = sc8180x_data, + .size = ARRAY_SIZE(sc8180x_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc8280xp_cfg = { - .sct_data = sc8280xp_data, - .size = ARRAY_SIZE(sc8280xp_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8280xp_cfg[] = { + { + .sct_data = sc8280xp_data, + .size = ARRAY_SIZE(sc8280xp_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sdm845_cfg = { - .sct_data = sdm845_data, - .size = ARRAY_SIZE(sdm845_data), - .need_llcc_cfg = false, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, - .no_edac = true, +static const struct qcom_llcc_config sdm845_cfg[] = { + { + .sct_data = sdm845_data, + .size = ARRAY_SIZE(sdm845_data), + .need_llcc_cfg = false, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + .no_edac = true, + }, + { }, }; -static const struct qcom_llcc_config sm6350_cfg = { - .sct_data = sm6350_data, - .size = ARRAY_SIZE(sm6350_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm6350_cfg[] = { + { + .sct_data = sm6350_data, + .size = ARRAY_SIZE(sm6350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm7150_cfg = { - .sct_data = sm7150_data, - .size = ARRAY_SIZE(sm7150_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm7150_cfg[] = { + { + .sct_data = sm7150_data, + .size = ARRAY_SIZE(sm7150_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8150_cfg = { - .sct_data = sm8150_data, - .size = ARRAY_SIZE(sm8150_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8150_cfg[] = { + { + .sct_data = sm8150_data, + .size = ARRAY_SIZE(sm8150_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8250_cfg = { - .sct_data = sm8250_data, - .size = ARRAY_SIZE(sm8250_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8250_cfg[] = { + { + .sct_data = sm8250_data, + .size = ARRAY_SIZE(sm8250_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8350_cfg = { - .sct_data = sm8350_data, - .size = ARRAY_SIZE(sm8350_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8350_cfg[] = { + { + .sct_data = sm8350_data, + .size = ARRAY_SIZE(sm8350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8450_cfg = { - .sct_data = sm8450_data, - .size = ARRAY_SIZE(sm8450_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v2_1_reg_offset, - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8450_cfg[] = { + { + .sct_data = sm8450_data, + .size = ARRAY_SIZE(sm8450_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8550_cfg = { - .sct_data = sm8550_data, - .size = ARRAY_SIZE(sm8550_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v2_1_reg_offset, - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8550_cfg[] = { + { + .sct_data = sm8550_data, + .size = ARRAY_SIZE(sm8550_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, }; static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; @@ -1004,8 +1040,8 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - llcc_cfg = cfg->sct_data; - sz = cfg->size; + llcc_cfg = cfg[0]->sct_data; + sz = cfg[0]->size; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) @@ -1051,18 +1087,18 @@ static int qcom_llcc_probe(struct platform_device *pdev) } static const struct of_device_id qcom_llcc_of_match[] = { - { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, - { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, - { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg }, - { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, - { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, - { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, - { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg }, - { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, - { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, - { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, - { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, - { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg }, + { .compatible = "qcom,sc7180-llcc", .data = sc7180_cfg }, + { .compatible = "qcom,sc7280-llcc", .data = sc7280_cfg }, + { .compatible = "qcom,sc8180x-llcc", .data = sc8180x_cfg }, + { .compatible = "qcom,sc8280xp-llcc", .data = sc8280xp_cfg }, + { .compatible = "qcom,sdm845-llcc", .data = sdm845_cfg }, + { .compatible = "qcom,sm6350-llcc", .data = sm6350_cfg }, + { .compatible = "qcom,sm7150-llcc", .data = sm7150_cfg }, + { .compatible = "qcom,sm8150-llcc", .data = sm8150_cfg }, + { .compatible = "qcom,sm8250-llcc", .data = sm8250_cfg }, + { .compatible = "qcom,sm8350-llcc", .data = sm8350_cfg }, + { .compatible = "qcom,sm8450-llcc", .data = sm8450_cfg }, + { .compatible = "qcom,sm8550-llcc", .data = sm8550_cfg }, { } }; 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Fri, 12 May 2023 12:21:54 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34CCLpHB029068; Fri, 12 May 2023 12:21:51 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3qdy59u1vg-1; Fri, 12 May 2023 12:21:51 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34CCLpHx029062; Fri, 12 May 2023 12:21:51 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-kbajaj-hyd.qualcomm.com [10.147.247.189]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 34CCLobD029061; Fri, 12 May 2023 12:21:51 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2340697) id 4632D52974D; Fri, 12 May 2023 17:51:50 +0530 (+0530) From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley Cc: Komal Bajaj , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 06/10] soc: qcom: Add LLCC support for multi channel DDR Date: Fri, 12 May 2023 17:51:30 +0530 Message-Id: <20230512122134.24339-7-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230512122134.24339-1-quic_kbajaj@quicinc.com> References: <20230512122134.24339-1-quic_kbajaj@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ENHVhyvHmZXH_BlUpj2N_v5FDTtYymC_ X-Proofpoint-GUID: ENHVhyvHmZXH_BlUpj2N_v5FDTtYymC_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-12_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 clxscore=1015 adultscore=0 mlxscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305120103 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765691198397962036?= X-GMAIL-MSGID: =?utf-8?q?1765691198397962036?= Add LLCC support for multi channel DDR configuration based on a feature register. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 6cf373da5df9..1da337e7a378 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -943,6 +944,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev, return ret; } +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index) +{ + int ret = 0; + + ret = nvmem_cell_read_u8(&pdev->dev, "multi_chan_ddr", cfg_index); + if (ret == -ENOENT) { + *cfg_index = 0; + return 0; + } + + return ret; +} + static int qcom_llcc_remove(struct platform_device *pdev) { /* Set the global pointer to a error code to avoid referencing it */ @@ -975,11 +989,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; int ret, i; struct platform_device *llcc_edac; - const struct qcom_llcc_config *cfg; + const struct qcom_llcc_config *cfg, *entry; const struct llcc_slice_config *llcc_cfg; u32 sz; + u8 cfg_index; u32 version; struct regmap *regmap; + u32 num_entries = 0; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -1040,8 +1056,18 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - llcc_cfg = cfg[0]->sct_data; - sz = cfg[0]->size; + ret = qcom_llcc_get_cfg_index(pdev, &cfg_index); + if (ret) + goto err; + + for (entry = cfg; entry->sct_data; entry++, num_entries++); + if (cfg_index >= num_entries || cfg_index < 0) { + ret = -EINVAL; + goto err; + } + + llcc_cfg = cfg[cfg_index].sct_data; + sz = cfg[cfg_index].size; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) From patchwork Fri May 12 12:21:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 93159 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp5062345vqo; Fri, 12 May 2023 05:28:00 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5gLg3VP5/JdU264L90nlCHyfpnYhP8GbAEmPz60mQDoJI1i94kz5g9lvcLRqgwKjbrYWcM X-Received: by 2002:a17:90a:31c1:b0:24e:1f06:4d32 with SMTP id j1-20020a17090a31c100b0024e1f064d32mr25209430pjf.2.1683894479895; Fri, 12 May 2023 05:27:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683894479; cv=none; d=google.com; s=arc-20160816; b=IkAyAeB+we92JmsKGhIYXYkI1e44CwVMRSStCszPykGtbhbCPSw5DXdd+gZ9b2vmxf ACKf1Rk91kO4FPBI1Ce6Pxejer49cqNj8lCfhHpFlpaDYhBmxnyt4PjKIwj5ZS4uRpG0 hRynudiU3gSCVDjh1qgjdCpkMc59p4SQWFwN9RMTWcE57KetswE6A4rJn9X1jnzkOlMR def8KRqNYPTq2L6o0mSzNSTHHrFcniDwX4gKvrkSAcFMX/sHYNBlo52cC5fmkSlHlB1e i2IRgWsp0Xfo8nt2eBY1/6G07udaPbisBpgSpViQCJxcrpY0rC/SJKYHyjlWQIqLKxvu gazA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=34o9OKGa5F/dsZLu3ZJJG3DB5+mUq0p6+wVLP7qrV+8=; b=FqOoKXwuNcxL7R/TsOyaQy88X9nKuhlvH7U+4VCGr31EHq36gq1XucxMRSuKbXZ9ga Xo8boxPbdeq0GRCjw3ogVdzcyYLdh/JLSQvngsemMXfQz+fuBGceAXfk4QmUT1TDKAXP q2fck84czrF/tsZuF8sSW5pMKsu6IWvN3HgqTwRDT65HY5TFjBHJnGp0ShCuEp2/ajsx OOstdiInZzbxppP+cS1zzRukrjbx2L81zw2cOERkJdUiRbk9PEWtZlC1Ht+EeJYlJyx9 Rrr4fN6rHQLj6LnPUwzlWLga3TfTZ2h1UDqKORTetwMbgsec9NRMLc9gRyGRiK+tz1ML Eagg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZZjST21S; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Komal Bajaj Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index d8b91944180a..f289a0294339 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,qdu1000-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc @@ -92,6 +93,7 @@ allOf: compatible: contains: enum: + - qcom,qdu1000-llcc - qcom,sc8180x-llcc - qcom,sc8280xp-llcc then: From patchwork Fri May 12 12:21:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 93150 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp5059416vqo; Fri, 12 May 2023 05:23:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5NvEF6+rlVkPmf0s1tzlciUIGvQUNYEkubrJwyWxb8aNllmLV2z93lfckq7SC0f3vF3Y67 X-Received: by 2002:a05:6a20:8f28:b0:101:2160:ff8f with SMTP id b40-20020a056a208f2800b001012160ff8fmr18041358pzk.11.1683894204992; Fri, 12 May 2023 05:23:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683894204; cv=none; d=google.com; s=arc-20160816; b=ekbA+qBQlsupumLXEaKe6kc/eVY7M6dwt/cy/2eFb0+7Micxw+sXNu5sUWxWBNX07h kqn18MGSrCtVornmZvtseq07SbPsP+F9e5+ie6c0nsAV/Zd5fi1YeohtAL0GIUNS61G0 8yyvi0lMz/HZEoU6gqWQk4LAp/GammLP24KUj+TH0upf8Pzv05pfGJW3CoQVic9ip+XP OmUcmFGc6N195brUb8g+kdBsD4EQDyrsDq9wU4rbNrHHNzqVT+pgAmyA6jz0Ws3SyPnD x5QNHhQeSXyB2YqRaNhR18J6T5NtivYUeFgDTYmV1Lmpb+uH5pvKuIC4Akfe3dTm61LM WvcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=/65vKdetwmb43mDhATuCjOVP9mfTPNcvx1hM5S1jW5k=; b=eM6pI/lhGsXQZQ7UfSwuH42VW6Jmll39zpYA0WlXmUP7EWNnLOQ6ZMdHcv3RUbe+wf DbNKs8JeoLmCXXaK8sYB6MWCuhUMwzfCxW0u5vxLzE2q9X//dLq6t/nkHqyWTter+W84 kKKAEXwxudNIs6he52ybAXsAYKjPSlEPUB4czCG2cOme4P2nlKBUfSWDL/zXuv65ff5w b4VLaSOM0TKVwkxyta4iq4pHTdXR2EAD2qHrJG1jr47Q6cfCBlKJJnoEn7cYGD1NQZzq H3+buGfjPUlFScBawRgldmvEYQM7sfkAhCKZ8ZIICttira+IOrBOa77FSD/fXmxkZvq8 KgTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=E5FQ3BTu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Fri, 12 May 2023 12:21:56 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34CCLsE0029094; Fri, 12 May 2023 12:21:54 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3qdy59u1vv-1; Fri, 12 May 2023 12:21:54 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34CCLrGe029088; Fri, 12 May 2023 12:21:54 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-kbajaj-hyd.qualcomm.com [10.147.247.189]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 34CCLrUu029087; Fri, 12 May 2023 12:21:53 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2340697) id 2F6F652974D; Fri, 12 May 2023 17:51:53 +0530 (+0530) From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley Cc: Komal Bajaj , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 08/10] Revert "arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller" Date: Fri, 12 May 2023 17:51:32 +0530 Message-Id: <20230512122134.24339-9-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230512122134.24339-1-quic_kbajaj@quicinc.com> References: <20230512122134.24339-1-quic_kbajaj@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: uuuZVEWM02Vjk06CBbBu6nfsR_GNHvin X-Proofpoint-GUID: uuuZVEWM02Vjk06CBbBu6nfsR_GNHvin X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-12_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 adultscore=0 mlxscore=0 suspectscore=0 mlxlogscore=789 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305120103 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765691049894755622?= X-GMAIL-MSGID: =?utf-8?q?1765691049894755622?= This reverts commit 6209038f131fee84ff1536dc59864f54d06740f2. Reverting change as it was merged before corresponding driver side changes, resulting in incompatibility with the current implementation. Committing the revert now. Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 12 ------------ 1 file changed, 12 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 418644f396bc..ff21e7a6b312 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1322,18 +1322,6 @@ #interconnect-cells = <2>; }; - system-cache-controller@19200000 { - compatible = "qcom,qdu1000-llcc"; - reg = <0 0x19200000 0 0xd80000>, - <0 0x1a200000 0 0x80000>, - <0 0x221c8128 0 0x4>; - reg-names = "llcc_base", - "llcc_broadcast_base", - "multi_channel_register"; - interrupts = ; - multi-ch-bit-off = <24 2>; - }; - qfprom: efuse@221c8000 { compatible = "qcom,qdu1000-qfprom", "qcom,qfprom"; reg = <0 0x221c8000 0 0x1000>; From patchwork Fri May 12 12:21:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 93156 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp5061243vqo; Fri, 12 May 2023 05:26:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6lfoQy+ckoPqkPYkeWZIUgKher083xVaWm5fualDXIBmDQJcmtDst0pE6mW7e1u9r3b4Tr X-Received: by 2002:a05:6a00:138c:b0:646:1f13:7fce with SMTP id t12-20020a056a00138c00b006461f137fcemr25390671pfg.2.1683894371048; Fri, 12 May 2023 05:26:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683894371; cv=none; d=google.com; s=arc-20160816; b=oJXhrWN0HMLX0ivjdnRVjq6aC8r1yUS9rclZHPKqeU03a7TIcrKg/mJJ81GUUs6uTs dCppJJ0VuK/qlODeAeNqpIFDxFVfyj8AiAeKNAY/lLJ6p97JtR9i5ZVM790F2ffcyNU5 wfImr3wbu+dl9IOA0BVGLHNapjsXP+3rcy/mrz82rQoVGKPG9TwIpyd0JxUdCL4Dazvt E8ZCsMDBpKG/3oa/3R8Tq5qM+Qnx/Q2ezgzGEdH37ewAaHNT/kwtaIyZ470Rpjyo8ht4 tmDJg+QoQ5ej7T6cSQMJV42UVMYBCBybvOEA+p+2qjao/P6Xia/ddFZxHouEnYZjG8O+ 19Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=v12n/lgcNRzkiFHv8J3dMVyC28U95ejbKaFc8h5K91E=; b=xJ7FhFaVpWy4EChSBK8CcviKfRhL7YsNNgM53QPARFnMSmq78VQI5pxAzz+WmEjtn5 toxoQDiq9Rb7ipKTpNE/REB8IX+qJMbocWfun/E6HMd2CkjWk4/SUrSY/Ln21tFoL2sE V1bVs8kOWgM3gldC9DPxfj5fWDRrF1rfoIaHvZ86gD+UKv43apwJw3UGXrBI0wuYbV/O +R7YE8/jfmY99SoDzFuaUxUU4J1aOdNqY5v5wULL53p+P4pHK5PUX42dtGetzBqGKn6u d9HFSFVyevvdgn5rOb4hpwsSJBfksrb3L/SIRBUk6Phswxl1USFFSusGCDH7vvWGyvd6 kzdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="JbK/5gTX"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Fri, 12 May 2023 12:21:58 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34CCLl6U029029; Fri, 12 May 2023 12:21:55 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3qdy59u1w2-1; Fri, 12 May 2023 12:21:55 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34CCLrGg029088; Fri, 12 May 2023 12:21:55 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-kbajaj-hyd.qualcomm.com [10.147.247.189]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 34CCLsZR029100; Fri, 12 May 2023 12:21:55 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2340697) id 6C91152974D; Fri, 12 May 2023 17:51:54 +0530 (+0530) From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley Cc: Komal Bajaj , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 09/10] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller Date: Fri, 12 May 2023 17:51:33 +0530 Message-Id: <20230512122134.24339-10-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230512122134.24339-1-quic_kbajaj@quicinc.com> References: <20230512122134.24339-1-quic_kbajaj@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: EwA_MWar3uiNsoXXrIxDCldGOtP_CnXI X-Proofpoint-GUID: EwA_MWar3uiNsoXXrIxDCldGOtP_CnXI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-12_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 mlxscore=0 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=533 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305120103 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765691224184007074?= X-GMAIL-MSGID: =?utf-8?q?1765691224184007074?= Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on QDU1000 and QRU1000 SoCs. Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index ff21e7a6b312..3c557ca27500 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1322,6 +1322,22 @@ #interconnect-cells = <2>; }; + system-cache-controller@19200000 { + compatible = "qcom,qdu1000-llcc"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>, <0 0x19b00000 0 0x80000>, + <0 0x19e00000 0 0x80000>, <0 0x19f00000 0 0x80000>, + <0 0x1a200000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; + interrupts = ; + + nvmem-cell-names = "multi_chan_ddr"; + nvmem-cells = <&multi_chan_ddr>; + }; + qfprom: efuse@221c8000 { compatible = "qcom,qdu1000-qfprom", "qcom,qfprom"; reg = <0 0x221c8000 0 0x1000>; From patchwork Fri May 12 12:21:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 93154 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp5061202vqo; Fri, 12 May 2023 05:26:08 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4pq0qZbC74i9jRK/7fosKzcQARJjFURilrYn0/9gRK4tIHmEk3wtun0cxX34giZYUY8YW5 X-Received: by 2002:a17:902:dac3:b0:1ad:b463:1318 with SMTP id q3-20020a170902dac300b001adb4631318mr11345448plx.22.1683894367974; Fri, 12 May 2023 05:26:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683894367; cv=none; d=google.com; s=arc-20160816; b=TsPEAp4pBbvV5lUA5CSdcM+6t3n88jj09l8EC1iDWeCG0tFZMi0DH3oEn3Rej7CQl1 sF9srsvDMMJoafTYXsh4qKOMaoJluKMCVhJqN8Q83qikM3zJKgB1PNX6afoaO/aDqGTi t/M9HMHvg7KPmhxXrTto5CxGpOT51Z2irc01CBlHmh4xPU2UUr1ccP0/7T6P54fpim05 BUc74qwOlPmMBYiJdfc9eY+bQ5P4JKFjcXxI0KQ1GzCPwVqhHoLSjuQoPApWsRUgs+Bu fI/R/6llvtO4R5HZ+bTmeRU4Ri/fDvkzl2BOX16gTehPAC57vh0AygGm4J2IQaFriaeP SzRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=NIMkV1VJzIXY7dIMMBQioiedQcl/BFgTMohOJYZ1TWU=; b=J7cAJBlH/TA8BCbJbEFuSz8JJKmzsWBkfcNkrYLxR/4k2Vnlm6/XBCEvPzmGTr+ZOV DZXrU9eqRkrqoqPFqxEkXvftFGR4I9/EdqRWimp/gYH/ooYntx1WpNNyPUMznFAoSUgJ TmOWzQNInQW12yBbF9NrhKSCYPDopyBgaUFSVhtfPTPTyCMyvG30IpOZtcl14l7OdGOY o25k9HNAJjUWLjOMO29MIJ7iu+ElB5EcphAk5pXD2rmyhpgdq4tBj8KIJve/6cU66bDq bgrR8AgTTAMy0hi7kMd5KvPIg2pIEJILkJRXgOlxGTlL0m7lxcVMBFqtC9hErISxjxAN bitQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=oyLFf+HV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Fri, 12 May 2023 12:22:00 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34CCLv4I029122; Fri, 12 May 2023 12:21:57 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3qdy59u1w7-1; Fri, 12 May 2023 12:21:57 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34CCLvIm029117; Fri, 12 May 2023 12:21:57 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-kbajaj-hyd.qualcomm.com [10.147.247.189]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 34CCLuew029116; Fri, 12 May 2023 12:21:57 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2340697) id 3CF2952974D; Fri, 12 May 2023 17:51:56 +0530 (+0530) From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley Cc: Komal Bajaj , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 10/10] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support Date: Fri, 12 May 2023 17:51:34 +0530 Message-Id: <20230512122134.24339-11-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230512122134.24339-1-quic_kbajaj@quicinc.com> References: <20230512122134.24339-1-quic_kbajaj@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WPEJo8Do-RyKQYwt770G-oaoxvej3oIq X-Proofpoint-ORIG-GUID: WPEJo8Do-RyKQYwt770G-oaoxvej3oIq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-12_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 clxscore=1015 mlxscore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305120103 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765691221000894162?= X-GMAIL-MSGID: =?utf-8?q?1765691221000894162?= Add LLCC configuration data for QDU1000 and QRU1000 SoCs and updating macro name for LLCC_DRE to LLCC_ECC as per the latest specification. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 65 +++++++++++++++++++++++++++++- include/linux/soc/qcom/llcc-qcom.h | 2 +- 2 files changed, 65 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 1da337e7a378..01da6be1f861 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -187,7 +187,7 @@ static const struct llcc_slice_config sc8280xp_data[] = { { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, - { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_ECC, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, @@ -358,6 +358,36 @@ static const struct llcc_slice_config sm8550_data[] = { {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, }; +static const struct llcc_slice_config qdu1000_data_2ch[] = { + {LLCC_MDMHPGRW, 7, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 512, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + +static const struct llcc_slice_config qdu1000_data_4ch[] = { + {LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 1024, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + +static const struct llcc_slice_config qdu1000_data_8ch[] = { + {LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 2048, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = { .trp_ecc_error_status0 = 0x20344, .trp_ecc_error_status1 = 0x20348, @@ -557,6 +587,38 @@ static const struct qcom_llcc_config sm8550_cfg[] = { { }, }; +static const struct qcom_llcc_config qdu1000_cfg[] = { + { + .sct_data = qdu1000_data_8ch, + .size = ARRAY_SIZE(qdu1000_data_8ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data = qdu1000_data_4ch, + .size = ARRAY_SIZE(qdu1000_data_4ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data = qdu1000_data_4ch, + .size = ARRAY_SIZE(qdu1000_data_4ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data = qdu1000_data_2ch, + .size = ARRAY_SIZE(qdu1000_data_2ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, +}; + static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; /** @@ -1125,6 +1187,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sm8350-llcc", .data = sm8350_cfg }, { .compatible = "qcom,sm8450-llcc", .data = sm8450_cfg }, { .compatible = "qcom,sm8550-llcc", .data = sm8550_cfg }, + { .compatible = "qcom,qdu1000-llcc", .data = qdu1000_cfg}, { } }; MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 423220e66026..1359ed8a8a3f 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -30,7 +30,7 @@ #define LLCC_NPU 23 #define LLCC_WLHW 24 #define LLCC_PIMEM 25 -#define LLCC_DRE 26 +#define LLCC_ECC 26 #define LLCC_CVP 28 #define LLCC_MODPE 29 #define LLCC_APTCM 30