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Signed-off-by: Devi Priya Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d9dd25695c3d..7e6a128fe1db 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -85,6 +85,7 @@ description: | The 'board' element must be one of the following strings: adp + ap-al02-c2 ap-al02-c7 ap-mi01.2 ap-mi01.6 @@ -351,6 +352,7 @@ properties: - items: - enum: + - qcom,ipq9574-ap-al02-c2 - qcom,ipq9574-ap-al02-c7 - const: qcom,ipq9574 From patchwork Wed May 10 10:43:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devi Priya X-Patchwork-Id: 92014 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp3524416vqo; Wed, 10 May 2023 03:53:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7WKDJRr7U5YWPN871Ai0yApF59Ux+z/P1b+xxW6Hvg0lv5Xn1Tdaaq8+5IPsGJ2YD+eFwO X-Received: by 2002:a05:6a20:6a2a:b0:f6:d4d:2d with SMTP id p42-20020a056a206a2a00b000f60d4d002dmr21000208pzk.31.1683716022618; Wed, 10 May 2023 03:53:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683716022; cv=none; d=google.com; s=arc-20160816; b=Dgne7GrYsHbJLVKzGjspRhBi5ooxFINrsDztqQ9XkAaoLMqG0QNr8LqXF62hYlLfO0 +k4eJGCHoC4JWQNdJOIEOjxwEHjmrx4UgSHT69Ui/JLhvzZ93AO0JIVcrTogn1TPMZq7 spLp6yCwH8qn/CpJgBDsboxZEXOODkd8/lbrIsuGLFr6caRTHsk7ErmuIUMqiAHMk0Ok RtW8XZSeNuLzdhjeOTHVBzPOOH/y9uYWy3iabeq4IQXHicvBG2Lgf4fZkt7/VV6pnjwp JXJoQLoN3DPb/skH3xBlDWaL7wvcdi7LBVKWXJjZnC8HTLKrVOcWws24nMZ+tljtlk7/ y/6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=YIHnMmHMw/x+gAuRqtxvwzS2d+0swEIvuLoxNhcrLiA=; b=0H0eIZXScN56uVckWu1aDGdx5e5xWwmkYuD2syb+YUv4cN0no7wNKT8nkiKfXM/jJE vMG0jy3LXRJ5gaFJEz5agxO2douOCgdNJDp6btwYPb/CUxIEymbMQ3ZRblIGWgRqh/GG N5a/QUWI8DL6pT4agJHd85rZAEcTcF+9g/mfQjfHL2jOb3fVB4jqdrGV0savAE5kJQsv WykrvXuFyhNlYG5POLntdolc2oOCZNvxYJvoKLu+lzhfqVb+AQumbm0xobeNOhXUupve FfwKXs9K9QATj3M9q7gAjFcxVNxPFkeyrF5u9aElP9JI8qU26+KzZIvpeJzzZbYjQF5K kLpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=o434+bks; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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This patch adds support for Console UART, SPI NOR, eMMC and SMPA1 regulator node. Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: Devi Priya --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts | 124 ++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4d7789a06186..29c862035861 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts new file mode 100644 index 000000000000..2b093e02637b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP418 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2"; + compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum supported voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1075000>; + }; + }; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <384000000>; + bus-width = <8>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", + "gpio3", "gpio6", "gpio7", + "gpio8", "gpio9"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio10"; + function = "sdc_rclk"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + spi_0_pins: spi-0-state { + pins = "gpio11", "gpio12", "gpio13", "gpio14"; + function = "blsp0_spi"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +};