From patchwork Wed May 10 09:11:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 91988 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp3480751vqo; Wed, 10 May 2023 02:22:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6la5o8Xc6FcyR24IiNzAnu67dRe4GyVVa2vMkZFpsO/HRGsEmK2hqCwOdpQc1sdmZr9Tk1 X-Received: by 2002:a05:6a20:4c8:b0:ec:6039:f76f with SMTP id 8-20020a056a2004c800b000ec6039f76fmr16339224pzd.11.1683710570819; Wed, 10 May 2023 02:22:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683710570; cv=none; d=google.com; s=arc-20160816; b=uFgwy38qFhB/LQ3371JKo/ZarOuN9FhK0rdYLWnNX8adMqQyHp0M/umRcur7tG0rU6 1dP2m3Ql3rh5cw1ncEQP98eDJYatOakdLT9BQPPOWW+OZ3urFYYyxj3V3aQlo7TbWKCd W/tKeO8NenAcVWGbg9bAqhnlPMxXB6fGHA+mebZYnHTYVall2S26B2FJkp+6H43WR1cb FSIOTsuYGS6F2PkTVEyyedp7mIdAG+Y+/sDSbrEfCMoBRsGbf+YWtiU4FRllCZqRfNoJ HBBxW9m4+LubY06xS5mILtUqkfRxIuDDOfmiqC3gjHRI/4vYTVCQHeZcO/0EmPqarV5A PUUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=cATmMTmQhtjUjg5zOA3l+3CwTVxdCdDC/M+2BA8ofDo=; b=zApebt4lFm+ePZCnyBp3S9YlOUm7OKoxPJP7q9sF6Z3DhY49kJn7tOprcA07IA9TCG gm+qSpEy1M9ZOaHp0MuCNHhMo/O08+i7I2Yh+S7LBU+Ix41G2EL8dVaPRiOBfvNWPm2J Va0yi8sKK0/CPW5Ue6tA/SN9mygVLzwgjHClw5lqXVY6U8xon+r2VSirsqfikZWGK9Te BrB42R28qAam2RkSKi/pAZZRECBP0CWN+2nuvnvErsTBPwztwqqP9eK2Z6kspHnorEPl znSg94Mpv6MxeZ81Ohm7qpOMv2h/CwimGehGCwOroWOkoS2/lPfEAnP5/Q3hsGTpFpCB kwDg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=amlogic.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p6-20020a625b06000000b006469e2271f0si4488038pfb.172.2023.05.10.02.22.37; Wed, 10 May 2023 02:22:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=amlogic.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236593AbjEJJM1 (ORCPT + 99 others); Wed, 10 May 2023 05:12:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231486AbjEJJM0 (ORCPT ); Wed, 10 May 2023 05:12:26 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F6CB30CF; Wed, 10 May 2023 02:11:35 -0700 (PDT) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Wed, 10 May 2023 17:11:25 +0800 From: Xianwei Zhao To: , , , CC: Catalin Marinas , Will Deacon , Neil Armstrong , Kevin Hilman , Rob Herring , Krzysztof Kozlowski , Xianwei Zhao Subject: [PATCH V4] arm64: dts: add support for C3 based Amlogic AW409 Date: Wed, 10 May 2023 17:11:29 +0800 Message-ID: <20230510091129.151669-1-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765498495264764724?= X-GMAIL-MSGID: =?utf-8?q?1765498495264764724?= Amlogic C3 is an advanced edge AI processor designed for smart IP camera applications. Add basic support for the C3 based Amlogic AW409 board, which describes the following components: CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Xianwei Zhao Reviewed-by: Neil Armstrong --- Link: https://lore.kernel.org/all/20230407102704.1055152-1-kelvin.zhang@amlogic.com Link: https://lore.kernel.org/all/20230307222651.2106615-2-martin.blumenstingl@googlemail.com V3 -> V4: Move Link under the --- before the changelog. V2 -> V3: Remove '256m' from filename; Keep alphabetical order of Makefile. V1 -> V2: Remove new arch, and use ARCH_MESON; Modify node name, and delete superfluous blank line. --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/amlogic-c3-c302x-aw409.dts | 29 +++++++ arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 86 +++++++++++++++++++ 3 files changed, 116 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi base-commit: ae68fb187b59bc8645974320808ab2d7c41b1833 diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index cd1c5b04890a..6f61798a109f 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts new file mode 100644 index 000000000000..edce8850b338 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-c3.dtsi" + +/ { + model = "Amlogic C302 aw409 Development Board"; + compatible = "amlogic,aw409", "amlogic,c3"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_b; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x10000000>; + }; +}; + +&uart_b { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi new file mode 100644 index 000000000000..93b335aef605 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + interrupts = ; + }; + + apb4: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_b: serial@7a000 { + compatible = "amlogic,meson-g12a-uart"; + reg = <0x0 0x7a000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + + }; + }; +};