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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id j22-20020a170906535600b00965afa154d1si1689177ejo.623.2023.05.09.05.06.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 May 2023 05:06:41 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BA329385700C for ; Tue, 9 May 2023 12:06:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id E77FE3858D37 for ; Tue, 9 May 2023 12:05:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E77FE3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp82t1683633952t3idg92v Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 09 May 2023 20:05:51 +0800 (CST) X-QQ-SSF: 01400000000000F0Q000000A0000000 X-QQ-FEAT: jXjag1m6xl6CCs09EyrmLM9WLYIjsEgUBan2A/d2gbaCIhsI7uENRjV35k3+M b2tqsAre6XgpmEWJQoD3vm5LSwc0NpUmvNusMYyIxq0CP+KX4uP6x71iF5G1e4HtzGDOfy6 rc9M85GcFQVlonWiYBsN3GLPkfFSd8xU+hTiPYUb5DHtSyMIRnGPKI7iItzK07PzR6mUyKg GvUzIqEfPL8WfeApIp0FwW/FzpnS+MhWxKsX8kd19dhmWtXc3ua65rtRcpDKLBAG32/LaKI mRSUFg1autigEcDdOzJ/jd+pGnUJgxuC2UreDkegNIorP+5ar2CNgC1Yy+LnQRmJkAg8Ov4 ZWKGSBxRFGEgakrf1BNkWCvF6irP1VcflVLJJT2IliXHziGsLcXiE5oBnpso1eIInMsjodN pYDdp2PB0fA= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 8646725518547395845 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH V2] RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT Date: Tue, 9 May 2023 20:05:50 +0800 Message-Id: <20230509120550.4093888-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765408289000387124?= X-GMAIL-MSGID: =?utf-8?q?1765418206139696145?= From: Juzhe-Zhong This incorrect codes blocks the scalable RVV auto-vectorization. Take a look at this target hook implementation of aarch64. They only have the similiar handling on TARGET_SIMD. They let movmisalign to handle scalable vector of SVE. For RVV, we should follow the same implementation of ARM SVE. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix incorrect codes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/v-2.c: Adapt testcase. * gcc.target/riscv/rvv/autovec/zve32f-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Ditto. --- gcc/config/riscv/riscv.cc | 21 +++++++------------ .../gcc.target/riscv/rvv/autovec/v-2.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/zve32f-2.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/zve32f-3.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/zve32x-2.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/zve32x-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d-2.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/zve64d-3.c | 4 ++-- .../riscv/rvv/autovec/zve64d_zvl128b-2.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/zve64f-2.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/zve64f-3.c | 4 ++-- .../riscv/rvv/autovec/zve64f_zvl128b-2.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/zve64x-2.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/zve64x-3.c | 2 +- .../riscv/rvv/autovec/zve64x_zvl128b-2.c | 2 +- 15 files changed, 32 insertions(+), 39 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8684271f8ac..ff90c44d811 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7264,27 +7264,20 @@ riscv_estimated_poly_value (poly_int64 val, return val.coeffs[0] + val.coeffs[1] * over_128 / 128; } +/* Return true if the vector misalignment factor is supported by the + target. */ bool riscv_support_vector_misalignment (machine_mode mode, const_tree type ATTRIBUTE_UNUSED, int misalignment, bool is_packed ATTRIBUTE_UNUSED) { - if (TARGET_VECTOR) - { - if (STRICT_ALIGNMENT) - { - /* Return if movmisalign pattern is not supported for this mode. */ - if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing) - return false; - - /* Misalignment factor is unknown at compile time. */ - if (misalignment == -1) - return false; - } - return true; - } + /* TODO: For RVV scalable vector auto-vectorization, we should allow + movmisalign pattern to handle misalign data movement to unblock + possible auto-vectorization. + RVV VLS auto-vectorization or SIMD auto-vectorization can be supported here + in the future. */ return default_builtin_support_vector_misalignment (mode, type, misalignment, is_packed); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c index 3d086e30081..66d8ea15f5b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c index d6199665126..7cdc174c06f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c index d5109c72045..5654a34ea5c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c index 575e9479f94..1602f5f17d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c index 50e8963033b..5cc8f1462d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c index 0d6ebc53d1a..5e38b41a5c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c index 2a72030c3bc..6a23713d1ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c index 9e236e0af1b..20429967f36 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c index 6bb6b919c77..ee37282f1f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c index 43eca9d0727..a4618e00494 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c index f1500074370..64caef5c6ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c index ede28e88dac..6a64a1a1fdf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c index d59f7362b43..a30e73371ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c index 90398db52a0..b98a8704276 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ #include "template-1.h"