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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l65-20020a633e44000000b0052c6e736ad1si1472951pga.61.2023.05.09.05.01.14; Tue, 09 May 2023 05:01:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=AGZX9hko; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235178AbjEILyp (ORCPT + 99 others); Tue, 9 May 2023 07:54:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235101AbjEILyi (ORCPT ); Tue, 9 May 2023 07:54:38 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4A413AAF; Tue, 9 May 2023 04:54:36 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3498XZeW018666; Tue, 9 May 2023 11:54:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=8H/Y6qYrga8Hk0ur6oMNeeqiF9bxrzI6PhpZZsziyI8=; b=AGZX9hkoM/xccM44UYb5O7uGyKwitWaRHhpcUxkf621dLpWlp9VB3J1FjneCRJzonZdk ByxBjVIFMpAbyhNl6rq3iVZNeTvQKCK47eXF1JvGf8tykARU9WgGRx5ABQkqKE8GToiM nL380oWHkH9YapJXWL93OvdAHnkVw6uliB+iRnvnrO4TeKiwlyMjKp8MQ6NhjU8W3GDv txODtDoZk5632jdk/85erS51m7Fj9i+f38lKk5rK1KyJvvlR8zMiCvyNbr5UCg3HBzpn 1CRb8CmloUmteZuiNULVo7Tlxf+Xgmoj3Bpf7gIX1WJlIlFFT62A1/pPr0IiIsL3Uioi Ag== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qf77f1nf1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 May 2023 11:54:27 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349BsRkr014374 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 11:54:27 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 04:54:21 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v11 1/9] dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible Date: Tue, 9 May 2023 17:24:01 +0530 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KAh2F5T0lkL1ElKCjoW3nnZHzPknGC_V X-Proofpoint-GUID: KAh2F5T0lkL1ElKCjoW3nnZHzPknGC_V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 phishscore=0 mlxlogscore=865 suspectscore=0 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090095 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765417879303755128?= X-GMAIL-MSGID: =?utf-8?q?1765417879303755128?= Document the compatible string used for the qusb2 phy in IPQ9574. Acked-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan --- Changes in v5: - Undo v4 changes Changes in v4: - Remove constraints not applicable to IPQ9574 Changes in v3: - Maintain the proper sorted order Changes in v2: - Moved ipq6018 to the proper place and placed ipq9574 next to it as suggested by Dmitry --- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 543c1a2..95eecba 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -18,13 +18,14 @@ properties: oneOf: - items: - enum: + - qcom,ipq6018-qusb2-phy - qcom,ipq8074-qusb2-phy + - qcom,ipq9574-qusb2-phy - qcom,msm8953-qusb2-phy - qcom,msm8996-qusb2-phy - qcom,msm8998-qusb2-phy - qcom,qcm2290-qusb2-phy - qcom,sdm660-qusb2-phy - - qcom,ipq6018-qusb2-phy - qcom,sm4250-qusb2-phy - qcom,sm6115-qusb2-phy - items: From patchwork Tue May 9 11:54:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 91550 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2820074vqo; Tue, 9 May 2023 05:00:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5JiyaC5dponRvx+IY0UE02T+6CokigrBU7a9WAORwLZYpwMjhrRWq3rJ4bTRU5e/OPvJxe X-Received: by 2002:a17:90a:f0cb:b0:250:7d14:d0a8 with SMTP id fa11-20020a17090af0cb00b002507d14d0a8mr7428119pjb.36.1683633636755; Tue, 09 May 2023 05:00:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683633636; cv=none; d=google.com; s=arc-20160816; b=aPoaTKwjr93Dr7vRTBo52JA2ZgDpDT1wpMlV7+xoB5lOWKCZ5ttxnLEnZ0uHb/KSUP BCFWsj0EPuc4Ox2gtQXNha7bIoDXc6IN3CMqqy2HQp7dXNQtqUheK9QapRtkPLumdBre b/Wjc9Q+UntHTxt4yiFGkGSnWuiPwqagUpAQN9d/UWCUVq5rvssKek7tUIE0zppMyJ54 +4awhdWbA/OYT/3FeehOLFY1/1IZavu326y4FuMvbd8vJKQb6k8GoBeWDlw7zFzGNbEM 0eMiHkP4k17rNYYZ9TnoTEkVpiTBX/SkcbxkSDLGvMhvsAX0yH/lO81GilSu8eEa3TzP WYSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=GVPXECU1g8S0Dk+Wl1NXtHOunWomjrF4M7NEfA8YzFo=; b=YoTQeRAO29Qg7DvDcBqb4L/JeK3fS6T4/lF7WOa5kZdpschWbS1qjBrbRpbzNdQICG eRY0IJRXzHV9cF+bxySmUaeoG7veGN5JxfxwqOp6uJSNdQUQo1EwheXZnSt1awwvVdd2 5sNam8uALI+jfq2IKSyw9b5HlshnnspX9GDIRvgL70CcVMisFLJb9hKP8eDVOlGX8u2w +zVELGwMEaruPyV1XwrC6GGTe/YB8mONr+wnXFn27UqpOF5cCg1YkdBYASdT9nd5lbBZ t1BFQMF7Zp7OwIVDvWQvDfaJ+CmD4t+bfnv9UFmZCN8/Ff00gyiqIXkg51/krCys8OHn FdQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Z1jGfWK7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Tue, 09 May 2023 11:54:33 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349BsWaV021495 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 11:54:32 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 04:54:27 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v11 2/9] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY Date: Tue, 9 May 2023 17:24:02 +0530 Message-ID: <064614c5b28f6d813634ad14a59b0bf94ac334b7.1683630932.git.quic_varada@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: syZzJzl9g01kXk8rRW5y6cKq7ANuoMCW X-Proofpoint-ORIG-GUID: syZzJzl9g01kXk8rRW5y6cKq7ANuoMCW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 suspectscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 mlxscore=0 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090095 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765417823903746295?= X-GMAIL-MSGID: =?utf-8?q?1765417823903746295?= * Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 * Making power-domains as optional since IPQ9574 doesn't have GDSCs Signed-off-by: Varadarajan Narayanan Reviewed-by: Krzysztof Kozlowski --- Changes in v11: - Have power-domains as required for non ipq9574 SoCs Changes in v10: - Remove maxItems for clocks as it is present in top level Changes in v9: - Move 'allOf' to the correct position Changes in v8: - Update clock names for ipq9574 Changes in v6: - Made power-domains optional Note: In the earlier patch sets, had used the (legacy) specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml --- .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 44 +++++++++++++++++++--- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml index c61cea4..a272c40 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,ipq9574-qmp-usb3-phy - qcom,sa8775p-qmp-usb3-uni-phy - qcom,sc8280xp-qmp-usb3-uni-phy @@ -26,11 +27,7 @@ properties: maxItems: 4 clock-names: - items: - - const: aux - - const: ref - - const: com_aux - - const: pipe + maxItems: 4 power-domains: maxItems: 1 @@ -61,7 +58,6 @@ required: - reg - clocks - clock-names - - power-domains - resets - reset-names - vdda-phy-supply @@ -70,6 +66,42 @@ required: - clock-output-names - "#phy-cells" +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-qmp-usb3-phy + then: + properties: + clock-names: + items: + - const: aux + - const: ref + - const: cfg_ahb + - const: pipe + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-qmp-usb3-uni-phy + - qcom,sc8280xp-qmp-usb3-uni-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: ref + - const: com_aux + - const: pipe + required: + - power-domains + additionalProperties: false examples: From patchwork Tue May 9 11:54:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 91569 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2838768vqo; Tue, 9 May 2023 05:25:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5zd1pEz0KtPpIQhS48Bi8DojUzSnM6m5rVjwkzyrs03cK3twZ9KuJTDIUAzNasE3coI36x X-Received: by 2002:a17:902:7d98:b0:1ac:7b13:de71 with SMTP id a24-20020a1709027d9800b001ac7b13de71mr7125466plm.37.1683635123551; Tue, 09 May 2023 05:25:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683635123; cv=none; d=google.com; s=arc-20160816; b=dY8pL5fsAgIv1Y5yKtKrzLW51nzrc8sOwDab/E1Y9Sx9DbGSBq2xlptu+4VzGccJAm i0MlquRKrcAR9l6K9giCkTAhlHYuc5ag0tY0IMB4p8wToOxn1QSgm1eZU9Ygkc2TDbB5 cdTW68jw/UxNAbPK+XxY4f7G4OERyPqj5dcTDYWb6R/puWolzZkmtkl09PMu2uTvkxXv KEyw57DkV7KYpjiGOHHzmbCZDoURnuSvEW86XBL8GUDujLxFk4+bala7G9tDkRu+mQD2 DN5ANqPeXv+O6EI/FBOrxZl0c0iAjir2XZjR0bDkjz3EzmSlAhZ6JdeIIXXXJhl2mSby XXow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=gLmwapybUc0axIZ6lsP2Y4271vrqe3iuO1ZhisTQoxw=; b=MLRgwxFaEEVfk9SLpB1qquIj01WBUrGeq2W/X0NXyMYoOlNVSB/o3BJVoh9xSLJEVN Ux56N1n7zYARJazcm9MB9M1vGuN+mGPOD3G/Wu1mJUx8744rw41TbbPkWcC7K1pIA5Fz iIKlkFkxnVRauN6YOgnl5cmmMWebJoA+y+CWRTkfJDfAWVnvc2N5JbbeU6NWpSy7dXHC rNyXNiZx1qBalo6XDh1EeeKIOnIqV39l9fpGf8uFNGWtHMptqEKTaqngjuVDlCnVury5 ChV9JA2O82QI+cGC2YKbusGy0BO/zg9pKMqqwn1ikYTbEfCdEKl+MXeWew5MNHYVHKJN GNmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=KTZBih2Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Tue, 09 May 2023 11:54:38 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349BsbLG014539 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 11:54:37 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 04:54:32 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v11 3/9] dt-bindings: usb: dwc3: Add IPQ9574 compatible Date: Tue, 9 May 2023 17:24:03 +0530 Message-ID: <3e38f926dbc6f30cb924b6720a7006c35a381a30.1683630932.git.quic_varada@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: O-Tx0HFdgoZJAmOE1lLKT1SU6fQpIamQ X-Proofpoint-GUID: O-Tx0HFdgoZJAmOE1lLKT1SU6fQpIamQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 phishscore=0 mlxlogscore=894 suspectscore=0 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090095 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765419383425351264?= X-GMAIL-MSGID: =?utf-8?q?1765419383425351264?= * Document the IPQ9574 dwc3 compatible. * Make power-domains as optional since IPQ9574 doesn't have GDSCs Reviewed-by: Rob Herring Signed-off-by: Varadarajan Narayanan --- Changes in v9: - Place ipq9574 alongwith similar SoCs instead of new entry - Make power-domains as optional since IPQ9574 doesn't have GDSCs Changes in v6: - Made power-domains as optional - Resolved all 'make dtbs_check' messages Changes in v5: - Restore removed constraints Changes in v4: - Update other relevant sections - Remove constraints not applicable to IPQ9574 --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 4a36e2b..ae24dac 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -17,6 +17,7 @@ properties: - qcom,ipq6018-dwc3 - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 + - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8994-dwc3 - qcom,msm8996-dwc3 @@ -134,7 +135,6 @@ required: - "#address-cells" - "#size-cells" - ranges - - power-domains - clocks - clock-names - interrupts @@ -178,6 +178,7 @@ allOf: compatible: contains: enum: + - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 From patchwork Tue May 9 11:54:04 2023 Content-Type: text/plain; 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+static struct clk_branch gcc_usb0_pipe_clk = { + .halt_reg = 0x2c054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2c054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &usb0_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_sleep_clk = { + .halt_reg = 0x2c058, + .clkr = { + .enable_reg = 0x2c058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb0_sleep_clk", + .parent_hws = (const struct clk_hw *[]) { + &gcc_sleep_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { F(144000, P_XO, 16, 12, 125), F(400000, P_XO, 12, 1, 5), @@ -3985,6 +4020,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, + [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, + [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 2d7b460..2cb02f7 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -214,4 +214,6 @@ #define GCC_PCIE1_PIPE_CLK 205 #define GCC_PCIE2_PIPE_CLK 206 #define GCC_PCIE3_PIPE_CLK 207 +#define GCC_USB0_PIPE_CLK 208 +#define GCC_USB0_SLEEP_CLK 209 #endif From patchwork Tue May 9 11:54:05 2023 Content-Type: text/plain; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan --- Changes in v2: - Place the entry such that the list continues to be sorted --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 2ef638b..bec6e40 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -912,6 +912,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = { .compatible = "qcom,ipq8074-qusb2-phy", .data = &msm8996_phy_cfg, }, { + .compatible = "qcom,ipq9574-qusb2-phy", + .data = &ipq6018_phy_cfg, + }, { .compatible = "qcom,msm8953-qusb2-phy", .data = &msm8996_phy_cfg, }, { From patchwork Tue May 9 11:54:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 91553 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2825486vqo; Tue, 9 May 2023 05:06:45 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7gK4WZ8hQIIX0JQYPFefTz/fSkfSCkJXfDZc3N4mwFVxu1AUVgk3H5GEe2nIzwCRnGoo4R X-Received: by 2002:a17:903:124d:b0:1a1:ca4d:120a with SMTP id u13-20020a170903124d00b001a1ca4d120amr21936754plh.7.1683634005514; Tue, 09 May 2023 05:06:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683634005; cv=none; d=google.com; s=arc-20160816; b=FLvmBTOJFVn9gCqMq0oaDp0FpbzaBx6seJMTdaZj7Mb5ZFj7O1DK9WAStUqMOAPG0t e2txyIws8SxTHgCTCsmutFqwhV5MucQ/2Mv+GZBNVs8gn2Mk79YRwr3WDhFnUwfyy490 qpVf7vCgCeNi1hzfK9yrrVLHcggFkAedca4Qdzvb6Gr1iiWZs1CrM6Ut5s92k72Mdlbu a+1BYlcGEwIzN46IhUOcl2rsLjYcNpdWmhllBwG2w7r0IvjuO6V+XNQSx90gcW4FGzI0 HFbJZrEJYQ0V3twJbQVoPqHdyIzlRKypPa7N4Ucdqv6sJJ/m8Pz8W3DtXePxUMJaKMa+ HfNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=3mciLDFWdvDBW5DWGZI7xebPtQarwtXMu3Cppxtf1Sg=; b=qfYPpLsmK4ZzrtAY+IT1rNoqrFHe76cEoQrZDiS8ntT3/Ev2Fq6Nu8Aggk3IPjZ6k1 2rv9/OpU2tvOUXx6EbCR53p7ooj42BTEh8MpGEMrlT2tszjYtqLlcg0GXz5YeJcjl1v5 uRDDDyZtrFaJvytgDnn/eX+a3nKepLeMYFDf8/D9dGHYFY2ehuWL1hU5LMxV+RetmBH1 ip2g2jDIYi14Wsn6EatsDNcmSLbPuD8HTryDOOmKGU+uORhYq3CoDKXBXKAMMc8E2nET d4Ye5CtKs97IGrzIFrdTCHMNMMPFYTEIcGgt4eZwqwtZmFP8mFjpGBLXf8ggGuPrT4n8 FYJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=l3jXTBLN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Reused clock and reset list from existing targets. Reviewed-by: Dmitry Baryshkov Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- Changes in v6: - Fix pcs_usb offset - Use correct clock names array Changes in v5: - Fix additional review comments - Use V3 register offsets Changes in v4: - Use qmp_usb_offsets for register space access Changes in v3: - Fix hex captitalization Changes in v2: - Removed unused phy register offsets - Moved the clock entries to the correct place - Maintain sorted order --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 5c039bb..6f2798b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, }; +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + /* PLL and Loop filter settings */ + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + /* SSC settings */ + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c), +}; + +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), +}; + static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), @@ -1578,6 +1660,14 @@ static const char * const qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", }; +static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = { + .serdes = 0, + .pcs = 0x800, + .pcs_usb = 0x800, + .tx = 0x200, + .rx = 0x400, +}; + static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { .serdes = 0, .pcs = 0x0200, @@ -1606,6 +1696,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { .regs = qmp_v3_usb3phy_regs_layout, }; +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { + .lanes = 1, + + .offsets = &qmp_usb_offsets_ipq9574, + + .serdes_tbl = ipq9574_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl), + .tx_tbl = ipq9574_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl), + .rx_tbl = ipq9574_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl), + .pcs_tbl = ipq9574_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl), + .clk_list = msm8996_phy_clk_l, + .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), + .reset_list = qcm2290_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, +}; + static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .lanes = 1, @@ -2631,6 +2743,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = { .compatible = "qcom,ipq8074-qmp-usb3-phy", .data = &ipq8074_usb3phy_cfg, }, { + .compatible = "qcom,ipq9574-qmp-usb3-phy", + .data = &ipq9574_usb3phy_cfg, + }, { .compatible = "qcom,msm8996-qmp-usb3-phy", .data = &msm8996_usb3phy_cfg, }, { From patchwork Tue May 9 11:54:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 91556 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2832790vqo; Tue, 9 May 2023 05:16:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ611gjvLMGtPddWj/seKhCChgcOqoPbzy/WuwquS8s2DDrro3AB9JUwX/WRKXf6zcTfmORw X-Received: by 2002:a05:6a21:158f:b0:f0:a0f4:7c5d with SMTP id nr15-20020a056a21158f00b000f0a0f47c5dmr12849699pzb.56.1683634599577; Tue, 09 May 2023 05:16:39 -0700 (PDT) ARC-Seal: i=1; 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Tue, 09 May 2023 11:55:01 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349Bsxva017888 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 11:54:59 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 04:54:54 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v11 7/9] arm64: dts: qcom: ipq9574: Add USB related nodes Date: Tue, 9 May 2023 17:24:07 +0530 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GF2OlAtSY--Fg8Q_HxI2CzE5A9yQR8Mt X-Proofpoint-GUID: GF2OlAtSY--Fg8Q_HxI2CzE5A9yQR8Mt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 impostorscore=0 spamscore=0 mlxscore=0 priorityscore=1501 adultscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090095 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765418833760502086?= X-GMAIL-MSGID: =?utf-8?q?1765418833760502086?= Add USB phy and controller related nodes SS PHY need two supplies and HS PHY needs three supplies. 0.925V and 3.3V are from fixed regulators and 1.8V is generated from PMIC's LDO Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan --- Changes in v11: - Rename dwc_0 -> usb_0_dwc3 Changes in v10: - Fix regulator definitions Changes in v8: - Change clocks order to match the bindings Changes in v7: - Change com_aux -> cfg_ahb Changes in v6: - Introduce fixed regulators for the phy - Resolved all 'make dtbs_check' messages Changes in v5: - Fix additional comments - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml - 'make dtbs_check' giving the following messages since ipq9574 doesn't have power domains. Hope this is ok /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml Changes in v4: - Use newer bindings without subnodes - Fix coding style issues Changes in v3: - Insert the nodes at proper location Changes in v2: - Fixed issues flagged by Krzysztof - Fix issues reported by make dtbs_check - Remove NOC related clocks (to be added with proper interconnect support) --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 104 ++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 93b4ba9..42b61f6 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -150,6 +150,24 @@ method = "smc"; }; + fixed_3p3: s3300 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_3p3"; + }; + + fixed_0p925: s0925 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_0p925"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -191,6 +209,45 @@ reg = <0x00060000 0x6000>; }; + usb_0_qusbphy: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board_clk>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + usb_0_qmpphy: phy@7d000 { + compatible = "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0007d000 0xa00>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&xo_board_clk>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + status = "disabled"; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk"; + }; + pcie0_phy: phy@84000 { compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x00084000 0x1000>; @@ -560,6 +617,53 @@ status = "disabled"; }; + usb3: usb@8a00000 { + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_ANOC_USB_AXI_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event"; + + resets = <&gcc GCC_USB_BCR>; + status = "disabled"; + + usb_0_dwc3: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xcd00>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = ; + phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ From patchwork Tue May 9 11:54:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 91566 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2838015vqo; Tue, 9 May 2023 05:24:16 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6qhBmqgfCllwX7oYabqqZTaI7+R0l2iY12LFovEXic5nbBJoHl8G4b4ZMgIEh7loCvPUVw X-Received: by 2002:a05:6a20:244d:b0:f3:5cf7:581b with SMTP id t13-20020a056a20244d00b000f35cf7581bmr17884630pzc.28.1683635056135; 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Tue, 09 May 2023 11:55:05 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349Bt4Fi022772 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 11:55:04 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 04:54:59 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v11 8/9] arm64: dts: qcom: ipq9574: Add LDO regulator node Date: Tue, 9 May 2023 17:24:08 +0530 Message-ID: <42bf6244582d6208f51db1a9299fe1c8afab4e14.1683630932.git.quic_varada@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ygB8CtVpKMHGGTQTMQKY8Wb0M57SIa87 X-Proofpoint-ORIG-GUID: ygB8CtVpKMHGGTQTMQKY8Wb0M57SIa87 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=776 malwarescore=0 clxscore=1015 mlxscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090095 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765419312328698323?= X-GMAIL-MSGID: =?utf-8?q?1765419312328698323?= Add LDO regulator node Signed-off-by: Varadarajan Narayanan Reviewed-by: Dmitry Baryshkov --- Changes in v10: - Add LDO regulator node --- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index bdc1434..1f5d14f 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -60,6 +60,13 @@ regulator-min-microvolt = <725000>; regulator-max-microvolt = <1075000>; }; + + mp5496_l2: l2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; }; }; From patchwork Tue May 9 11:54:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 91554 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2825999vqo; Tue, 9 May 2023 05:07:27 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4jobC+liv0bpV0Qe2d2FQTz9vSOEcwL8WjUIoTTIG9WI3oKKsn7VIM6HdYtqCilbdf019f X-Received: by 2002:a17:90a:ff17:b0:24d:e937:6670 with SMTP id ce23-20020a17090aff1700b0024de9376670mr13122479pjb.19.1683634046853; Tue, 09 May 2023 05:07:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683634046; cv=none; d=google.com; s=arc-20160816; b=nlAljN/iMRvELlewCE31NKB+AwhbWt3Np4lJBFiJEPLk6fjNaB/8Lz3+KNNgEx2X9Q rnAjMNVx8+EEdNB3PQA68Gasz5qN1IBqfriKiV7XbA3v5zapi/pQIYi9Iaxzeid2A+I2 HWa6Wq1K2BcpGUDXYgzLlxHcB/bDEAq0PXweHRVWFY2r8fnS4z39+tqiJkcfbzOuOCrO IoIYFmHBatvp/9ESU/5C/c2EASZFOq17Dd1QOOTMIOzOqo3ZYe3xujpBQEz+Sud7rjb8 C5fXJqDhe9OE2VF5IJCTrNjD+I54g6RSdCZKzfARpzWV6YPMp9fFoMpdAAXNUskrS9HE LvLw== ARC-Message-Signature: i=1; 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Tue, 09 May 2023 11:55:10 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349Bt9fg015776 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 11:55:10 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 04:55:04 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v11 9/9] arm64: dts: qcom: ipq9574: Enable USB Date: Tue, 9 May 2023 17:24:09 +0530 Message-ID: <1691872a83758cb65053dce7001e96e88dbeed2a.1683630932.git.quic_varada@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fD4avqo5DRB3IqlOVr9CjVBt-ctpVdjx X-Proofpoint-GUID: fD4avqo5DRB3IqlOVr9CjVBt-ctpVdjx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 mlxlogscore=689 mlxscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 clxscore=1015 suspectscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090095 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765418253994194965?= X-GMAIL-MSGID: =?utf-8?q?1765418253994194965?= Turn on USB related nodes Provide vdd info Signed-off-by: Varadarajan Narayanan Reviewed-by: Dmitry Baryshkov --- Changes in v11: - Rename dwc_0 -> usb_0_dwc3 - Maintain sorted order for the usb nodes Changes in v10: - Provide vdd info Changes in v5: - Move "host" mode specification to board dts - Due to dependency with earlier patches board dts filename changed ipq9574-al02-c7.dts -> ipq9574-rdp433.dts Changes in v2: - Fix node placement and coding style - "ok" -> "okay" --- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 1f5d14f..ea38098 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -188,6 +188,29 @@ }; }; +&usb_0_dwc3 { + dr_mode = "host"; +}; + +&usb_0_qmpphy { + vdda-pll-supply = <&mp5496_l2>; + vdda-phy-supply = <&fixed_0p925>; + + status = "okay"; +}; + +&usb_0_qusbphy { + vdd-supply = <&fixed_0p925>; + vdda-pll-supply = <&mp5496_l2>; + vdda-phy-dpdm-supply = <&fixed_3p3>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + &xo_board_clk { clock-frequency = <24000000>; };