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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id e2-20020a170906374200b0096152a7a561si1638219ejc.245.2023.05.09.02.29.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 May 2023 02:29:03 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 564033858288 for ; Tue, 9 May 2023 09:28:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id D971A3858C53 for ; Tue, 9 May 2023 09:28:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D971A3858C53 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1683624503tvu5dgod Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 09 May 2023 17:28:22 +0800 (CST) X-QQ-SSF: 01400000000000F0Q000000A0000000 X-QQ-FEAT: 90EFqYDyPxDpV4A/+2Xyu/blu844eqqMtcJi1Z8G4WutPiUjkR0aX83si3uAj RfOISCi6hLPEBMc8WS9e6T4xHUC++3BETOxo12DhLzC/UcjY17BSaswlPPxh6H+nHsK1ZfD TLvgfbBLzAVdxLhbsW3RB/mpriN1ryof23Nqr9eQOMwzzseWWOzObPB16fWbe0IxZ9m0HkK JiBINNVZhmDTPqGWrS7WnpX9+rgabAtKnDdLhl8Hc/45h6ggPT3UEhjKxBp6TyTaXdgFKo4 vEANR+/ZQ1eSrNmxw3i+yKhz0+t2JTdbnf2RsmMQ2suqqTaGWOoxnxo8UOuxZwoLKJ0ZTrU XnwyF0QOM3XDREWNQ4eeK2eSBYU7zA96Sy9l7FQEH3bGptOYBAe+iyUpVSYag1ChtehwlQT 09k8pmXQIBs= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 983109901164268610 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT Date: Tue, 9 May 2023 17:28:20 +0800 Message-Id: <20230509092820.658568-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765408289000387124?= X-GMAIL-MSGID: =?utf-8?q?1765408289000387124?= From: Juzhe-Zhong This incorrect codes blocks the scalable RVV auto-vectorization. Take a look at this target hook implementation of aarch64. They only have the similiar handling on TARGET_SIMD. They let movmisalign to handle scalable vector of SVE. For RVV, we should follow the same implementation of ARM SVE. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix incorrect codes. --- gcc/config/riscv/riscv.cc | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8684271f8ac..ff90c44d811 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7264,27 +7264,20 @@ riscv_estimated_poly_value (poly_int64 val, return val.coeffs[0] + val.coeffs[1] * over_128 / 128; } +/* Return true if the vector misalignment factor is supported by the + target. */ bool riscv_support_vector_misalignment (machine_mode mode, const_tree type ATTRIBUTE_UNUSED, int misalignment, bool is_packed ATTRIBUTE_UNUSED) { - if (TARGET_VECTOR) - { - if (STRICT_ALIGNMENT) - { - /* Return if movmisalign pattern is not supported for this mode. */ - if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing) - return false; - - /* Misalignment factor is unknown at compile time. */ - if (misalignment == -1) - return false; - } - return true; - } + /* TODO: For RVV scalable vector auto-vectorization, we should allow + movmisalign pattern to handle misalign data movement to unblock + possible auto-vectorization. + RVV VLS auto-vectorization or SIMD auto-vectorization can be supported here + in the future. */ return default_builtin_support_vector_misalignment (mode, type, misalignment, is_packed); }