From patchwork Tue May 9 06:48:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 91388 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2669091vqo; Mon, 8 May 2023 23:50:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4BjdkrDKMmSYz/C9mZhH1CH2Ws4nFydZ+46aXBcCv6fmBtVcTGtq9PdjuWwEEsSaTViU0v X-Received: by 2002:a05:6402:1255:b0:50b:cadd:21e6 with SMTP id l21-20020a056402125500b0050bcadd21e6mr11221676edw.8.1683615024576; Mon, 08 May 2023 23:50:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683615024; cv=none; d=google.com; s=arc-20160816; b=ilQaBqx+yVN/QxwwZcHhnVk+h8ULIL9fzecT+dRgB9fzd20CKTiDJcWVqzH9W9PSB0 AdpSINKNircNTzqlxDZIxd+aAku7vQU8r8gMv5sGPYXbUpAbUK5VZ5v8F8s4sgq7dfU7 rj4K2qjzdwwhCVYwDy9TxEgc78pu+AKyoar9+W27pqDG7GhdnDH+cfnNMigaNAqD+48V nWmsXqW0Nj6fyUiMSJR7nuF0tAuKbRO5JQeagvR1JjcaVwfODiLLYXa4ZuhxZSOCQghd TbESr2PuHejaGM73flPCJ2uRyqCyeCgV1XjcLjDAgwTvs7JpGrHAYNLy4BjbdxiowBgf YsTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=xjA9HSQPS+xnEHU8Gq4AeU+lYXbOUo3pgMnBSm9Z3uI=; b=bieipbEdoK8/diqG9HJjAjv32Pc3QfE2n2kYceHDAC7W/3LFkKxMhAHWP6GHfSGbfv qmtJ2wBTrc8pNGdmK1a02AxgR7gY5ign6nOZ65gJxKMgGVJMCICj3rhmEhSdo2xw9OCB 5fLBUeSiUTMo8xNChs4Sp8/ZGxYBhVinzhQj8qXogfL/DoQDcHdqkmt2wRfT9RN+QBZl 9zBNsub8B7t6DpprAVMe+Vy8nd5EakvkbyGhmAAZzoc5AM2dcn3V7d7HX9kReOYix5PF O7ll+hcaIxV1jABgNSSQG42KwaSahPfhnxCoxiwhIBq5P1Zq5fHp5rf3HUBqQNfx5gkx F2EA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=TL4VNHd2; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id o11-20020aa7c7cb000000b0050bcbd9b378si591589eds.502.2023.05.08.23.50.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 23:50:24 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=TL4VNHd2; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DEA3638555AA for ; Tue, 9 May 2023 06:49:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DEA3638555AA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683614993; bh=xjA9HSQPS+xnEHU8Gq4AeU+lYXbOUo3pgMnBSm9Z3uI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=TL4VNHd2gpjVl9JUP7BUmhYF+YYvw1eiioL3BcmGhOtSmWQxsDqXojaJVUcKBrkn5 WnKFs6obTR7qyZ0gOzGMYX16agMaJuQd0+9bqq8CEYRLz8VqYR8jmLRpUlNZMih3rs 3oYPWHn9l0uowQu/3dBEL+BV4lwMSL95xKAH/0FA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id BFDB4385800A for ; Tue, 9 May 2023 06:49:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BFDB4385800A Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CEEAC1063; Mon, 8 May 2023 23:49:52 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E39593F5A1; Mon, 8 May 2023 23:49:07 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 1/6] aarch64: Fix move-after-intrinsic function-body tests Date: Tue, 9 May 2023 07:48:26 +0100 Message-Id: <20230509064831.1651327-2-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230509064831.1651327-1-richard.sandiford@arm.com> References: <20230509064831.1651327-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-29.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765398307540530603?= X-GMAIL-MSGID: =?utf-8?q?1765398307540530603?= Some of the SVE ACLE asm tests tried to be agnostic about the instruction order, but only one of the alternatives was exercised in practice. This patch fixes latent typos in the other versions. gcc/testsuite/ * gcc.target/aarch64/sve2/acle/asm/aesd_u8.c: Fix expected register allocation in the case where a move occurs after the intrinsic instruction. * gcc.target/aarch64/sve2/acle/asm/aese_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c: Likewise. --- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c index 622f5cf4609..384b6ffc9aa 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c @@ -28,13 +28,13 @@ TEST_UNIFORM_Z (aesd_u8_tied2, svuint8_t, ** mov z0\.d, z1\.d ** aesd z0\.b, z0\.b, z2\.b ** | -** aesd z1\.b, z0\.b, z2\.b +** aesd z1\.b, z1\.b, z2\.b ** mov z0\.d, z1\.d ** | ** mov z0\.d, z2\.d ** aesd z0\.b, z0\.b, z1\.b ** | -** aesd z2\.b, z0\.b, z1\.b +** aesd z2\.b, z2\.b, z1\.b ** mov z0\.d, z2\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c index 6555bbb1de7..6381bce1661 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c @@ -28,13 +28,13 @@ TEST_UNIFORM_Z (aese_u8_tied2, svuint8_t, ** mov z0\.d, z1\.d ** aese z0\.b, z0\.b, z2\.b ** | -** aese z1\.b, z0\.b, z2\.b +** aese z1\.b, z1\.b, z2\.b ** mov z0\.d, z1\.d ** | ** mov z0\.d, z2\.d ** aese z0\.b, z0\.b, z1\.b ** | -** aese z2\.b, z0\.b, z1\.b +** aese z2\.b, z2\.b, z1\.b ** mov z0\.d, z2\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c index 4630595ff20..76259326467 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c @@ -19,7 +19,7 @@ TEST_UNIFORM_Z (aesimc_u8_tied1, svuint8_t, ** mov z0\.d, z1\.d ** aesimc z0\.b, z0\.b ** | -** aesimc z1\.b, z0\.b +** aesimc z1\.b, z1\.b ** mov z0\.d, z1\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c index 6e8acf48f2a..30e83d381dc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c @@ -19,7 +19,7 @@ TEST_UNIFORM_Z (aesmc_u8_tied1, svuint8_t, ** mov z0\.d, z1\.d ** aesmc z0\.b, z0\.b ** | -** aesmc z1\.b, z0\.b +** aesmc z1\.b, z1\.b ** mov z0\.d, z1\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c index 0ff5746d814..cf6a2a95235 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c @@ -24,7 +24,7 @@ TEST_UNIFORM_Z (sm4e_u32_tied2, svuint32_t, ** mov z0\.d, z1\.d ** sm4e z0\.s, z0\.s, z2\.s ** | -** sm4e z1\.s, z0\.s, z2\.s +** sm4e z1\.s, z1\.s, z2\.s ** mov z0\.d, z1\.d ** ) ** ret From patchwork Tue May 9 06:48:27 2023 Content-Type: text/plain; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id w4-20020a50fa84000000b0050bc57ac96fsi745141edr.131.2023.05.08.23.52.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 23:52:02 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=I1xwk6U+; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 584BF385291F for ; Tue, 9 May 2023 06:50:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 584BF385291F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683615053; bh=d2ZiqmH5zMtKe13MBIVwS1fTEO5TOplbmCGkelHG7GU=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=I1xwk6U+FSMMNr3ZWnHrQTjowDHUvwnOQoUlcJyeuIs7QId2ufKjE2EVCvDNPl1nd neXPZIKCyFUekTKlz8LC8B9sLj1zkckS6tOVxCkSwGrKOVBKR0IAtQheItQjFtb6TI /ZT1Guas9YR0ursQEuXsCMnojxd1JHjBP1ekFCVk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 95F7D3858C2C for ; Tue, 9 May 2023 06:49:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 95F7D3858C2C Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BAA92106F; Mon, 8 May 2023 23:49:53 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 97D5B3F5A1; Mon, 8 May 2023 23:49:08 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 2/6] aarch64: Allow moves after tied-register intrinsics Date: Tue, 9 May 2023 07:48:27 +0100 Message-Id: <20230509064831.1651327-3-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230509064831.1651327-1-richard.sandiford@arm.com> References: <20230509064831.1651327-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-28.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_35_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765398410140661212?= X-GMAIL-MSGID: =?utf-8?q?1765398410140661212?= Some ACLE intrinsics map to instructions that tie the output operand to an input operand. If all the operands are allocated to different registers, and if MOVPRFX can't be used, we will need a move either before the instruction or after it. Many tests only matched the "before" case; this patch makes them accept the "after" case too. gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c: Allow moves to occur after the intrinsic instruction, rather than requiring them to happen before. * gcc.target/aarch64/advsimd-intrinsics/bfdot-1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c: Likewise. * gcc.target/aarch64/sve/acle/asm/adda_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/adda_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/adda_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/brka_b.c: Likewise. * gcc.target/aarch64/sve/acle/asm/brkb_b.c: Likewise. * gcc.target/aarch64/sve/acle/asm/brkn_b.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clasta_bf16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clasta_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clasta_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clasta_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clastb_bf16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clastb_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clastb_f32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/clastb_f64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pfirst_b.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pnext_b16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pnext_b32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pnext_b64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/pnext_b8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sli_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sri_u8.c: Likewise. --- .../aarch64/advsimd-intrinsics/bfcvtnq2-untied.c | 5 +++++ .../aarch64/advsimd-intrinsics/bfdot-1.c | 10 ++++++++++ .../aarch64/advsimd-intrinsics/vdot-3-1.c | 10 ++++++++++ .../gcc.target/aarch64/sve/acle/asm/adda_f16.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/adda_f32.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/adda_f64.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/brka_b.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/brkb_b.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/brkn_b.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/clasta_bf16.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/clasta_f16.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/clasta_f32.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/clasta_f64.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/clastb_bf16.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/clastb_f16.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/clastb_f32.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/clastb_f64.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/pfirst_b.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/pnext_b16.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/pnext_b32.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/pnext_b64.c | 5 +++++ .../gcc.target/aarch64/sve/acle/asm/pnext_b8.c | 5 +++++ .../gcc.target/aarch64/sve2/acle/asm/sli_s16.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sli_s32.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sli_s64.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sli_s8.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sli_u16.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sli_u32.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sli_u64.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sli_u8.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sri_s16.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sri_s32.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sri_s64.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sri_s8.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sri_u16.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sri_u32.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sri_u64.c | 15 +++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/sri_u8.c | 15 +++++++++++++++ 38 files changed, 360 insertions(+) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c index 4b730e39d4e..1143bb797bc 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c @@ -9,8 +9,13 @@ /* **test_bfcvtnq2_untied: +** ( ** mov v0.16b, v1.16b ** bfcvtn2 v0.8h, v2.4s +** | +** bfcvtn2 v1.8h, v2.4s +** mov v0.16b, v1.16b +** ) ** ret */ bfloat16x8_t test_bfcvtnq2_untied (bfloat16x8_t unused, bfloat16x8_t inactive, diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfdot-1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfdot-1.c index ad51507731b..a5baf57cd5c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfdot-1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfdot-1.c @@ -69,8 +69,13 @@ float32x4_t ufooq_lane(float32x4_t r, bfloat16x8_t x, bfloat16x4_t y) /* **ufoo_untied: +** ( ** mov v0.8b, v1.8b ** bfdot v0.2s, (v2.4h, v3.4h|v3.4h, v2.4h) +** | +** bfdot v1.2s, (v2.4h, v3.4h|v3.4h, v2.4h) +** mov v0.8b, v1.8b +** ) ** ret */ float32x2_t ufoo_untied(float32x4_t unused, float32x2_t r, bfloat16x4_t x, bfloat16x4_t y) @@ -80,8 +85,13 @@ float32x2_t ufoo_untied(float32x4_t unused, float32x2_t r, bfloat16x4_t x, bfloa /* **ufooq_lane_untied: +** ( ** mov v0.16b, v1.16b ** bfdot v0.4s, v2.8h, v3.2h\[1\] +** | +** bfdot v1.4s, v2.8h, v3.2h\[1\] +** mov v0.16b, v1.16b +** ) ** ret */ float32x4_t ufooq_lane_untied(float32x4_t unused, float32x4_t r, bfloat16x8_t x, bfloat16x4_t y) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c index ac4f821e771..a245b9f792a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdot-3-1.c @@ -114,8 +114,13 @@ int32x4_t sfooq_laneq (int32x4_t r, int8x16_t x, uint8x16_t y) /* **ufoo_untied: +** ( ** mov v0\.8b, v1\.8b ** usdot v0\.2s, v2\.8b, v3\.8b +** | +** usdot v1\.2s, v2\.8b, v3\.8b +** mov v0\.8b, v1\.8b +** ) ** ret */ int32x2_t ufoo_untied (int32x2_t unused, int32x2_t r, uint8x8_t x, int8x8_t y) @@ -125,8 +130,13 @@ int32x2_t ufoo_untied (int32x2_t unused, int32x2_t r, uint8x8_t x, int8x8_t y) /* **ufooq_laneq_untied: +** ( ** mov v0\.16b, v1\.16b ** usdot v0\.4s, v2\.16b, v3\.4b\[3\] +** | +** usdot v1\.4s, v2\.16b, v3\.4b\[3\] +** mov v0\.16b, v1\.16b +** ) ** ret */ int32x4_t ufooq_laneq_untied (int32x2_t unused, int32x4_t r, uint8x16_t x, int8x16_t y) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f16.c index 6c6bfa1c294..642c45ab492 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f16.c @@ -13,8 +13,13 @@ TEST_FOLD_LEFT_D (adda_d0_f16, float16_t, svfloat16_t, /* ** adda_d1_f16: +** ( ** mov v0\.h\[0\], v1\.h\[0\] ** fadda h0, p0, h0, z2\.h +** | +** fadda h1, p0, h1, z2\.h +** mov v0\.h\[0\], v1\.h\[0\] +** ) ** ret */ TEST_FOLD_LEFT_D (adda_d1_f16, float16_t, svfloat16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f32.c index 8b2a1dd1c68..79bdd3d8048 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f32.c @@ -13,8 +13,13 @@ TEST_FOLD_LEFT_D (adda_d0_f32, float32_t, svfloat32_t, /* ** adda_d1_f32: +** ( ** fmov s0, s1 ** fadda s0, p0, s0, z2\.s +** | +** fadda s1, p0, s1, z2\.s +** fmov s0, s1 +** ) ** ret */ TEST_FOLD_LEFT_D (adda_d1_f32, float32_t, svfloat32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f64.c index 90a56420a6a..c8f56772218 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f64.c @@ -13,8 +13,13 @@ TEST_FOLD_LEFT_D (adda_d0_f64, float64_t, svfloat64_t, /* ** adda_d1_f64: +** ( ** fmov d0, d1 ** fadda d0, p0, d0, z2\.d +** | +** fadda d1, p0, d1, z2\.d +** fmov d0, d1 +** ) ** ret */ TEST_FOLD_LEFT_D (adda_d1_f64, float64_t, svfloat64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brka_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brka_b.c index 63426cf947d..7a20a22d128 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brka_b.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brka_b.c @@ -27,8 +27,13 @@ TEST_UNIFORM_P (brka_b_m_tied2, /* ** brka_b_m_untied: +** ( ** mov p0\.b, p2\.b ** brka p0\.b, p3/m, p1\.b +** | +** brka p2\.b, p3/m, p1\.b +** mov p0\.b, p2\.b +** ) ** ret */ TEST_UNIFORM_P (brka_b_m_untied, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkb_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkb_b.c index 4f9a2c2d7b9..f1c8c436863 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkb_b.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkb_b.c @@ -27,8 +27,13 @@ TEST_UNIFORM_P (brkb_b_m_tied2, /* ** brkb_b_m_untied: +** ( ** mov p0\.b, p2\.b ** brkb p0\.b, p3/m, p1\.b +** | +** brkb p2\.b, p3/m, p1\.b +** mov p0\.b, p2\.b +** ) ** ret */ TEST_UNIFORM_P (brkb_b_m_untied, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkn_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkn_b.c index 229a5fff9eb..69e8eb6b0e5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkn_b.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkn_b.c @@ -18,8 +18,13 @@ TEST_UNIFORM_P (brkn_b_z_tied2, /* ** brkn_b_z_untied: +** ( ** mov p0\.b, p2\.b ** brkn p0\.b, p3/z, p1\.b, p0\.b +** | +** brkn p2\.b, p3/z, p1\.b, p2\.b +** mov p0\.b, p2\.b +** ) ** ret */ TEST_UNIFORM_P (brkn_b_z_untied, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_bf16.c index a15e34400f6..54a1d1af178 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_bf16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_bf16.c @@ -43,8 +43,13 @@ TEST_FOLD_LEFT_D (clasta_d0_bf16, bfloat16_t, svbfloat16_t, /* ** clasta_d1_bf16: +** ( ** mov v0\.h\[0\], v1\.h\[0\] ** clasta h0, p0, h0, z2\.h +** | +** clasta h1, p0, h1, z2\.h +** mov v0\.h\[0\], v1\.h\[0\] +** ) ** ret */ TEST_FOLD_LEFT_D (clasta_d1_bf16, bfloat16_t, svbfloat16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f16.c index d9a980f60c0..243cad40f56 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f16.c @@ -43,8 +43,13 @@ TEST_FOLD_LEFT_D (clasta_d0_f16, float16_t, svfloat16_t, /* ** clasta_d1_f16: +** ( ** mov v0\.h\[0\], v1\.h\[0\] ** clasta h0, p0, h0, z2\.h +** | +** clasta h1, p0, h1, z2\.h +** mov v0\.h\[0\], v1\.h\[0\] +** ) ** ret */ TEST_FOLD_LEFT_D (clasta_d1_f16, float16_t, svfloat16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f32.c index cac01fa6d64..44e700ada9a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f32.c @@ -43,8 +43,13 @@ TEST_FOLD_LEFT_D (clasta_d0_f32, float32_t, svfloat32_t, /* ** clasta_d1_f32: +** ( ** fmov s0, s1 ** clasta s0, p0, s0, z2\.s +** | +** clasta s1, p0, s1, z2\.s +** fmov s0, s1 +** ) ** ret */ TEST_FOLD_LEFT_D (clasta_d1_f32, float32_t, svfloat32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f64.c index 43b93553ba8..fb147d51f0c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f64.c @@ -43,8 +43,13 @@ TEST_FOLD_LEFT_D (clasta_d0_f64, float64_t, svfloat64_t, /* ** clasta_d1_f64: +** ( ** fmov d0, d1 ** clasta d0, p0, d0, z2\.d +** | +** clasta d1, p0, d1, z2\.d +** fmov d0, d1 +** ) ** ret */ TEST_FOLD_LEFT_D (clasta_d1_f64, float64_t, svfloat64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_bf16.c index 235fd1b4ed6..8dcb9a152b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_bf16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_bf16.c @@ -43,8 +43,13 @@ TEST_FOLD_LEFT_D (clastb_d0_bf16, bfloat16_t, svbfloat16_t, /* ** clastb_d1_bf16: +** ( ** mov v0\.h\[0\], v1\.h\[0\] ** clastb h0, p0, h0, z2\.h +** | +** clastb h1, p0, h1, z2\.h +** mov v0\.h\[0\], v1\.h\[0\] +** ) ** ret */ TEST_FOLD_LEFT_D (clastb_d1_bf16, bfloat16_t, svbfloat16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f16.c index e56d7688a1c..08e63cee9e8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f16.c @@ -43,8 +43,13 @@ TEST_FOLD_LEFT_D (clastb_d0_f16, float16_t, svfloat16_t, /* ** clastb_d1_f16: +** ( ** mov v0\.h\[0\], v1\.h\[0\] ** clastb h0, p0, h0, z2\.h +** | +** clastb h1, p0, h1, z2\.h +** mov v0\.h\[0\], v1\.h\[0\] +** ) ** ret */ TEST_FOLD_LEFT_D (clastb_d1_f16, float16_t, svfloat16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f32.c index c580d13064b..8d71344b2ce 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f32.c @@ -43,8 +43,13 @@ TEST_FOLD_LEFT_D (clastb_d0_f32, float32_t, svfloat32_t, /* ** clastb_d1_f32: +** ( ** fmov s0, s1 ** clastb s0, p0, s0, z2\.s +** | +** clastb s1, p0, s1, z2\.s +** fmov s0, s1 +** ) ** ret */ TEST_FOLD_LEFT_D (clastb_d1_f32, float32_t, svfloat32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f64.c index 217a76f5112..6b24dcad17e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f64.c @@ -43,8 +43,13 @@ TEST_FOLD_LEFT_D (clastb_d0_f64, float64_t, svfloat64_t, /* ** clastb_d1_f64: +** ( ** fmov d0, d1 ** clastb d0, p0, d0, z2\.d +** | +** clastb d1, p0, d1, z2\.d +** fmov d0, d1 +** ) ** ret */ TEST_FOLD_LEFT_D (clastb_d1_f64, float64_t, svfloat64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfirst_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfirst_b.c index a32099656cc..9ec5f00c7f1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfirst_b.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfirst_b.c @@ -13,8 +13,13 @@ TEST_UNIFORM_P (pfirst_b_tied1, /* ** pfirst_b_untied: +** ( ** mov p0\.b, p1\.b ** pfirst p0\.b, p3, p0\.b +** | +** pfirst p1\.b, p3, p1\.b +** mov p0\.b, p1\.b +** ) ** ret */ TEST_UNIFORM_P (pfirst_b_untied, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b16.c index ad0efe5e711..efb76e8ba8a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b16.c @@ -13,8 +13,13 @@ TEST_UNIFORM_P (pnext_b16_tied1, /* ** pnext_b16_untied: +** ( ** mov p0\.b, p1\.b ** pnext p0\.h, p3, p0\.h +** | +** pnext p1\.h, p3, p1\.h +** mov p0\.b, p1\.b +** ) ** ret */ TEST_UNIFORM_P (pnext_b16_untied, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b32.c index a0030fae18d..1f57253fbf1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b32.c @@ -13,8 +13,13 @@ TEST_UNIFORM_P (pnext_b32_tied1, /* ** pnext_b32_untied: +** ( ** mov p0\.b, p1\.b ** pnext p0\.s, p3, p0\.s +** | +** pnext p1\.s, p3, p1\.s +** mov p0\.b, p1\.b +** ) ** ret */ TEST_UNIFORM_P (pnext_b32_untied, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b64.c index 59db2f04f2a..eed5a56f134 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b64.c @@ -13,8 +13,13 @@ TEST_UNIFORM_P (pnext_b64_tied1, /* ** pnext_b64_untied: +** ( ** mov p0\.b, p1\.b ** pnext p0\.d, p3, p0\.d +** | +** pnext p1\.d, p3, p1\.d +** mov p0\.b, p1\.b +** ) ** ret */ TEST_UNIFORM_P (pnext_b64_untied, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b8.c index cfc2e907c25..a36d43c4cff 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b8.c @@ -13,8 +13,13 @@ TEST_UNIFORM_P (pnext_b8_tied1, /* ** pnext_b8_untied: +** ( ** mov p0\.b, p1\.b ** pnext p0\.b, p3, p0\.b +** | +** pnext p1\.b, p3, p1\.b +** mov p0\.b, p1\.b +** ) ** ret */ TEST_UNIFORM_P (pnext_b8_untied, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s16.c index 6772a5620d2..d91d499da5a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s16.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sli_0_s16_tied2, svint16_t, /* ** sli_0_s16_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.h, z2\.h, #0 +** | +** sli z1\.h, z2\.h, #0 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_0_s16_untied, svint16_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sli_1_s16_tied2, svint16_t, /* ** sli_1_s16_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.h, z2\.h, #1 +** | +** sli z1\.h, z2\.h, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_1_s16_untied, svint16_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sli_15_s16_tied2, svint16_t, /* ** sli_15_s16_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.h, z2\.h, #15 +** | +** sli z1\.h, z2\.h, #15 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_15_s16_untied, svint16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s32.c index 023e7c40d3e..3ae507c432c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s32.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sli_0_s32_tied2, svint32_t, /* ** sli_0_s32_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.s, z2\.s, #0 +** | +** sli z1\.s, z2\.s, #0 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_0_s32_untied, svint32_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sli_1_s32_tied2, svint32_t, /* ** sli_1_s32_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.s, z2\.s, #1 +** | +** sli z1\.s, z2\.s, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_1_s32_untied, svint32_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sli_31_s32_tied2, svint32_t, /* ** sli_31_s32_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.s, z2\.s, #31 +** | +** sli z1\.s, z2\.s, #31 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_31_s32_untied, svint32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s64.c index c37db1b4796..93c5723a804 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s64.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sli_0_s64_tied2, svint64_t, /* ** sli_0_s64_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.d, z2\.d, #0 +** | +** sli z1\.d, z2\.d, #0 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_0_s64_untied, svint64_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sli_1_s64_tied2, svint64_t, /* ** sli_1_s64_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.d, z2\.d, #1 +** | +** sli z1\.d, z2\.d, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_1_s64_untied, svint64_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sli_63_s64_tied2, svint64_t, /* ** sli_63_s64_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.d, z2\.d, #63 +** | +** sli z1\.d, z2\.d, #63 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_63_s64_untied, svint64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s8.c index ea0dcdc1871..5ac336f76d1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_s8.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sli_0_s8_tied2, svint8_t, /* ** sli_0_s8_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.b, z2\.b, #0 +** | +** sli z1\.b, z2\.b, #0 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_0_s8_untied, svint8_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sli_1_s8_tied2, svint8_t, /* ** sli_1_s8_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.b, z2\.b, #1 +** | +** sli z1\.b, z2\.b, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_1_s8_untied, svint8_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sli_7_s8_tied2, svint8_t, /* ** sli_7_s8_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.b, z2\.b, #7 +** | +** sli z1\.b, z2\.b, #7 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_7_s8_untied, svint8_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u16.c index 475c00ea6a4..b6cbb55b8a0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u16.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sli_0_u16_tied2, svuint16_t, /* ** sli_0_u16_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.h, z2\.h, #0 +** | +** sli z1\.h, z2\.h, #0 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_0_u16_untied, svuint16_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sli_1_u16_tied2, svuint16_t, /* ** sli_1_u16_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.h, z2\.h, #1 +** | +** sli z1\.h, z2\.h, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_1_u16_untied, svuint16_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sli_15_u16_tied2, svuint16_t, /* ** sli_15_u16_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.h, z2\.h, #15 +** | +** sli z1\.h, z2\.h, #15 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_15_u16_untied, svuint16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u32.c index 52bd8370e5f..654f4b6d670 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u32.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sli_0_u32_tied2, svuint32_t, /* ** sli_0_u32_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.s, z2\.s, #0 +** | +** sli z1\.s, z2\.s, #0 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_0_u32_untied, svuint32_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sli_1_u32_tied2, svuint32_t, /* ** sli_1_u32_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.s, z2\.s, #1 +** | +** sli z1\.s, z2\.s, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_1_u32_untied, svuint32_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sli_31_u32_tied2, svuint32_t, /* ** sli_31_u32_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.s, z2\.s, #31 +** | +** sli z1\.s, z2\.s, #31 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_31_u32_untied, svuint32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u64.c index ab75ba2e6d5..c5466a295cc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u64.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sli_0_u64_tied2, svuint64_t, /* ** sli_0_u64_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.d, z2\.d, #0 +** | +** sli z1\.d, z2\.d, #0 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_0_u64_untied, svuint64_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sli_1_u64_tied2, svuint64_t, /* ** sli_1_u64_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.d, z2\.d, #1 +** | +** sli z1\.d, z2\.d, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_1_u64_untied, svuint64_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sli_63_u64_tied2, svuint64_t, /* ** sli_63_u64_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.d, z2\.d, #63 +** | +** sli z1\.d, z2\.d, #63 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_63_u64_untied, svuint64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u8.c index e2207c3c466..2b3533f5e71 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sli_u8.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sli_0_u8_tied2, svuint8_t, /* ** sli_0_u8_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.b, z2\.b, #0 +** | +** sli z1\.b, z2\.b, #0 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_0_u8_untied, svuint8_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sli_1_u8_tied2, svuint8_t, /* ** sli_1_u8_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.b, z2\.b, #1 +** | +** sli z1\.b, z2\.b, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_1_u8_untied, svuint8_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sli_7_u8_tied2, svuint8_t, /* ** sli_7_u8_untied: +** ( ** mov z0\.d, z1\.d ** sli z0\.b, z2\.b, #7 +** | +** sli z1\.b, z2\.b, #7 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sli_7_u8_untied, svuint8_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s16.c index 177fbb20d62..16cb73ce542 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s16.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sri_1_s16_tied2, svint16_t, /* ** sri_1_s16_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.h, z2\.h, #1 +** | +** sri z1\.h, z2\.h, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_1_s16_untied, svint16_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sri_2_s16_tied2, svint16_t, /* ** sri_2_s16_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.h, z2\.h, #2 +** | +** sri z1\.h, z2\.h, #2 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_2_s16_untied, svint16_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sri_16_s16_tied2, svint16_t, /* ** sri_16_s16_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.h, z2\.h, #16 +** | +** sri z1\.h, z2\.h, #16 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_16_s16_untied, svint16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s32.c index 27d6c99c3a0..3c69f622d74 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s32.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sri_1_s32_tied2, svint32_t, /* ** sri_1_s32_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.s, z2\.s, #1 +** | +** sri z1\.s, z2\.s, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_1_s32_untied, svint32_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sri_2_s32_tied2, svint32_t, /* ** sri_2_s32_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.s, z2\.s, #2 +** | +** sri z1\.s, z2\.s, #2 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_2_s32_untied, svint32_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sri_32_s32_tied2, svint32_t, /* ** sri_32_s32_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.s, z2\.s, #32 +** | +** sri z1\.s, z2\.s, #32 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_32_s32_untied, svint32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s64.c index 021613d0179..5c64e1bb51f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s64.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sri_1_s64_tied2, svint64_t, /* ** sri_1_s64_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.d, z2\.d, #1 +** | +** sri z1\.d, z2\.d, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_1_s64_untied, svint64_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sri_2_s64_tied2, svint64_t, /* ** sri_2_s64_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.d, z2\.d, #2 +** | +** sri z1\.d, z2\.d, #2 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_2_s64_untied, svint64_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sri_64_s64_tied2, svint64_t, /* ** sri_64_s64_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.d, z2\.d, #64 +** | +** sri z1\.d, z2\.d, #64 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_64_s64_untied, svint64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s8.c index 0bfa2678559..1871bb47645 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_s8.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sri_1_s8_tied2, svint8_t, /* ** sri_1_s8_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.b, z2\.b, #1 +** | +** sri z1\.b, z2\.b, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_1_s8_untied, svint8_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sri_2_s8_tied2, svint8_t, /* ** sri_2_s8_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.b, z2\.b, #2 +** | +** sri z1\.b, z2\.b, #2 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_2_s8_untied, svint8_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sri_8_s8_tied2, svint8_t, /* ** sri_8_s8_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.b, z2\.b, #8 +** | +** sri z1\.b, z2\.b, #8 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_8_s8_untied, svint8_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u16.c index 2f12dc90857..ce6e838f7db 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u16.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sri_1_u16_tied2, svuint16_t, /* ** sri_1_u16_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.h, z2\.h, #1 +** | +** sri z1\.h, z2\.h, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_1_u16_untied, svuint16_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sri_2_u16_tied2, svuint16_t, /* ** sri_2_u16_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.h, z2\.h, #2 +** | +** sri z1\.h, z2\.h, #2 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_2_u16_untied, svuint16_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sri_16_u16_tied2, svuint16_t, /* ** sri_16_u16_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.h, z2\.h, #16 +** | +** sri z1\.h, z2\.h, #16 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_16_u16_untied, svuint16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u32.c index d4d107f55cc..7cf6fea771b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u32.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sri_1_u32_tied2, svuint32_t, /* ** sri_1_u32_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.s, z2\.s, #1 +** | +** sri z1\.s, z2\.s, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_1_u32_untied, svuint32_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sri_2_u32_tied2, svuint32_t, /* ** sri_2_u32_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.s, z2\.s, #2 +** | +** sri z1\.s, z2\.s, #2 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_2_u32_untied, svuint32_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sri_32_u32_tied2, svuint32_t, /* ** sri_32_u32_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.s, z2\.s, #32 +** | +** sri z1\.s, z2\.s, #32 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_32_u32_untied, svuint32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u64.c index 41d67346f25..be61f85f265 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u64.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sri_1_u64_tied2, svuint64_t, /* ** sri_1_u64_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.d, z2\.d, #1 +** | +** sri z1\.d, z2\.d, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_1_u64_untied, svuint64_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sri_2_u64_tied2, svuint64_t, /* ** sri_2_u64_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.d, z2\.d, #2 +** | +** sri z1\.d, z2\.d, #2 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_2_u64_untied, svuint64_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sri_64_u64_tied2, svuint64_t, /* ** sri_64_u64_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.d, z2\.d, #64 +** | +** sri z1\.d, z2\.d, #64 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_64_u64_untied, svuint64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u8.c index 0aa6a543860..84de5a2b2e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sri_u8.c @@ -18,8 +18,13 @@ TEST_UNIFORM_Z (sri_1_u8_tied2, svuint8_t, /* ** sri_1_u8_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.b, z2\.b, #1 +** | +** sri z1\.b, z2\.b, #1 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_1_u8_untied, svuint8_t, @@ -42,8 +47,13 @@ TEST_UNIFORM_Z (sri_2_u8_tied2, svuint8_t, /* ** sri_2_u8_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.b, z2\.b, #2 +** | +** sri z1\.b, z2\.b, #2 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_2_u8_untied, svuint8_t, @@ -66,8 +76,13 @@ TEST_UNIFORM_Z (sri_8_u8_tied2, svuint8_t, /* ** sri_8_u8_untied: +** ( ** mov z0\.d, z1\.d ** sri z0\.b, z2\.b, #8 +** | +** sri z1\.b, z2\.b, #8 +** mov z0\.d, z1\.d +** ) ** ret */ TEST_UNIFORM_Z (sri_8_u8_untied, svuint8_t, From patchwork Tue May 9 06:48:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 91389 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2669158vqo; Mon, 8 May 2023 23:50:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ48kDB0BeBWBTMZ8L5CYuuAgX1lM8vroCkz83E4ISoz8qK4nW73Otf1OA6RBDK6UXbJ+LSw X-Received: by 2002:a17:907:6d06:b0:966:4d11:7887 with SMTP id sa6-20020a1709076d0600b009664d117887mr5781286ejc.4.1683615035198; Mon, 08 May 2023 23:50:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683615035; cv=none; d=google.com; s=arc-20160816; b=CUCDngLfvX9nB3lf5mBFXWzwBWjyc9oTzL6bcizWcPR8LBQoQUWI8b3TBu+nqwYIJj fJcrSNp90zZZqYawP0nqQJYERIGZbEg0vJyL9rSuEhyj9ZErMTHlhIo++YOZz4dBWoqG 7xmUdYCmlmb8ErhXT65Gbc6nWRB99OETj/ZVdstVCt2aZ3dPWjVIZIE8+DwE9dAXrOpy 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[8.43.85.97]) by mx.google.com with ESMTPS id sb7-20020a1709076d8700b00969f7861d71si489409ejc.873.2023.05.08.23.50.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 23:50:35 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="M/GX+vKj"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C57E93858C1F for ; Tue, 9 May 2023 06:49:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C57E93858C1F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683614999; bh=dB47TAjNL2uMjWd97UtJ9YATzSeMsHivr5NUCfpeZO8=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=M/GX+vKjkcYYJd9IK54lRo1m8OqTN5WsfNspnWr51RXn7Xxy/OK8oVKOgmEyVjP36 gSomtfBmNZcBvnU4UGe/mUItbhkO5aDW/iqBptNAcS1EGFuFc2olCzLyM11xRPkc8P WHguMY7TAkw7P2s/bn6J+Qu55FM7V3bApFtKgUps= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 653553857706 for ; Tue, 9 May 2023 06:49:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 653553857706 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 89E891576; Mon, 8 May 2023 23:49:54 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 82E073F5A1; Mon, 8 May 2023 23:49:09 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 3/6] aarch64: Relax ordering requirements in SVE dup tests Date: Tue, 9 May 2023 07:48:28 +0100 Message-Id: <20230509064831.1651327-4-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230509064831.1651327-1-richard.sandiford@arm.com> References: <20230509064831.1651327-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-30.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765398318815466069?= X-GMAIL-MSGID: =?utf-8?q?1765398318815466069?= Some of the svdup tests expand to a SEL between two constant vectors. This patch allows the constants to be formed in either order. gcc/testsuite/ * gcc.target/aarch64/sve/acle/asm/dup_s16.c: When using SEL to select between two constant vectors, allow the constant moves to appear in either order. * gcc.target/aarch64/sve/acle/asm/dup_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dup_u64.c: Likewise. --- .../gcc.target/aarch64/sve/acle/asm/dup_s16.c | 72 +++++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_s32.c | 60 ++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_s64.c | 60 ++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_u16.c | 72 +++++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_u32.c | 60 ++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_u64.c | 60 ++++++++++++++++ 6 files changed, 384 insertions(+) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c index 21ab6f63e37..9c91a5bbad9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c @@ -611,9 +611,15 @@ TEST_UNIFORM_Z (dup_127_s16_z, svint16_t, /* ** dup_128_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #128 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #128 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_128_s16_z, svint16_t, @@ -632,9 +638,15 @@ TEST_UNIFORM_Z (dup_253_s16_z, svint16_t, /* ** dup_254_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #254 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #254 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_254_s16_z, svint16_t, @@ -643,9 +655,15 @@ TEST_UNIFORM_Z (dup_254_s16_z, svint16_t, /* ** dup_255_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #255 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_255_s16_z, svint16_t, @@ -663,9 +681,15 @@ TEST_UNIFORM_Z (dup_256_s16_z, svint16_t, /* ** dup_257_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+)\.b, #1 ** sel z0\.h, p0, \2\.h, \1\.h +** | +** mov (z[0-9]+)\.b, #1 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3\.h, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_257_s16_z, svint16_t, @@ -702,9 +726,15 @@ TEST_UNIFORM_Z (dup_7ffd_s16_z, svint16_t, /* ** dup_7ffe_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #32766 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #32766 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_7ffe_s16_z, svint16_t, @@ -713,9 +743,15 @@ TEST_UNIFORM_Z (dup_7ffe_s16_z, svint16_t, /* ** dup_7fff_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #32767 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_7fff_s16_z, svint16_t, @@ -742,9 +778,15 @@ TEST_UNIFORM_Z (dup_m128_s16_z, svint16_t, /* ** dup_m129_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-129 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-129 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m129_s16_z, svint16_t, @@ -763,9 +805,15 @@ TEST_UNIFORM_Z (dup_m254_s16_z, svint16_t, /* ** dup_m255_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-255 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m255_s16_z, svint16_t, @@ -783,9 +831,15 @@ TEST_UNIFORM_Z (dup_m256_s16_z, svint16_t, /* ** dup_m257_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-257 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-257 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m257_s16_z, svint16_t, @@ -794,9 +848,15 @@ TEST_UNIFORM_Z (dup_m257_s16_z, svint16_t, /* ** dup_m258_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+)\.b, #-2 ** sel z0\.h, p0, \2\.h, \1\.h +** | +** mov (z[0-9]+)\.b, #-2 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3\.h, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m258_s16_z, svint16_t, @@ -828,9 +888,15 @@ TEST_UNIFORM_Z (dup_m7f00_s16_z, svint16_t, /* ** dup_m7f01_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-32513 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-32513 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m7f01_s16_z, svint16_t, @@ -849,9 +915,15 @@ TEST_UNIFORM_Z (dup_m7ffe_s16_z, svint16_t, /* ** dup_m7fff_s16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-32767 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m7fff_s16_z, svint16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c index 500ec48b34a..1cfecd962a4 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c @@ -603,9 +603,15 @@ TEST_UNIFORM_Z (dup_127_s32_z, svint32_t, /* ** dup_128_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #128 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #128 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_128_s32_z, svint32_t, @@ -624,9 +630,15 @@ TEST_UNIFORM_Z (dup_253_s32_z, svint32_t, /* ** dup_254_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #254 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #254 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_254_s32_z, svint32_t, @@ -635,9 +647,15 @@ TEST_UNIFORM_Z (dup_254_s32_z, svint32_t, /* ** dup_255_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #255 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_255_s32_z, svint32_t, @@ -688,9 +706,15 @@ TEST_UNIFORM_Z (dup_7ffd_s32_z, svint32_t, /* ** dup_7ffe_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #32766 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #32766 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_7ffe_s32_z, svint32_t, @@ -699,9 +723,15 @@ TEST_UNIFORM_Z (dup_7ffe_s32_z, svint32_t, /* ** dup_7fff_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #32767 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_7fff_s32_z, svint32_t, @@ -728,9 +758,15 @@ TEST_UNIFORM_Z (dup_m128_s32_z, svint32_t, /* ** dup_m129_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-129 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-129 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m129_s32_z, svint32_t, @@ -749,9 +785,15 @@ TEST_UNIFORM_Z (dup_m254_s32_z, svint32_t, /* ** dup_m255_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-255 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m255_s32_z, svint32_t, @@ -769,9 +811,15 @@ TEST_UNIFORM_Z (dup_m256_s32_z, svint32_t, /* ** dup_m257_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-257 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-257 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m257_s32_z, svint32_t, @@ -808,9 +856,15 @@ TEST_UNIFORM_Z (dup_m7f00_s32_z, svint32_t, /* ** dup_m7f01_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-32513 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-32513 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m7f01_s32_z, svint32_t, @@ -829,9 +883,15 @@ TEST_UNIFORM_Z (dup_m7ffe_s32_z, svint32_t, /* ** dup_m7fff_s32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-32767 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m7fff_s32_z, svint32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c index 651bb1b43f0..5189dcf590a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c @@ -603,9 +603,15 @@ TEST_UNIFORM_Z (dup_127_s64_z, svint64_t, /* ** dup_128_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #128 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #128 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_128_s64_z, svint64_t, @@ -624,9 +630,15 @@ TEST_UNIFORM_Z (dup_253_s64_z, svint64_t, /* ** dup_254_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #254 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #254 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_254_s64_z, svint64_t, @@ -635,9 +647,15 @@ TEST_UNIFORM_Z (dup_254_s64_z, svint64_t, /* ** dup_255_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #255 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_255_s64_z, svint64_t, @@ -688,9 +706,15 @@ TEST_UNIFORM_Z (dup_7ffd_s64_z, svint64_t, /* ** dup_7ffe_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #32766 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #32766 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_7ffe_s64_z, svint64_t, @@ -699,9 +723,15 @@ TEST_UNIFORM_Z (dup_7ffe_s64_z, svint64_t, /* ** dup_7fff_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #32767 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_7fff_s64_z, svint64_t, @@ -728,9 +758,15 @@ TEST_UNIFORM_Z (dup_m128_s64_z, svint64_t, /* ** dup_m129_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #-129 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #-129 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_m129_s64_z, svint64_t, @@ -749,9 +785,15 @@ TEST_UNIFORM_Z (dup_m254_s64_z, svint64_t, /* ** dup_m255_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #-255 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #-255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_m255_s64_z, svint64_t, @@ -769,9 +811,15 @@ TEST_UNIFORM_Z (dup_m256_s64_z, svint64_t, /* ** dup_m257_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #-257 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #-257 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_m257_s64_z, svint64_t, @@ -808,9 +856,15 @@ TEST_UNIFORM_Z (dup_m7f00_s64_z, svint64_t, /* ** dup_m7f01_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #-32513 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #-32513 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_m7f01_s64_z, svint64_t, @@ -829,9 +883,15 @@ TEST_UNIFORM_Z (dup_m7ffe_s64_z, svint64_t, /* ** dup_m7fff_s64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #-32767 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #-32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_m7fff_s64_z, svint64_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c index dba409d5b3b..09fecd44b88 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c @@ -611,9 +611,15 @@ TEST_UNIFORM_Z (dup_127_u16_z, svuint16_t, /* ** dup_128_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #128 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #128 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_128_u16_z, svuint16_t, @@ -632,9 +638,15 @@ TEST_UNIFORM_Z (dup_253_u16_z, svuint16_t, /* ** dup_254_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #254 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #254 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_254_u16_z, svuint16_t, @@ -643,9 +655,15 @@ TEST_UNIFORM_Z (dup_254_u16_z, svuint16_t, /* ** dup_255_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #255 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_255_u16_z, svuint16_t, @@ -663,9 +681,15 @@ TEST_UNIFORM_Z (dup_256_u16_z, svuint16_t, /* ** dup_257_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+)\.b, #1 ** sel z0\.h, p0, \2\.h, \1\.h +** | +** mov (z[0-9]+)\.b, #1 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3\.h, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_257_u16_z, svuint16_t, @@ -702,9 +726,15 @@ TEST_UNIFORM_Z (dup_7ffd_u16_z, svuint16_t, /* ** dup_7ffe_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #32766 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #32766 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_7ffe_u16_z, svuint16_t, @@ -713,9 +743,15 @@ TEST_UNIFORM_Z (dup_7ffe_u16_z, svuint16_t, /* ** dup_7fff_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #32767 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_7fff_u16_z, svuint16_t, @@ -742,9 +778,15 @@ TEST_UNIFORM_Z (dup_m128_u16_z, svuint16_t, /* ** dup_m129_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-129 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-129 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m129_u16_z, svuint16_t, @@ -763,9 +805,15 @@ TEST_UNIFORM_Z (dup_m254_u16_z, svuint16_t, /* ** dup_m255_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-255 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m255_u16_z, svuint16_t, @@ -783,9 +831,15 @@ TEST_UNIFORM_Z (dup_m256_u16_z, svuint16_t, /* ** dup_m257_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-257 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-257 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m257_u16_z, svuint16_t, @@ -794,9 +848,15 @@ TEST_UNIFORM_Z (dup_m257_u16_z, svuint16_t, /* ** dup_m258_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+)\.b, #-2 ** sel z0\.h, p0, \2\.h, \1\.h +** | +** mov (z[0-9]+)\.b, #-2 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3\.h, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m258_u16_z, svuint16_t, @@ -828,9 +888,15 @@ TEST_UNIFORM_Z (dup_m7f00_u16_z, svuint16_t, /* ** dup_m7f01_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-32513 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-32513 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m7f01_u16_z, svuint16_t, @@ -849,9 +915,15 @@ TEST_UNIFORM_Z (dup_m7ffe_u16_z, svuint16_t, /* ** dup_m7fff_u16_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.h), #-32767 ** sel z0\.h, p0, \2, \1\.h +** | +** mov (z[0-9]+\.h), #-32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.h, p0, \3, \4\.h +** ) ** ret */ TEST_UNIFORM_Z (dup_m7fff_u16_z, svuint16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c index 7d5b4626fd4..4b7da13a456 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c @@ -603,9 +603,15 @@ TEST_UNIFORM_Z (dup_127_u32_z, svuint32_t, /* ** dup_128_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #128 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #128 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_128_u32_z, svuint32_t, @@ -624,9 +630,15 @@ TEST_UNIFORM_Z (dup_253_u32_z, svuint32_t, /* ** dup_254_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #254 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #254 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_254_u32_z, svuint32_t, @@ -635,9 +647,15 @@ TEST_UNIFORM_Z (dup_254_u32_z, svuint32_t, /* ** dup_255_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #255 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_255_u32_z, svuint32_t, @@ -688,9 +706,15 @@ TEST_UNIFORM_Z (dup_7ffd_u32_z, svuint32_t, /* ** dup_7ffe_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #32766 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #32766 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_7ffe_u32_z, svuint32_t, @@ -699,9 +723,15 @@ TEST_UNIFORM_Z (dup_7ffe_u32_z, svuint32_t, /* ** dup_7fff_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #32767 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_7fff_u32_z, svuint32_t, @@ -728,9 +758,15 @@ TEST_UNIFORM_Z (dup_m128_u32_z, svuint32_t, /* ** dup_m129_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-129 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-129 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m129_u32_z, svuint32_t, @@ -749,9 +785,15 @@ TEST_UNIFORM_Z (dup_m254_u32_z, svuint32_t, /* ** dup_m255_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-255 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m255_u32_z, svuint32_t, @@ -769,9 +811,15 @@ TEST_UNIFORM_Z (dup_m256_u32_z, svuint32_t, /* ** dup_m257_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-257 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-257 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m257_u32_z, svuint32_t, @@ -808,9 +856,15 @@ TEST_UNIFORM_Z (dup_m7f00_u32_z, svuint32_t, /* ** dup_m7f01_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-32513 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-32513 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m7f01_u32_z, svuint32_t, @@ -829,9 +883,15 @@ TEST_UNIFORM_Z (dup_m7ffe_u32_z, svuint32_t, /* ** dup_m7fff_u32_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.s), #-32767 ** sel z0\.s, p0, \2, \1\.s +** | +** mov (z[0-9]+\.s), #-32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.s, p0, \3, \4\.s +** ) ** ret */ TEST_UNIFORM_Z (dup_m7fff_u32_z, svuint32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c index 0431e75bc65..4d64b40a90b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c @@ -603,9 +603,15 @@ TEST_UNIFORM_Z (dup_127_u64_z, svuint64_t, /* ** dup_128_u64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #128 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #128 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_128_u64_z, svuint64_t, @@ -624,9 +630,15 @@ TEST_UNIFORM_Z (dup_253_u64_z, svuint64_t, /* ** dup_254_u64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #254 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #254 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_254_u64_z, svuint64_t, @@ -635,9 +647,15 @@ TEST_UNIFORM_Z (dup_254_u64_z, svuint64_t, /* ** dup_255_u64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #255 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_255_u64_z, svuint64_t, @@ -688,9 +706,15 @@ TEST_UNIFORM_Z (dup_7ffd_u64_z, svuint64_t, /* ** dup_7ffe_u64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #32766 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #32766 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_7ffe_u64_z, svuint64_t, @@ -699,9 +723,15 @@ TEST_UNIFORM_Z (dup_7ffe_u64_z, svuint64_t, /* ** dup_7fff_u64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #32767 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #32767 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_7fff_u64_z, svuint64_t, @@ -728,9 +758,15 @@ TEST_UNIFORM_Z (dup_m128_u64_z, svuint64_t, /* ** dup_m129_u64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #-129 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #-129 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_m129_u64_z, svuint64_t, @@ -749,9 +785,15 @@ TEST_UNIFORM_Z (dup_m254_u64_z, svuint64_t, /* ** dup_m255_u64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #-255 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #-255 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_m255_u64_z, svuint64_t, @@ -769,9 +811,15 @@ TEST_UNIFORM_Z (dup_m256_u64_z, svuint64_t, /* ** dup_m257_u64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #-257 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #-257 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_m257_u64_z, svuint64_t, @@ -808,9 +856,15 @@ TEST_UNIFORM_Z (dup_m7f00_u64_z, svuint64_t, /* ** dup_m7f01_u64_z: +** ( ** mov (z[0-9]+)\.b, #0 ** mov (z[0-9]+\.d), #-32513 ** sel z0\.d, p0, \2, \1\.d +** | +** mov (z[0-9]+\.d), #-32513 +** mov (z[0-9]+)\.b, #0 +** sel z0\.d, p0, \3, \4\.d +** ) ** ret */ TEST_UNIFORM_Z (dup_m7f01_u64_z, svuint64_t, @@ -829,9 +883,15 @@ TEST_UNIFORM_Z (dup_m7ffe_u64_z, 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[8.43.85.97]) by mx.google.com with ESMTPS id 26-20020a170906311a00b0096578f876b7si1303149ejx.867.2023.05.08.23.52.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 23:52:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="xD3B5/Il"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2ABB93854175 for ; Tue, 9 May 2023 06:50:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2ABB93854175 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683615055; bh=SDtUo4vJoDSh7hV1BciEs/pEMmVUc5SrOdhK3d+2oAE=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=xD3B5/IlHaecfJj7Aa+kNNujGuD2f7hxfqb/BwI4XmDSMUEe5x0Zhp2Y92ZRfeqZj /y6VbR/rRY6By5v1HGPz5M1ZDfxygBXU4nHdRSXV8IlKTlVsu8GE6/qOfu/AOLaaYu 2Zd/2TD5Ab3k69GDTTwDLoDhhx6GsjDyeadIXo+k= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 3E5553858404 for ; Tue, 9 May 2023 06:49:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3E5553858404 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5E4D41063; Mon, 8 May 2023 23:49:55 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 550003F5A1; Mon, 8 May 2023 23:49:10 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 4/6] aarch64: Relax predicate register matches Date: Tue, 9 May 2023 07:48:29 +0100 Message-Id: <20230509064831.1651327-5-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230509064831.1651327-1-richard.sandiford@arm.com> References: <20230509064831.1651327-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-30.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765398412967276637?= X-GMAIL-MSGID: =?utf-8?q?1765398412967276637?= Most governing predicate operands require p0-p7, but some instructions also allow p8-p15. Non-gp uses of predicates often also allow all of p0-p15. This patch fixes up cases where we required p0-p7 unnecessarily. In some cases we match the definition (typically a comparison, PFALSE or PTRUE), sometimes we match the use (like a logic instruction, MOV or SEL), and sometimes we match both. gcc/testsuite/ * g++.target/aarch64/sve/vcond_1.C: Allow any predicate register for the temporary results, not just p0-p7. * gcc.target/aarch64/sve/acle/asm/dupq_b8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dupq_b16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dupq_b32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dupq_b64.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_5.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_6.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_7.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_9.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilele_10.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilelt_1.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilelt_2.c: Likewise. * gcc.target/aarch64/sve/acle/general/whilelt_3.c: Likewise. * gcc.target/aarch64/sve/pcs/varargs_1.c: Likewise. * gcc.target/aarch64/sve/peel_ind_2.c: Likewise. * gcc.target/aarch64/sve/mask_gather_load_6.c: Likewise. * gcc.target/aarch64/sve/vcond_2.c: Likewise. * gcc.target/aarch64/sve/vcond_3.c: Likewise. * gcc.target/aarch64/sve/vcond_7.c: Likewise. * gcc.target/aarch64/sve/vcond_18.c: Likewise. * gcc.target/aarch64/sve/vcond_19.c: Likewise. * gcc.target/aarch64/sve/vcond_20.c: Likewise. --- .../g++.target/aarch64/sve/vcond_1.C | 258 +++++++++--------- .../aarch64/sve/acle/asm/dupq_b16.c | 86 +++--- .../aarch64/sve/acle/asm/dupq_b32.c | 48 ++-- .../aarch64/sve/acle/asm/dupq_b64.c | 16 +- .../gcc.target/aarch64/sve/acle/asm/dupq_b8.c | 136 ++++----- .../aarch64/sve/acle/general/whilele_10.c | 2 +- .../aarch64/sve/acle/general/whilele_5.c | 10 +- .../aarch64/sve/acle/general/whilele_6.c | 2 +- .../aarch64/sve/acle/general/whilele_7.c | 6 +- .../aarch64/sve/acle/general/whilele_9.c | 6 +- .../aarch64/sve/acle/general/whilelt_1.c | 10 +- .../aarch64/sve/acle/general/whilelt_2.c | 2 +- .../aarch64/sve/acle/general/whilelt_3.c | 6 +- .../aarch64/sve/mask_gather_load_6.c | 4 +- .../gcc.target/aarch64/sve/pcs/varargs_1.c | 8 +- .../gcc.target/aarch64/sve/peel_ind_2.c | 2 +- .../gcc.target/aarch64/sve/vcond_18.c | 14 +- .../gcc.target/aarch64/sve/vcond_19.c | 34 +-- .../gcc.target/aarch64/sve/vcond_2.c | 248 ++++++++--------- .../gcc.target/aarch64/sve/vcond_20.c | 34 +-- .../gcc.target/aarch64/sve/vcond_3.c | 26 +- .../gcc.target/aarch64/sve/vcond_7.c | 198 +++++++------- 22 files changed, 578 insertions(+), 578 deletions(-) diff --git a/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C b/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C index da52c4c1359..3e7de9b455a 100644 --- a/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C +++ b/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C @@ -112,132 +112,132 @@ TYPE vcond_imm_##TYPE##_##SUFFIX (TYPE x, TYPE y, TYPE a) \ TEST_VAR_ALL (DEF_VCOND_VAR) TEST_IMM_ALL (DEF_VCOND_IMM) -/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.b, p[0-7], z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - - - -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #14\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #14\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #14\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #14\n} } } */ - -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #14\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #14\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #14\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #14\n} } } */ - -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-15\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-15\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-15\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-15\n} } } */ - -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-15\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-15\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-15\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-15\n} } } */ - -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - - - -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */ - -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */ - - -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ - -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #30\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #30\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #30\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #30\n} } } */ - -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #30\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #30\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #30\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #30\n} } } */ - -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ +/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.b, p[0-9]+, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmphs\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmphs\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmphs\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmphs\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + + + +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmple\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #14\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #14\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #14\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #14\n} } } */ + +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #14\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #14\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #14\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #14\n} } } */ + +/* { dg-final { scan-assembler {\tcmple\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-15\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-15\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-15\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-15\n} } } */ + +/* { dg-final { scan-assembler {\tcmplt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + +/* { dg-final { scan-assembler {\tcmplt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-15\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-15\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-15\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-15\n} } } */ + +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + + + +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */ + +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */ + + +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ + +/* { dg-final { scan-assembler {\tcmpls\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #30\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #30\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #30\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #30\n} } } */ + +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #30\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #30\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #30\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #30\n} } } */ + +/* { dg-final { scan-assembler {\tcmpls\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b16.c index ecbacd7e98b..4d1185da82a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b16.c @@ -23,12 +23,12 @@ TEST_UNIFORM_P (dupq_11_b16, /* ** dupq_22_b16: ** ( -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.d, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.h, \1\.h, \2\.h ** | -** ptrue (p[0-7])\.d, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.d, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.h, \4\.h, \3\.h ** ) ** ret @@ -39,7 +39,7 @@ TEST_UNIFORM_P (dupq_22_b16, /* ** dupq_33_b16: -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.h, \1\.h, \1\.h ** ret */ @@ -50,12 +50,12 @@ TEST_UNIFORM_P (dupq_33_b16, /* ** dupq_44_b16: ** ( -** ptrue (p[0-7])\.d, all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.d, all +** ptrue (p[0-9]+)\.s, all ** not p0\.b, \2/z, \1\.b ** | -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.d, all ** not p0\.b, \3/z, \4\.b ** ) ** ret @@ -86,12 +86,12 @@ TEST_UNIFORM_P (dupq_66_b16, /* ** dupq_77_b16: ** ( -** ptrue (p[0-7])\.d, all -** ptrue (p[0-7])\.[hs], all +** ptrue (p[0-9]+)\.d, all +** ptrue (p[0-9]+)\.[hs], all ** trn1 p0\.h, \2\.h, \1\.h ** | -** ptrue (p[0-7])\.[hs], all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.[hs], all +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.h, \3\.h, \4\.h ** ) ** ret @@ -104,10 +104,10 @@ TEST_UNIFORM_P (dupq_77_b16, ** dupq_88_b16: ** ( ** mov (z[0-9]+)\.d, #71776119061217280 -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.b, all ** cmpne p0\.b, \2/z, \1\.b, #0 ** | -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.b, all ** mov (z[0-9]+)\.d, #71776119061217280 ** cmpne p0\.b, \3/z, \4\.b, #0 ** ) @@ -130,12 +130,12 @@ TEST_UNIFORM_P (dupq_99_b16, /* ** dupq_aa_b16: ** ( -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.h, all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.h, all ** not p0\.b, \2/z, \1\.b ** | -** ptrue (p[0-7])\.h, all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.h, all +** ptrue (p[0-9]+)\.s, all ** not p0\.b, \3/z, \4\.b ** ) ** ret @@ -147,12 +147,12 @@ TEST_UNIFORM_P (dupq_aa_b16, /* ** dupq_bb_b16: ** ( -** ptrue (p[0-7])\.d, all -** ptrue (p[0-7])\.[hs], all +** ptrue (p[0-9]+)\.d, all +** ptrue (p[0-9]+)\.[hs], all ** trn1 p0\.h, \1\.h, \2\.h ** | -** ptrue (p[0-7])\.[hs], all -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.[hs], all +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.h, \4\.h, \3\.h ** ) ** ret @@ -164,12 +164,12 @@ TEST_UNIFORM_P (dupq_bb_b16, /* ** dupq_cc_b16: ** ( -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.h, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.h, all ** trn1 p0\.s, \1\.s, \2\.s ** | -** ptrue (p[0-7])\.h, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.h, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.s, \4\.s, \3\.s ** ) ** ret @@ -181,12 +181,12 @@ TEST_UNIFORM_P (dupq_cc_b16, /* ** dupq_dd_b16: ** ( -** ptrue (p[0-7])\.[sd], all -** ptrue (p[0-7])\.h, all +** ptrue (p[0-9]+)\.[sd], all +** ptrue (p[0-9]+)\.h, all ** trn1 p0\.s, \1\.s, \2\.s ** | -** ptrue (p[0-7])\.h, all -** ptrue (p[0-7])\.[sd], all +** ptrue (p[0-9]+)\.h, all +** ptrue (p[0-9]+)\.[sd], all ** trn1 p0\.s, \4\.s, \3\.s ** ) ** ret @@ -198,12 +198,12 @@ TEST_UNIFORM_P (dupq_dd_b16, /* ** dupq_ee_b16: ** ( -** ptrue (p[0-7])\.d, all -** ptrue (p[0-7])\.h, all +** ptrue (p[0-9]+)\.d, all +** ptrue (p[0-9]+)\.h, all ** not p0\.b, \2/z, \1\.b ** | -** ptrue (p[0-7])\.h, all -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.h, all +** ptrue (p[0-9]+)\.d, all ** not p0\.b, \3/z, \4\.b ** ) ** ret @@ -224,12 +224,12 @@ TEST_UNIFORM_P (dupq_ff_b16, /* ** dupq_01_b16: ** ( -** ptrue (p[0-7])\.d, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.d, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \1\.d, \2\.d ** | -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.d, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.d, \4\.d, \3\.d ** ) ** ret @@ -251,12 +251,12 @@ TEST_UNIFORM_P (dupq_03_b16, /* ** dupq_0f_b16: ** ( -** ptrue (p[0-7])\.h, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.h, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \1\.d, \2\.d ** | -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.h, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.h, all ** trn1 p0\.d, \4\.d, \3\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b32.c index 39719a76d3c..11038c84046 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b32.c @@ -14,12 +14,12 @@ TEST_UNIFORM_P (dupq_0_b32, /* ** dupq_1_b32: ** ( -** ptrue (p[0-7])\.d, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.d, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \1\.d, \2\.d ** | -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.d, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.d, \4\.d, \3\.d ** ) ** ret @@ -31,12 +31,12 @@ TEST_UNIFORM_P (dupq_1_b32, /* ** dupq_3_b32: ** ( -** ptrue (p[0-7])\.s, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.s, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \1\.d, \2\.d ** | -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.s, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.s, all ** trn1 p0\.d, \4\.d, \3\.d ** ) ** ret @@ -48,12 +48,12 @@ TEST_UNIFORM_P (dupq_3_b32, /* ** dupq_4_b32: ** ( -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.d, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.d, \1\.d, \2\.d ** | -** ptrue (p[0-7])\.d, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.d, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \4\.d, \3\.d ** ) ** ret @@ -74,12 +74,12 @@ TEST_UNIFORM_P (dupq_5_b32, /* ** dupq_7_b32: ** ( -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.d, \1\.d, \2\.d ** | -** ptrue (p[0-7])\.d, all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.d, all +** ptrue (p[0-9]+)\.s, all ** trn1 p0\.d, \4\.d, \3\.d ** ) ** ret @@ -91,12 +91,12 @@ TEST_UNIFORM_P (dupq_7_b32, /* ** dupq_a_b32: ** ( -** ptrue (p[0-7])\.d, all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.d, all +** ptrue (p[0-9]+)\.s, all ** not p0\.b, \2/z, \1\.b ** | -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.d, all ** not p0\.b, \3/z, \4\.b ** ) ** ret @@ -108,12 +108,12 @@ TEST_UNIFORM_P (dupq_a_b32, /* ** dupq_e_b32: ** ( -** ptrue (p[0-7])\.d, all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.d, all +** ptrue (p[0-9]+)\.s, all ** trn1 p0\.d, \1\.d, \2\.d ** | -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.d, \4\.d, \3\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b64.c index 820ace43189..698f3678763 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b64.c @@ -14,12 +14,12 @@ TEST_UNIFORM_P (dupq_0_b64, /* ** dupq_1_b64: ** ( -** ptrue (p[0-7])\.d, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.d, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \1\.d, \2\.d ** | -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.d, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.d, \4\.d, \3\.d ** ) ** ret @@ -31,12 +31,12 @@ TEST_UNIFORM_P (dupq_1_b64, /* ** dupq_2_b64: ** ( -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.d, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.d, \1\.d, \2\.d ** | -** ptrue (p[0-7])\.d, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.d, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \4\.d, \3\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b8.c index 4762f950bad..578b833b360 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b8.c @@ -27,12 +27,12 @@ TEST_UNIFORM_P (dupq_1111_b8, /* ** dupq_2222_b8: ** ( -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.s, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.s, all ** trn1 p0\.b, \1\.b, \2\.b ** | -** ptrue (p[0-7])\.s, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.s, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.b, \4\.b, \3\.b ** ) ** ret @@ -45,7 +45,7 @@ TEST_UNIFORM_P (dupq_2222_b8, /* ** dupq_3333_b8: -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.s, all ** trn1 p0\.b, \1\.b, \1\.b ** ret */ @@ -58,12 +58,12 @@ TEST_UNIFORM_P (dupq_3333_b8, /* ** dupq_4444_b8: ** ( -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.h, all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.h, all ** not p0\.b, \2/z, \1\.b ** | -** ptrue (p[0-7])\.h, all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.h, all +** ptrue (p[0-9]+)\.s, all ** not p0\.b, \3/z, \4\.b ** ) ** ret @@ -89,10 +89,10 @@ TEST_UNIFORM_P (dupq_5555_b8, ** dupq_6666_b8: ** ( ** mov (z[0-9]+)\.s, #16776960 -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.b, all ** cmpne p0\.b, \2/z, \1\.b, #0 ** | -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.b, all ** mov (z[0-9]+)\.s, #16776960 ** cmpne p0\.b, \3/z, \4\.b, #0 ** ) @@ -107,12 +107,12 @@ TEST_UNIFORM_P (dupq_6666_b8, /* ** dupq_7777_b8: ** ( -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.[bh], all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.[bh], all ** trn1 p0\.b, \2\.b, \1\.b ** | -** ptrue (p[0-7])\.[bh], all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.[bh], all +** ptrue (p[0-9]+)\.s, all ** trn1 p0\.b, \3\.b, \4\.b ** ) ** ret @@ -127,10 +127,10 @@ TEST_UNIFORM_P (dupq_7777_b8, ** dupq_8888_b8: ** ( ** mov (z[0-9]+)\.s, #-16777216 -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.b, all ** cmpne p0\.b, \2/z, \1\.b, #0 ** | -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.b, all ** mov (z[0-9]+)\.s, #-16777216 ** cmpne p0\.b, \3/z, \4\.b, #0 ** ) @@ -146,10 +146,10 @@ TEST_UNIFORM_P (dupq_8888_b8, ** dupq_9999_b8: ** ( ** mov (z[0-9]+)\.s, #-16776961 -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.b, all ** cmpne p0\.b, \2/z, \1\.b, #0 ** | -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.b, all ** mov (z[0-9]+)\.s, #-16776961 ** cmpne p0\.b, \3/z, \4\.b, #0 ** ) @@ -164,12 +164,12 @@ TEST_UNIFORM_P (dupq_9999_b8, /* ** dupq_aaaa_b8: ** ( -** ptrue (p[0-7])\.h, all -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.h, all +** ptrue (p[0-9]+)\.b, all ** not p0\.b, \2/z, \1\.b ** | -** ptrue (p[0-7])\.b, all -** ptrue (p[0-7])\.h, all +** ptrue (p[0-9]+)\.b, all +** ptrue (p[0-9]+)\.h, all ** not p0\.b, \3/z, \4\.b ** ) ** ret @@ -183,12 +183,12 @@ TEST_UNIFORM_P (dupq_aaaa_b8, /* ** dupq_bbbb_b8: ** ( -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.[bh], all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.[bh], all ** trn1 p0\.b, \1\.b, \2\.b ** | -** ptrue (p[0-7])\.[bh], all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.[bh], all +** ptrue (p[0-9]+)\.s, all ** trn1 p0\.b, \4\.b, \3\.b ** ) ** ret @@ -202,12 +202,12 @@ TEST_UNIFORM_P (dupq_bbbb_b8, /* ** dupq_cccc_b8: ** ( -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.b, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.b, all ** trn1 p0\.h, \1\.h, \2\.h ** | -** ptrue (p[0-7])\.b, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.b, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.h, \4\.h, \3\.h ** ) ** ret @@ -221,12 +221,12 @@ TEST_UNIFORM_P (dupq_cccc_b8, /* ** dupq_dddd_b8: ** ( -** ptrue (p[0-7])\.[hs], all -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.[hs], all +** ptrue (p[0-9]+)\.b, all ** trn1 p0\.h, \1\.h, \2\.h ** | -** ptrue (p[0-7])\.b, all -** ptrue (p[0-7])\.[hs], all +** ptrue (p[0-9]+)\.b, all +** ptrue (p[0-9]+)\.[hs], all ** trn1 p0\.h, \4\.h, \3\.h ** ) ** ret @@ -240,12 +240,12 @@ TEST_UNIFORM_P (dupq_dddd_b8, /* ** dupq_eeee_b8: ** ( -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.b, all ** not p0\.b, \2/z, \1\.b ** | -** ptrue (p[0-7])\.b, all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.b, all +** ptrue (p[0-9]+)\.s, all ** not p0\.b, \3/z, \4\.b ** ) ** ret @@ -270,12 +270,12 @@ TEST_UNIFORM_P (dupq_ffff_b8, /* ** dupq_5f5f_b8: ** ( -** ptrue (p[0-7])\.h, all -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.h, all +** ptrue (p[0-9]+)\.b, all ** trn1 p0\.s, \2\.s, \1\.s ** | -** ptrue (p[0-7])\.b, all -** ptrue (p[0-7])\.h, all +** ptrue (p[0-9]+)\.b, all +** ptrue (p[0-9]+)\.h, all ** trn1 p0\.s, \3\.s, \4\.s ** ) ** ret @@ -289,12 +289,12 @@ TEST_UNIFORM_P (dupq_5f5f_b8, /* ** dupq_1f1f_b8: ** ( -** ptrue (p[0-7])\.[sd], all -** ptrue (p[0-7])\.b, all +** ptrue (p[0-9]+)\.[sd], all +** ptrue (p[0-9]+)\.b, all ** trn1 p0\.s, \2\.s, \1\.s ** | -** ptrue (p[0-7])\.b, all -** ptrue (p[0-7])\.[sd], all +** ptrue (p[0-9]+)\.b, all +** ptrue (p[0-9]+)\.[sd], all ** trn1 p0\.s, \3\.s, \4\.s ** ) ** ret @@ -308,12 +308,12 @@ TEST_UNIFORM_P (dupq_1f1f_b8, /* ** dupq_1515_b8: ** ( -** ptrue (p[0-7])\.d, all -** ptrue (p[0-7])\.[hs], all +** ptrue (p[0-9]+)\.d, all +** ptrue (p[0-9]+)\.[hs], all ** trn1 p0\.h, \2\.h, \1\.h ** | -** ptrue (p[0-7])\.[hs], all -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.[hs], all +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.h, \3\.h, \4\.h ** ) ** ret @@ -326,7 +326,7 @@ TEST_UNIFORM_P (dupq_1515_b8, /* ** dupq_0505_b8: -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.h, \1\.h, \1\.h ** ret */ @@ -339,12 +339,12 @@ TEST_UNIFORM_P (dupq_0505_b8, /* ** dupq_00ff_b8: ** ( -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.b, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.b, all ** trn1 p0\.d, \2\.d, \1\.d ** | -** ptrue (p[0-7])\.b, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.b, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \3\.d, \4\.d ** ) ** ret @@ -358,12 +358,12 @@ TEST_UNIFORM_P (dupq_00ff_b8, /* ** dupq_0055_b8: ** ( -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.h, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.h, all ** trn1 p0\.d, \2\.d, \1\.d ** | -** ptrue (p[0-7])\.h, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.h, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \3\.d, \4\.d ** ) ** ret @@ -377,12 +377,12 @@ TEST_UNIFORM_P (dupq_0055_b8, /* ** dupq_0011_b8: ** ( -** pfalse (p[0-7])\.b -** ptrue (p[0-7])\.s, all +** pfalse (p[0-9]+)\.b +** ptrue (p[0-9]+)\.s, all ** trn1 p0\.d, \2\.d, \1\.d ** | -** ptrue (p[0-7])\.s, all -** pfalse (p[0-7])\.b +** ptrue (p[0-9]+)\.s, all +** pfalse (p[0-9]+)\.b ** trn1 p0\.d, \3\.d, \4\.d ** ) ** ret @@ -396,12 +396,12 @@ TEST_UNIFORM_P (dupq_0011_b8, /* ** dupq_0111_b8: ** ( -** ptrue (p[0-7])\.d, all -** ptrue (p[0-7])\.s, all +** ptrue (p[0-9]+)\.d, all +** ptrue (p[0-9]+)\.s, all ** trn1 p0\.d, \2\.d, \1\.d ** | -** ptrue (p[0-7])\.s, all -** ptrue (p[0-7])\.d, all +** ptrue (p[0-9]+)\.s, all +** ptrue (p[0-9]+)\.d, all ** trn1 p0\.d, \3\.d, \4\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_10.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_10.c index ca339c41c6e..abe9a11e595 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_10.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_10.c @@ -25,4 +25,4 @@ test3 (svbool_t *ptr) *ptr = svwhilele_b8_u64 (0x8000000000000001ULL, 0x7ffffffffffffffeULL); } -/* { dg-final { scan-assembler-times {\tpfalse\tp[0-7]\.b\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tpfalse\tp[0-9]+\.b\n} 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_5.c index ada958b29c1..7c73aa5926b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_5.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_5.c @@ -12,7 +12,7 @@ test1 (svbool_t *ptr) *ptr = svwhilele_b32_s32 (-8, -8); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.[bhsd], vl1\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.[bhsd], vl1\n} } } */ void test2 (svbool_t *ptr) @@ -20,7 +20,7 @@ test2 (svbool_t *ptr) *ptr = svwhilele_b16_s64 (-1, 1); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h, vl3\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.h, vl3\n} } } */ void test3 (svbool_t *ptr) @@ -28,7 +28,7 @@ test3 (svbool_t *ptr) *ptr = svwhilele_b16_s32 (0x7ffffffb, 0x7fffffff); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h, vl5\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.h, vl5\n} } } */ void test4 (svbool_t *ptr) @@ -36,7 +36,7 @@ test4 (svbool_t *ptr) *ptr = svwhilele_b8_s64 (svcntb (), svcntb () + 6); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.b, vl7\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.b, vl7\n} } } */ void test5 (svbool_t *ptr) @@ -44,4 +44,4 @@ test5 (svbool_t *ptr) *ptr = svwhilele_b64_s64 (0, 1); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.d, vl2\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.d, vl2\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_6.c index 00d92ba8a47..fd2420b523e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_6.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_6.c @@ -37,4 +37,4 @@ test5 (svbool_t *ptr) *ptr = svwhilele_b8_s64 (svcntb (), svcntw ()); } -/* { dg-final { scan-assembler-times {\tpfalse\tp[0-7]\.b\n} 5 } } */ +/* { dg-final { scan-assembler-times {\tpfalse\tp[0-9]+\.b\n} 5 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_7.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_7.c index 92488f5972f..1b58f562176 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_7.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_7.c @@ -12,7 +12,7 @@ test1 (svbool_t *ptr) *ptr = svwhilele_b8_s32 (-svcnth (), svcnth () - 1); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.b, all\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.b, all\n} } } */ void test2 (svbool_t *ptr) @@ -20,7 +20,7 @@ test2 (svbool_t *ptr) *ptr = svwhilele_b16_s64 (1, svcntw () * 2); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h, all\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.h, all\n} } } */ void test3 (svbool_t *ptr) @@ -28,4 +28,4 @@ test3 (svbool_t *ptr) *ptr = svwhilele_b32_s32 (svcntd (), svcntw () + svcntd () - 1); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.s, all\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.s, all\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_9.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_9.c index e7f81a86f31..27b77c69409 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_9.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilele_9.c @@ -12,7 +12,7 @@ test1 (svbool_t *ptr) *ptr = svwhilele_b32_u32 (1, 3); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.s, vl3\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.s, vl3\n} } } */ void test2 (svbool_t *ptr) @@ -20,7 +20,7 @@ test2 (svbool_t *ptr) *ptr = svwhilele_b16_u64 (svcntd (), svcntd () + 5); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h, vl6\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.h, vl6\n} } } */ void test3 (svbool_t *ptr) @@ -28,4 +28,4 @@ test3 (svbool_t *ptr) *ptr = svwhilele_b8_u32 (0x7ffffffb, 0x80000002); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.b, vl8\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.b, vl8\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_1.c index 5c8f97e2f26..3391696e20f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_1.c @@ -12,7 +12,7 @@ test1 (svbool_t *ptr) *ptr = svwhilelt_b32_s32 (-8, -7); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.[bhsd], vl1\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.[bhsd], vl1\n} } } */ void test2 (svbool_t *ptr) @@ -20,7 +20,7 @@ test2 (svbool_t *ptr) *ptr = svwhilelt_b16_s64 (-1, 2); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h, vl3\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.h, vl3\n} } } */ void test3 (svbool_t *ptr) @@ -28,7 +28,7 @@ test3 (svbool_t *ptr) *ptr = svwhilelt_b16_s32 (0x7ffffffa, 0x7fffffff); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h, vl5\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.h, vl5\n} } } */ void test4 (svbool_t *ptr) @@ -36,7 +36,7 @@ test4 (svbool_t *ptr) *ptr = svwhilelt_b8_s64 (svcntb (), svcntb () + 7); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.b, vl7\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.b, vl7\n} } } */ void test5 (svbool_t *ptr) @@ -44,4 +44,4 @@ test5 (svbool_t *ptr) *ptr = svwhilelt_b64_s64 (0, 2); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.d, vl2\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.d, vl2\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_2.c index 2be3a5b0c3e..90819221369 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_2.c @@ -37,4 +37,4 @@ test5 (svbool_t *ptr) *ptr = svwhilelt_b8_s64 (svcntb (), svcntw ()); } -/* { dg-final { scan-assembler-times {\tpfalse\tp[0-7]\.b\n} 5 } } */ +/* { dg-final { scan-assembler-times {\tpfalse\tp[0-9]+\.b\n} 5 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_3.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_3.c index 650b2652fec..938dbbcd860 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/whilelt_3.c @@ -12,7 +12,7 @@ test1 (svbool_t *ptr) *ptr = svwhilelt_b8_s32 (-svcnth (), svcnth ()); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.b, all\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.b, all\n} } } */ void test2 (svbool_t *ptr) @@ -20,7 +20,7 @@ test2 (svbool_t *ptr) *ptr = svwhilelt_b16_s64 (0, svcntw () * 2); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h, all\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.h, all\n} } } */ void test3 (svbool_t *ptr) @@ -28,4 +28,4 @@ test3 (svbool_t *ptr) *ptr = svwhilelt_b32_s32 (svcntd (), svcntw () + svcntd ()); } -/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.s, all\n} } } */ +/* { dg-final { scan-assembler {\tptrue\tp[0-9]+\.s, all\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mask_gather_load_6.c b/gcc/testsuite/gcc.target/aarch64/sve/mask_gather_load_6.c index a13516aad6e..a735e610756 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/mask_gather_load_6.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/mask_gather_load_6.c @@ -30,8 +30,8 @@ TEST_ALL (TEST_LOOP) /* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x[0-9]+, x[0-9]+, lsl 3\]\n} 72 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 24 } } */ -/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 12 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 24 } } */ +/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 12 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, x[0-9]+, lsl 2\]\n} 36 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+\.s, sxtw 2\]\n} 9 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+\.s, uxtw 2\]\n} 9 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_1.c index 72960fd4ef2..721e1060ff3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_1.c @@ -29,7 +29,7 @@ callee_0 (int64_t *ptr, ...) /* ** caller_0: ** ... -** ptrue (p[0-7])\.d, vl7 +** ptrue (p[0-9]+)\.d, vl7 ** ... ** str \1, \[x1\] ** ... @@ -66,7 +66,7 @@ callee_1 (int64_t *ptr, ...) /* ** caller_1: ** ... -** ptrue (p[0-7])\.d, vl7 +** ptrue (p[0-9]+)\.d, vl7 ** ... ** str \1, \[x2\] ** ... @@ -108,7 +108,7 @@ callee_7 (int64_t *ptr, ...) /* ** caller_7: ** ... -** ptrue (p[0-7])\.d, vl7 +** ptrue (p[0-9]+)\.d, vl7 ** ... ** str \1, \[x7\] ** ... @@ -155,7 +155,7 @@ callee_8 (int64_t *ptr, ...) /* ** caller_8: ** ... -** ptrue (p[0-7])\.d, vl7 +** ptrue (p[0-9]+)\.d, vl7 ** ... ** str \1, \[(x[0-9]+)\] ** ... diff --git a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c index 5fce02102f0..985cd0c6d77 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c @@ -20,4 +20,4 @@ foo (void) /* { dg-final { scan-assembler {\t(adrp|adr)\tx[0-9]+, (x|\.LANCHOR0)\n} } } */ /* We should unroll the loop three times. */ /* { dg-final { scan-assembler-times "\tst1w\t" 3 } } */ -/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.s, vl7\n.*\teor\tp[0-7]\.b, (p[0-7])/z, (\1\.b, \2\.b|\2\.b, \1\.b)\n} } } */ +/* { dg-final { scan-assembler {\tptrue\t(p[0-9]+)\.s, vl7\n.*\teor\tp[0-9]+\.b, (p[0-9]+)/z, (\1\.b, \2\.b|\2\.b, \1\.b)\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c index a2590b9ee2b..bd83e4c377d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c @@ -25,20 +25,20 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/z, #16384\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/z, #15616\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/z, #-15360\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/z, #-16128\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/z, #16384\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/z, #15616\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/z, #-15360\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/z, #-16128\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ /* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #2\.0(?:e[+]0)?\n} } } */ /* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #1\.25(?:e[+]0)?\n} } } */ /* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #-4\.0(?:e[+]0)?\n} } } */ /* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.s), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #-2\.5(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ /* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #2\.0(?:e[+]0)?\n} } } */ /* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #1\.25(?:e[+]0)?\n} } } */ /* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #-4\.0(?:e[+]0)?\n} } } */ /* { dg-final { scan-assembler {\tmovprfx\t(z[0-9]+\.d), (p[0-7])/z, \1\n\tfmov\t\1, \2/m, #-2\.5(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_19.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_19.c index 2347b7f2853..1f50c88bfb3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_19.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_19.c @@ -25,22 +25,22 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/m, #16384\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/m, #15616\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/m, #-15360\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/m, #-16128\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ - -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-7]/m, #2\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-7]/m, #1\.25(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-7]/m, #-4\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-7]/m, #-2\.5(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ - -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-7]/m, #2\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-7]/m, #1\.25(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-7]/m, #-4\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-7]/m, #-2\.5(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/m, #16384\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/m, #15616\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/m, #-15360\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/m, #-16128\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-9]+/m, #2\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-9]+/m, #1\.25(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-9]+/m, #-4\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-9]+/m, #-2\.5(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-9]+/m, #2\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-9]+/m, #1\.25(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-9]+/m, #-4\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-9]+/m, #-2\.5(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ /* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_2.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_2.c index 53baf86b1c0..b34a6c3da89 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_2.c @@ -145,10 +145,10 @@ TEST_VAR_ALL (DEF_VCOND_VAR) TEST_IMM_ALL (DEF_VCOND_IMM) -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.b, p[0-7], z[0-9]+\.b, z[0-9]+\.b\n} 66 } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 132 } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s, z[0-9]+\.s\n} 132 } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d, z[0-9]+\.d\n} 132 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.b, p[0-9]+, z[0-9]+\.b, z[0-9]+\.b\n} 66 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} 132 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} 132 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d, z[0-9]+\.d\n} 132 } } */ /* There are two signed ordered register comparisons for .b, one for a variable comparison and one for one of the two out-of-range constant @@ -157,162 +157,162 @@ TEST_IMM_ALL (DEF_VCOND_IMM) The same pattern appears twice for .h, .s and .d, once for integer data and once for floating-point data. */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ /* Out-of-range >= is converted to in-range >. */ -/* { dg-final { scan-assembler-times {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmphs\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphs\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmphs\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmphs\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ /* Out-of-range < is converted to in-range <=. */ -/* { dg-final { scan-assembler-times {\tcmplo\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmplo\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmplo\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmplo\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmplo\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmplo\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmplo\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmplo\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ /* 6 for .b: {signed, unsigned\n} x {variable, too high, too low}. */ /* 12 for .h,.s and .d: the above 6 repeated for integer and floating-point data. */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 6 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 12 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 12 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 12 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 12 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 12 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 12 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 6 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 12 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 12 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 12 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 12 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 12 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 12 } } */ /* Also used for >= 16. */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #15\n} 4 } } */ /* gcc converts "a < 15" into "a <= 14". */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #14\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #14\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #14\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #14\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #14\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #14\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #14\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #14\n} 2 } } */ /* gcc converts "a >= 15" into "a > 14". */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #14\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #14\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #14\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #14\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #14\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #14\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #14\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #14\n} 2 } } */ /* Also used for < 16. */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #15\n} 4 } } */ /* Appears once for each signedness. */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #15\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #15\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #15\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} 4 } } */ /* gcc converts "a > -16" into "a >= -15". */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-15\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-15\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-15\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-15\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-15\n} 2 } } */ /* Also used for <= -17. */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} 4 } } */ /* Also used for > -17. */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} 4 } } */ /* gcc converts "a <= -16" into "a < -15". */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-15\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-15\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-15\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #-15\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #-15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #-15\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #-15\n} 2 } } */ /* gcc converts "a > 0" into "a != 0". */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #0\n} 2 } } */ /* gcc converts "a <= 0" into "a == 0". */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #0\n} 2 } } */ /* Also used for >= 128. */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #127\n} 2 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #127\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #127\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #127\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #127\n} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #127\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #127\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #127\n} 4 } } */ /* gcc converts "a < 127" into "a <= 126". */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #126\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #126\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #126\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #126\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #126\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #126\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #126\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #126\n} 2 } } */ /* gcc converts "a >= 127" into "a > 126". */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #126\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #126\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #126\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #126\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #126\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #126\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #126\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #126\n} 2 } } */ /* Also used for < 128. */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #127\n} 2 { xfail *-*-* } } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #127\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #127\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #127\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #127\n} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #127\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #127\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #127\n} 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_20.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_20.c index bf2af1c62f8..c3618ca3c14 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_20.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_20.c @@ -25,22 +25,22 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/m, #16384\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/m, #15616\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/m, #-15360\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-7]/m, #-16128\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ - -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-7]/m, #2\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-7]/m, #1\.25(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-7]/m, #-4\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-7]/m, #-2\.5(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ - -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-7]/m, #2\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-7]/m, #1\.25(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-7]/m, #-4\.0(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-7]/m, #-2\.5(?:e[+]0)?\n} } } */ -/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/m, #16384\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/m, #15616\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/m, #-15360\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.h, p[0-9]+/m, #-16128\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.h, p[0-9]+, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-9]+/m, #2\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-9]+/m, #1\.25(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-9]+/m, #-4\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.s), p[0-9]+/m, #-2\.5(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.s, p[0-9]+, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-9]+/m, #2\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-9]+/m, #1\.25(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-9]+/m, #-4\.0(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.d), p[0-9]+/m, #-2\.5(?:e[+]0)?\n} } } */ +/* { dg-final { scan-assembler-times {\tsel\tz[0-9]+\.d, p[0-9]+, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */ /* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 12 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_3.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_3.c index 7dee996232b..354f4a89278 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_3.c @@ -52,17 +52,17 @@ TEST_TYPE16 (int16_t) TEST_TYPE32 (int32_t) TEST_TYPE32 (int64_t) -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-7]/z, #-128\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-7]/z, #-127\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-7]/z, #2\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-7]/z, #127\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-9]+/z, #-128\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-9]+/z, #-127\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-9]+/z, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.b, p[0-9]+/z, #127\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-32768\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-32512\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-256\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-128\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #-127\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #2\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #127\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #256\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-7]/z, #32512\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-9]+/z, #-32768\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-9]+/z, #-32512\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-9]+/z, #-256\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-9]+/z, #-128\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-9]+/z, #-127\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-9]+/z, #2\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-9]+/z, #127\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-9]+/z, #256\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.[hsd], p[0-9]+/z, #32512\n} 3 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/vcond_7.c b/gcc/testsuite/gcc.target/aarch64/sve/vcond_7.c index d2cdbdcff42..19648ea8d01 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/vcond_7.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/vcond_7.c @@ -62,105 +62,105 @@ FOR_EACH_TYPE (DEF_LOOP) /* { dg-final { scan-assembler-not {\tand\t} } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 2 } } */ - -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ - -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 2 } } */ - -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #1\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #2\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #3\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #4\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ - -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ - -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #1\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #2\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #3\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #4\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmplo\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmplo\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmplo\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmplo\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #1\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #2\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #3\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #4\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ - -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ - -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ - -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #1\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #2\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #3\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #4\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tcmpne\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmplt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #1\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #3\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #4\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ + +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmple\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ + +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpge\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #1\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #3\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpgt\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #4\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmplo\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmplo\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmplo\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmplo\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #1\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #3\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #4\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ + +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmpls\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */ + +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #3\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #4\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #5\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmphs\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphs\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphs\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphs\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.b, p[0-7]/z, z[0-9]+\.b, #1\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, #3\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tcmphi\tp[0-9]+\.d, p[0-7]/z, z[0-9]+\.d, #4\n} 1 } } */ /* { dg-final { scan-assembler-times {\tfcmeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ From patchwork Tue May 9 06:48:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 91392 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2669991vqo; Mon, 8 May 2023 23:53:06 -0700 (PDT) X-Google-Smtp-Source: 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id iy7-20020a170907818700b00965bc999a84si1335893ejc.872.2023.05.08.23.53.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 23:53:05 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=r4SLFRix; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C1BD038555BD for ; Tue, 9 May 2023 06:51:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C1BD038555BD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683615119; bh=+owKYVObOy6IneKSPm+Kjn2bv+N06ENOlEyg55JVcDY=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=r4SLFRixvWCZjMY2vlZH9bYFbS1sVgsk6CEVYYtYE74MY22hQZv0k2Z7xBsGkzsdh jT7ysRiVRGekTqEbSJmW8L23GYYn/yHdIRADRCP/h8o9ewelPxMJRMqDF5/RerCVTR nb1ykQszugosMd5y4E9zkhaGP+OeiAncxg2/dS8k= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id EC4323857712 for ; Tue, 9 May 2023 06:49:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EC4323857712 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11CB21595; Mon, 8 May 2023 23:49:56 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 26A9D3F5A1; Mon, 8 May 2023 23:49:11 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 5/6] aarch64: Relax FP/vector register matches Date: Tue, 9 May 2023 07:48:30 +0100 Message-Id: <20230509064831.1651327-6-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230509064831.1651327-1-richard.sandiford@arm.com> References: <20230509064831.1651327-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-30.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765398477130245601?= X-GMAIL-MSGID: =?utf-8?q?1765398477130245601?= There were many tests that used [0-9] to match an FP or vector register, but that should allow any of 0-31 instead. asm-x-constraint-1.c required s0-s7, but that's the range for "y" rather than "x". "x" allows s0-s15. sve/pcs/return_9.c required z2-z7 (the initial set of available call-clobbered registers), but z24-z31 are OK too. gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c: Allow any FP/vector register, not just register 0-9. * gcc.target/aarch64/fmul_fcvt_2.c: Likewise. * gcc.target/aarch64/ldp_stp_8.c: Likewise. * gcc.target/aarch64/ldp_stp_17.c: Likewise. * gcc.target/aarch64/ldp_stp_21.c: Likewise. * gcc.target/aarch64/simd/vpaddd_f64.c: Likewise. * gcc.target/aarch64/simd/vpaddd_s64.c: Likewise. * gcc.target/aarch64/simd/vpaddd_u64.c: Likewise. * gcc.target/aarch64/sve/adr_1.c: Likewise. * gcc.target/aarch64/sve/adr_2.c: Likewise. * gcc.target/aarch64/sve/adr_3.c: Likewise. * gcc.target/aarch64/sve/adr_4.c: Likewise. * gcc.target/aarch64/sve/adr_5.c: Likewise. * gcc.target/aarch64/sve/extract_1.c: Likewise. * gcc.target/aarch64/sve/extract_2.c: Likewise. * gcc.target/aarch64/sve/extract_3.c: Likewise. * gcc.target/aarch64/sve/extract_4.c: Likewise. * gcc.target/aarch64/sve/slp_4.c: Likewise. * gcc.target/aarch64/sve/spill_3.c: Likewise. * gcc.target/aarch64/vfp-1.c: Likewise. * gcc.target/aarch64/asm-x-constraint-1.c: Allow s0-s15, not just s0-s7. * gcc.target/aarch64/sve/pcs/return_9.c: Allow z24-z31 as well as z2-z7. --- .../aarch64/advsimd-intrinsics/vshl-opt-6.c | 2 +- .../gcc.target/aarch64/asm-x-constraint-1.c | 4 ++-- .../gcc.target/aarch64/fmul_fcvt_2.c | 6 ++--- gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c | 2 +- gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c | 2 +- gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c | 2 +- .../gcc.target/aarch64/simd/vpaddd_f64.c | 2 +- .../gcc.target/aarch64/simd/vpaddd_s64.c | 2 +- .../gcc.target/aarch64/simd/vpaddd_u64.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/adr_1.c | 24 +++++++++---------- gcc/testsuite/gcc.target/aarch64/sve/adr_2.c | 24 +++++++++---------- gcc/testsuite/gcc.target/aarch64/sve/adr_3.c | 24 +++++++++---------- gcc/testsuite/gcc.target/aarch64/sve/adr_4.c | 6 ++--- gcc/testsuite/gcc.target/aarch64/sve/adr_5.c | 16 ++++++------- .../gcc.target/aarch64/sve/extract_1.c | 4 ++-- .../gcc.target/aarch64/sve/extract_2.c | 4 ++-- .../gcc.target/aarch64/sve/extract_3.c | 4 ++-- .../gcc.target/aarch64/sve/extract_4.c | 4 ++-- .../gcc.target/aarch64/sve/pcs/return_9.c | 16 ++++++------- gcc/testsuite/gcc.target/aarch64/sve/slp_4.c | 2 +- .../gcc.target/aarch64/sve/spill_3.c | 8 +++---- gcc/testsuite/gcc.target/aarch64/vfp-1.c | 4 ++-- 22 files changed, 82 insertions(+), 82 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c index 442e3163237..3eff71b53fa 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c @@ -7,4 +7,4 @@ int32x4_t foo (int32x4_t x) { return vshlq_s32(x, vdupq_n_s32(256)); } -/* { dg-final { scan-assembler-times {\tsshl\t.+, v[0-9].4s} 1 } } */ +/* { dg-final { scan-assembler-times {\tsshl\t.+, v[0-9]+.4s} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c b/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c index a71043be504..ecfb01d247e 100644 --- a/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c +++ b/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c @@ -28,7 +28,7 @@ f (void) /* { dg-final { scan-assembler {\t// s7 out: s7\n.*[/]/ s7 in: s7\n} } } */ /* { dg-final { scan-assembler {\t// s8 out: s8\n.*[/]/ s8 in: s8\n} } } */ /* { dg-final { scan-assembler {\t// s15 out: s15\n.*[/]/ s15 in: s15\n} } } */ -/* { dg-final { scan-assembler {\t// s16 out: s16\n.*\tfmov\t(s[0-7]), s16\n.*[/]/ s16 in: \1\n} } } */ -/* { dg-final { scan-assembler {\t// s31 out: s31\n.*\tfmov\t(s[0-7]), s31\n.*[/]/ s31 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s16 out: s16\n.*\tfmov\t(s[0-9]|s1[0-5]), s16\n.*[/]/ s16 in: \1\n} } } */ +/* { dg-final { scan-assembler {\t// s31 out: s31\n.*\tfmov\t(s[0-9]|s1[0-5]), s31\n.*[/]/ s31 in: \1\n} } } */ /* { dg-final { scan-assembler-not {\t// s16 in: s16\n} } } */ /* { dg-final { scan-assembler-not {\t// s31 in: s31\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c b/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c index 8f0240bf5f7..6cb269cf7ae 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c +++ b/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c @@ -64,6 +64,6 @@ main (void) } /* { dg-final { scan-assembler-not "fmul\tv\[0-9\]*.*" } } */ -/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\].4s, v\[0-9\].4s*.*#2" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\].4s, v\[0-9\].4s*.*#3" 1 } } */ -/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\].4s, v\[0-9\].4s*.*#4" 1 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\]+.4s, v\[0-9\]+.4s*.*#2" 1 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\]+.4s, v\[0-9\]+.4s*.*#3" 1 } } */ +/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\]+.4s, v\[0-9\]+.4s*.*#4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c index c1122fc07d5..9260ada2aa5 100644 --- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c +++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c @@ -42,7 +42,7 @@ DUP_FN (8, int64_t); /* ** dup_16_int64_t: -** dup v([0-9])\.2d, x1 +** dup v([0-9]+)\.2d, x1 ** stp q\1, q\1, \[x0\] ** stp q\1, q\1, \[x0, #?32\] ** stp q\1, q\1, \[x0, #?64\] diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c index 462e3c9aabf..d54c322ce86 100644 --- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c +++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c @@ -4,4 +4,4 @@ #include "ldp_stp_8.c" -/* { dg-final { scan-assembler-times "ldp\td\[0-9\], d\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "ldp\td\[0-9\]+, d\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c index 2d9cb6b19d5..b25678323b8 100644 --- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c +++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c @@ -27,4 +27,4 @@ void ldp2 (fvec *a, ivec *b, struct vec_pair *p) *b = p->b; } -/* { dg-final { scan-assembler-times "ldp\td\[0-9\], d\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "ldp\td\[0-9\]+, d\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c index 4e7aaa554b2..9155a0c8d18 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c @@ -23,4 +23,4 @@ main (void) return 0; } -/* { dg-final { scan-assembler "faddp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */ +/* { dg-final { scan-assembler "faddp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\]+.2d+\n" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c index 7fe8c0643d5..18d5d75fc91 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c @@ -23,4 +23,4 @@ main (void) return 0; } -/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */ +/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\]+.2d+\n" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c index 3f5c701ee15..c4eee61df31 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c @@ -23,4 +23,4 @@ main (void) return 0; } -/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */ +/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\]+.2d+\n" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c index 223351c2fc5..ff477685a01 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c @@ -29,18 +29,18 @@ TEST_ALL (LOOP) -/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.b,} 2 } } */ -/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.b,} 2 } } */ -/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.b,} } } */ +/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 2 } } */ +/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 2 } } */ +/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.b,} } } */ -/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.h,} 2 } } */ -/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.h,} 2 } } */ -/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.h,} } } */ +/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 2 } } */ +/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h,} 2 } } */ +/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.h,} } } */ -/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.s,} } } */ -/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.s,} } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.s, \[z[0-9]\.s, z[0-9]\.s, lsl 1\]} 2 } } */ +/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.s,} } } */ +/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.s,} } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl 1\]} 2 } } */ -/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, lsl 1\]} 2 } } */ +/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, lsl 1\]} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_2.c index dc20ddbad00..7ca1dbcb565 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/adr_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_2.c @@ -4,18 +4,18 @@ #define FACTOR 4 #include "adr_1.c" -/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.b,} 2 } } */ -/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.b,} 2 } } */ -/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.b,} } } */ +/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 2 } } */ +/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 2 } } */ +/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.b,} } } */ -/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.h,} 2 } } */ -/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.h,} 2 } } */ -/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.h,} } } */ +/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 2 } } */ +/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h,} 2 } } */ +/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.h,} } } */ -/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.s,} } } */ -/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.s,} } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.s, \[z[0-9]\.s, z[0-9]\.s, lsl 2\]} 2 } } */ +/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.s,} } } */ +/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.s,} } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl 2\]} 2 } } */ -/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, lsl 2\]} 2 } } */ +/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, lsl 2\]} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_3.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_3.c index b0cb180dde3..da21c241a10 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/adr_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_3.c @@ -4,18 +4,18 @@ #define FACTOR 8 #include "adr_1.c" -/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.b,} 2 } } */ -/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.b,} 2 } } */ -/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.b,} } } */ +/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 2 } } */ +/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 2 } } */ +/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.b,} } } */ -/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.h,} 2 } } */ -/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.h,} 2 } } */ -/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.h,} } } */ +/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 2 } } */ +/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h,} 2 } } */ +/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.h,} } } */ -/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.s,} } } */ -/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.s,} } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.s, \[z[0-9]\.s, z[0-9]\.s, lsl 3\]} 2 } } */ +/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.s,} } } */ +/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.s,} } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl 3\]} 2 } } */ -/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, lsl 3\]} 2 } } */ +/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, lsl 3\]} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_4.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_4.c index 7c039ba1380..23778983ee0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/adr_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_4.c @@ -4,6 +4,6 @@ #define FACTOR 16 #include "adr_1.c" -/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.[bhsd],} 8 } } */ -/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.[bhsd],} 8 } } */ -/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.[bhsd],} } } */ +/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.[bhsd],} 8 } } */ +/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.[bhsd],} 8 } } */ +/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.[bhsd],} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_5.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_5.c index ce3991cb2e5..62806825216 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/adr_5.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_5.c @@ -17,11 +17,11 @@ TEST_ALL (LOOP) -/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-not {\tand\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-not {\tuxtw\tz[0-9]\.d,} } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, uxtw\]} 1 } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, uxtw 1\]} 1 } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, uxtw 2\]} 1 } } */ -/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, uxtw 3\]} 1 } } */ +/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-not {\tand\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-not {\tuxtw\tz[0-9]+\.d,} } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, uxtw\]} 1 } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, uxtw 1\]} 1 } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, uxtw 2\]} 1 } } */ +/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, uxtw 3\]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c b/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c index dbcc1d943e1..5d5edf26c19 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c @@ -56,7 +56,7 @@ typedef _Float16 vnx8hf __attribute__((vector_size (32))); TEST_ALL (EXTRACT) -/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]\n} 2 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 2 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 1 { target aarch64_big_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[1\]\n} 1 } } */ /* { dg-final { scan-assembler-not {\tdup\td[0-9]+, v[0-9]+\.d\[0\]\n} } } */ @@ -65,7 +65,7 @@ TEST_ALL (EXTRACT) /* { dg-final { scan-assembler-times {\tlastb\tx[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */ /* { dg-final { scan-assembler-times {\tlastb\td[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]\n} 2 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 2 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 1 { target aarch64_big_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[1\]\n} 1 } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[3\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/extract_2.c b/gcc/testsuite/gcc.target/aarch64/sve/extract_2.c index a48774664dd..0e6ec836228 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/extract_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/extract_2.c @@ -56,7 +56,7 @@ typedef _Float16 vnx16hf __attribute__((vector_size (64))); TEST_ALL (EXTRACT) -/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]\n} 2 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 2 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 1 { target aarch64_big_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[1\]\n} 1 } } */ /* { dg-final { scan-assembler-not {\tdup\td[0-9]+, v[0-9]+\.d\[0\]\n} } } */ @@ -65,7 +65,7 @@ TEST_ALL (EXTRACT) /* { dg-final { scan-assembler-times {\tlastb\tx[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */ /* { dg-final { scan-assembler-times {\tlastb\td[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]\n} 2 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 2 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 1 { target aarch64_big_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[1\]\n} 1 } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[3\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/extract_3.c b/gcc/testsuite/gcc.target/aarch64/sve/extract_3.c index bf10bf16efd..0d7a2fa2527 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/extract_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/extract_3.c @@ -77,7 +77,7 @@ typedef _Float16 vnx32hf __attribute__((vector_size (128))); TEST_ALL (EXTRACT) -/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]\n} 5 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 5 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 1 { target aarch64_big_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[1\]\n} 1 } } */ /* { dg-final { scan-assembler-not {\tdup\td[0-9]+, v[0-9]+\.d\[0\]\n} } } */ @@ -87,7 +87,7 @@ TEST_ALL (EXTRACT) /* { dg-final { scan-assembler-times {\tlastb\tx[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */ /* { dg-final { scan-assembler-times {\tlastb\td[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]\n} 5 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 5 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 1 { target aarch64_big_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[1\]\n} 1 } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[3\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/extract_4.c b/gcc/testsuite/gcc.target/aarch64/sve/extract_4.c index 9805678c12e..a706291023f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/extract_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/extract_4.c @@ -84,7 +84,7 @@ typedef _Float16 v128hf __attribute__((vector_size (256))); TEST_ALL (EXTRACT) -/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]\n} 6 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 6 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 1 { target aarch64_big_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[1\]\n} 1 } } */ /* { dg-final { scan-assembler-not {\tdup\td[0-9]+, v[0-9]+\.d\[0\]\n} } } */ @@ -94,7 +94,7 @@ TEST_ALL (EXTRACT) /* { dg-final { scan-assembler-times {\tlastb\tx[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */ /* { dg-final { scan-assembler-times {\tlastb\td[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]\n} 6 { target aarch64_little_endian } } } */ +/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 6 { target aarch64_little_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 1 { target aarch64_big_endian } } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[1\]\n} 1 } } */ /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[3\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_9.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_9.c index ad32e1fe56d..3b2604e6068 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_9.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_9.c @@ -22,7 +22,7 @@ callee_s8 (void) ** caller_s8: ** ... ** bl callee_s8 -** add (z[2-7]\.b), z2\.b, z3\.b +** add (z(?:[2-7]|2[4-9]|3[01])\.b), z2\.b, z3\.b ** ptrue (p[0-7])\.b, all ** mla z0\.b, \2/m, (z1\.b, \1|\1, z1\.b) ** ldp x29, x30, \[sp\], 16 @@ -57,7 +57,7 @@ callee_u8 (void) ** caller_u8: ** ... ** bl callee_u8 -** sub (z[2-7]\.b), z2\.b, z3\.b +** sub (z(?:[2-7]|2[4-9]|3[01])\.b), z2\.b, z3\.b ** ptrue (p[0-7])\.b, all ** mla z0\.b, \2/m, (z1\.b, \1|\1, z1\.b) ** ldp x29, x30, \[sp\], 16 @@ -93,7 +93,7 @@ callee_s16 (void) ** caller_s16: ** ... ** bl callee_s16 -** add (z[2-7]\.h), z2\.h, z3\.h +** add (z(?:[2-7]|2[4-9]|3[01])\.h), z2\.h, z3\.h ** ptrue (p[0-7])\.b, all ** mad z0\.h, \2/m, (z1\.h, \1|\1, z1\.h) ** ldp x29, x30, \[sp\], 16 @@ -129,7 +129,7 @@ callee_u16 (void) ** caller_u16: ** ... ** bl callee_u16 -** sub (z[2-7]\.h), z2\.h, z3\.h +** sub (z(?:[2-7]|2[4-9]|3[01])\.h), z2\.h, z3\.h ** ptrue (p[0-7])\.b, all ** mad z0\.h, \2/m, (z1\.h, \1|\1, z1\.h) ** ldp x29, x30, \[sp\], 16 @@ -236,7 +236,7 @@ callee_s32 (void) ** caller_s32: ** ... ** bl callee_s32 -** add (z[2-7]\.s), z2\.s, z3\.s +** add (z(?:[2-7]|2[4-9]|3[01])\.s), z2\.s, z3\.s ** ptrue (p[0-7])\.b, all ** msb z0\.s, \2/m, (z1\.s, \1|\1, z1\.s) ** ldp x29, x30, \[sp\], 16 @@ -272,7 +272,7 @@ callee_u32 (void) ** caller_u32: ** ... ** bl callee_u32 -** sub (z[2-7]\.s), z2\.s, z3\.s +** sub (z(?:[2-7]|2[4-9]|3[01])\.s), z2\.s, z3\.s ** ptrue (p[0-7])\.b, all ** msb z0\.s, \2/m, (z1\.s, \1|\1, z1\.s) ** ldp x29, x30, \[sp\], 16 @@ -346,7 +346,7 @@ callee_s64 (void) ** caller_s64: ** ... ** bl callee_s64 -** add (z[2-7]\.d), z2\.d, z3\.d +** add (z(?:[2-7]|2[4-9]|3[01])\.d), z2\.d, z3\.d ** ptrue (p[0-7])\.b, all ** mls z0\.d, \2/m, (z1\.d, \1|\1, z1\.d) ** ldp x29, x30, \[sp\], 16 @@ -382,7 +382,7 @@ callee_u64 (void) ** caller_u64: ** ... ** bl callee_u64 -** sub (z[2-7]\.d), z2\.d, z3\.d +** sub (z(?:[2-7]|2[4-9]|3[01])\.d), z2\.d, z3\.d ** ptrue (p[0-7])\.b, all ** mls z0\.d, \2/m, (z1\.d, \1|\1, z1\.d) ** ldp x29, x30, \[sp\], 16 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_4.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_4.c index 49fb828e874..b1fa5e3cf68 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/slp_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_4.c @@ -38,7 +38,7 @@ TEST_ALL (VEC_PERM) /* 1 for each 8-bit type, 4 for each 32-bit type and 4 for double. */ /* { dg-final { scan-assembler-times {\tld1rd\tz[0-9]+\.d, } 18 } } */ /* 1 for each 16-bit type. */ -/* { dg-final { scan-assembler-times {\tld1rqh\tz[0-9]\.h, } 3 } } */ +/* { dg-final { scan-assembler-times {\tld1rqh\tz[0-9]+\.h, } 3 } } */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #99\n} 2 } } */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #11\n} 2 } } */ /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #17\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/spill_3.c b/gcc/testsuite/gcc.target/aarch64/sve/spill_3.c index 8cb904ed0fb..b90cdb948e3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/spill_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/spill_3.c @@ -38,10 +38,10 @@ TEST_LOOP (uint32_t); /* Four iterations are needed; ought to stay a loop. */ TEST_LOOP (uint64_t); -/* { dg-final { scan-assembler {\tld1b\tz[0-9]\.b} } } */ -/* { dg-final { scan-assembler {\tld1h\tz[0-9]\.h} } } */ -/* { dg-final { scan-assembler {\tld1w\tz[0-9]\.s} } } */ -/* { dg-final { scan-assembler {\tld1d\tz[0-9]\.d} } } */ +/* { dg-final { scan-assembler {\tld1b\tz[0-9]+\.b} } } */ +/* { dg-final { scan-assembler {\tld1h\tz[0-9]+\.h} } } */ +/* { dg-final { scan-assembler {\tld1w\tz[0-9]+\.s} } } */ +/* { dg-final { scan-assembler {\tld1d\tz[0-9]+\.d} } } */ /* { dg-final { scan-assembler-not {\tldr\tz[0-9]} } } */ /* { dg-final { scan-assembler-not {\tstr\tz[0-9]} } } */ /* { dg-final { scan-assembler-not {\tldr\tp[0-9]} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vfp-1.c b/gcc/testsuite/gcc.target/aarch64/vfp-1.c index 02609bb52ba..9bd7d161b1f 100644 --- a/gcc/testsuite/gcc.target/aarch64/vfp-1.c +++ b/gcc/testsuite/gcc.target/aarch64/vfp-1.c @@ -82,13 +82,13 @@ void test_convert () { /* { dg-final { scan-assembler "fcvt\ts\[0-9\]*" } } */ f1 = d1; /* fixsfsi2 */ - /* { dg-final { scan-assembler "fcvtzs\ts\[0-9\], s\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcvtzs\ts\[0-9\]+, s\[0-9\]*" } } */ i1 = f1; /* fixdfsi2 */ /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], d\[0-9\]*" } } */ i1 = d1; /* fixunsfsi2 */ - /* { dg-final { scan-assembler "fcvtzu\ts\[0-9\], s\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcvtzu\ts\[0-9\]+, s\[0-9\]*" } } */ u1 = f1; /* fixunsdfsi2 */ /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], d\[0-9\]*" } } */ From patchwork Tue May 9 06:48:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 91393 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 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e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF1AE3F5A1; Mon, 8 May 2023 23:49:11 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 6/6] aarch64: Avoid hard-coding specific register allocations Date: Tue, 9 May 2023 07:48:31 +0100 Message-Id: <20230509064831.1651327-7-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230509064831.1651327-1-richard.sandiford@arm.com> References: <20230509064831.1651327-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-30.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765398290616684714?= X-GMAIL-MSGID: =?utf-8?q?1765398519943781101?= Some tests hard-coded specific allocations for temporary registers, whereas the RA should be free to pick anything that doesn't force unnecessary moves or spills. gcc/testsuite/ * gcc.target/aarch64/asimd-mul-to-shl-sub.c: Allow any register allocation for temporary results, rather than requiring specific registers. * gcc.target/aarch64/auto-init-padding-1.c: Likewise. * gcc.target/aarch64/auto-init-padding-2.c: Likewise. * gcc.target/aarch64/auto-init-padding-3.c: Likewise. * gcc.target/aarch64/auto-init-padding-4.c: Likewise. * gcc.target/aarch64/auto-init-padding-9.c: Likewise. * gcc.target/aarch64/memset-corner-cases.c: Likewise. * gcc.target/aarch64/memset-q-reg.c: Likewise. * gcc.target/aarch64/simd/vaddlv_1.c: Likewise. * gcc.target/aarch64/sve-neon-modes_1.c: Likewise. * gcc.target/aarch64/sve-neon-modes_3.c: Likewise. * gcc.target/aarch64/sve/load_scalar_offset_1.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_256.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_512.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_1024.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_2048.c: Likewise. * gcc.target/aarch64/sve/pr89007-1.c: Likewise. * gcc.target/aarch64/sve/pr89007-2.c: Likewise. * gcc.target/aarch64/sve/store_scalar_offset_1.c: Likewise. * gcc.target/aarch64/vadd_reduc-1.c: Likewise. * gcc.target/aarch64/vadd_reduc-2.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_bf16.c: Allow the temporary predicate register to be any of p4-p7, rather than requiring p4 specifically. * gcc.target/aarch64/sve/pcs/args_5_be_f16.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_f32.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_f64.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s8.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s16.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s32.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s64.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u8.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u16.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u32.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u64.c: Likewise. --- .../gcc.target/aarch64/asimd-mul-to-shl-sub.c | 4 +- .../gcc.target/aarch64/auto-init-padding-1.c | 2 +- .../gcc.target/aarch64/auto-init-padding-2.c | 3 +- .../gcc.target/aarch64/auto-init-padding-3.c | 3 +- .../gcc.target/aarch64/auto-init-padding-4.c | 3 +- .../gcc.target/aarch64/auto-init-padding-9.c | 2 +- .../gcc.target/aarch64/memset-corner-cases.c | 22 ++++----- .../gcc.target/aarch64/memset-q-reg.c | 22 ++++----- .../gcc.target/aarch64/simd/vaddlv_1.c | 24 +++++----- .../gcc.target/aarch64/sve-neon-modes_1.c | 4 +- .../gcc.target/aarch64/sve-neon-modes_3.c | 16 +++---- .../aarch64/sve/load_scalar_offset_1.c | 8 ++-- .../aarch64/sve/pcs/args_5_be_bf16.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_f16.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_f32.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_f64.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_s16.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_s32.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_s64.c | 18 +++---- .../gcc.target/aarch64/sve/pcs/args_5_be_s8.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_u16.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_u32.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_u64.c | 18 +++---- .../gcc.target/aarch64/sve/pcs/args_5_be_u8.c | 18 +++---- .../aarch64/sve/pcs/return_6_1024.c | 48 +++++++++---------- .../aarch64/sve/pcs/return_6_2048.c | 48 +++++++++---------- .../gcc.target/aarch64/sve/pcs/return_6_256.c | 48 +++++++++---------- .../gcc.target/aarch64/sve/pcs/return_6_512.c | 48 +++++++++---------- .../gcc.target/aarch64/sve/pr89007-1.c | 2 +- .../gcc.target/aarch64/sve/pr89007-2.c | 2 +- .../aarch64/sve/store_scalar_offset_1.c | 8 ++-- .../gcc.target/aarch64/vadd_reduc-1.c | 4 +- .../gcc.target/aarch64/vadd_reduc-2.c | 4 +- 33 files changed, 269 insertions(+), 272 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c b/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c index d7c5e5f341b..28dbe81a37d 100644 --- a/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c +++ b/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c @@ -4,8 +4,8 @@ /* **foo: -** shl v1.4s, v0.4s, 16 -** sub v0.4s, v1.4s, v0.4s +** shl (v[0-9]+.4s), v0.4s, 16 +** sub v0.4s, \1, v0.4s ** ret */ #include diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c index d3a88c72454..c747ebdcdf7 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c @@ -14,4 +14,4 @@ int foo () return var.internal1; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 2 } } */ +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c index aceceb87fbe..6e280904da1 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c @@ -14,5 +14,4 @@ int foo () return var.internal1; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 2 } } */ - +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c index 085c3862921..9ddea58b468 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c @@ -23,5 +23,4 @@ int foo () return var.four.internal1; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 4 } } */ - +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c index 7a6ddbc20ee..75bba82ed34 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c @@ -23,5 +23,4 @@ int foo () return var.four.internal1; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 5 } } */ - +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 5 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c index c81e5ff28b0..0f1930f813e 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c @@ -18,4 +18,4 @@ int foo () return var[2].four; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 5 } } */ +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 5 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c index c43f0199adc..d4c752711f8 100644 --- a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c +++ b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c @@ -29,8 +29,8 @@ set0byte (int64_t *src) /* 35bytes would become 4 scalar instructions. So favour NEON. **set0neon: -** movi v0.4s, 0 -** stp q0, q0, \[x0\] +** movi v([0-9]+).4s, 0 +** stp q\1, q\1, \[x0\] ** str wzr, \[x0, 31\] ** ret */ @@ -56,15 +56,15 @@ set0scalar (int64_t *src) /* 256-bytes expanded **set256byte: -** dup v0.16b, w1 -** stp q0, q0, \[x0\] -** stp q0, q0, \[x0, 32\] -** stp q0, q0, \[x0, 64\] -** stp q0, q0, \[x0, 96\] -** stp q0, q0, \[x0, 128\] -** stp q0, q0, \[x0, 160\] -** stp q0, q0, \[x0, 192\] -** stp q0, q0, \[x0, 224\] +** dup v([0-9]+).16b, w1 +** stp q\1, q\1, \[x0\] +** stp q\1, q\1, \[x0, 32\] +** stp q\1, q\1, \[x0, 64\] +** stp q\1, q\1, \[x0, 96\] +** stp q\1, q\1, \[x0, 128\] +** stp q\1, q\1, \[x0, 160\] +** stp q\1, q\1, \[x0, 192\] +** stp q\1, q\1, \[x0, 224\] ** ret */ void __attribute__((__noinline__)) diff --git a/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c b/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c index 156146badbc..eef5c21f50d 100644 --- a/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c +++ b/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c @@ -6,8 +6,8 @@ /* **set128bits: -** dup v0.16b, w1 -** str q0, \[x0\] +** dup v([0-9]+).16b, w1 +** str q\1, \[x0\] ** ret */ void __attribute__((__noinline__)) @@ -29,9 +29,9 @@ set128bitszero (int64_t *src) /* ** set128bitsplus: -** dup v0.16b, w1 -** str q0, \[x0\] -** str q0, \[x0, 12\] +** dup v([0-9]+).16b, w1 +** str q\1, \[x0\] +** str q\1, \[x0, 12\] ** ret */ void __attribute__((__noinline__)) @@ -42,8 +42,8 @@ set128bitsplus (int64_t *src, char c) /* ** set256bits: -** movi v0.16b, 0x63 -** stp q0, q0, \[x0\] +** movi v([0-9]+).16b, 0x63 +** stp q\1, q\1, \[x0\] ** ret */ void __attribute__((__noinline__)) @@ -66,10 +66,10 @@ set256bitszero (int64_t *src) /* ** set256bitsplus: -** movi v0.16b, 0x63 -** stp q0, q0, \[x0\] -** str q0, \[x0, 32\] -** str d0, \[x0, 48\] +** movi v([0-9]+).16b, 0x63 +** stp q\1, q\1, \[x0\] +** str q\1, \[x0, 32\] +** str d\1, \[x0, 48\] ** ret */ void __attribute__((__noinline__)) diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c index d4afaab5ba5..ef1f13efd2e 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c @@ -12,22 +12,22 @@ foo_##S (IT a) \ } FUNC (int8x8_t, int16_t, s8) -/* { dg-final { scan-assembler-times {saddlv\th0, v0\.8b} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\th[0-9]+, v0\.8b} 1} } */ FUNC (int16x4_t, int32_t, s16) -/* { dg-final { scan-assembler-times {saddlv\ts0, v0\.4h} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\ts[0-9]+, v0\.4h} 1} } */ FUNC (int32x2_t, int64_t, s32) -/* { dg-final { scan-assembler-times {saddlp\tv0\.1d, v0\.2s} 1} } */ +/* { dg-final { scan-assembler-times {saddlp\tv[0-9]+\.1d, v0\.2s} 1} } */ FUNC (uint8x8_t, uint16_t, u8) -/* { dg-final { scan-assembler-times {uaddlv\th0, v0\.8b} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\th[0-9]+, v0\.8b} 1} } */ FUNC (uint16x4_t, uint32_t, u16) -/* { dg-final { scan-assembler-times {uaddlv\ts0, v0\.4h} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\ts[0-9]+, v0\.4h} 1} } */ FUNC (uint32x2_t, uint64_t, u32) -/* { dg-final { scan-assembler-times {uaddlp\tv0.1d, v0\.2s} 1} } */ +/* { dg-final { scan-assembler-times {uaddlp\tv[0-9]+\.1d, v0\.2s} 1} } */ #define FUNCQ(IT, OT, S) \ OT \ @@ -37,20 +37,20 @@ fooq_##S (IT a) \ } FUNCQ (int8x16_t, int16_t, s8) -/* { dg-final { scan-assembler-times {saddlv\th0, v0\.16b} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\th[0-9]+, v0\.16b} 1} } */ FUNCQ (int16x8_t, int32_t, s16) -/* { dg-final { scan-assembler-times {saddlv\ts0, v0\.8h} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\ts[0-9]+, v0\.8h} 1} } */ FUNCQ (int32x4_t, int64_t, s32) -/* { dg-final { scan-assembler-times {saddlv\td0, v0\.4s} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\td[0-9]+, v0\.4s} 1} } */ FUNCQ (uint8x16_t, uint16_t, u8) -/* { dg-final { scan-assembler-times {uaddlv\th0, v0\.16b} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\th[0-9]+, v0\.16b} 1} } */ FUNCQ (uint16x8_t, uint32_t, u16) -/* { dg-final { scan-assembler-times {uaddlv\ts0, v0\.8h} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\ts[0-9]+, v0\.8h} 1} } */ FUNCQ (uint32x4_t, uint64_t, u32) -/* { dg-final { scan-assembler-times {uaddlv\td0, v0\.4s} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\td[0-9]+, v0\.4s} 1} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c index ce4f1c70bcc..c4019aaf4f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c @@ -6,8 +6,8 @@ typedef long v2di __attribute__((vector_size (16))); /* ** foo: -** ptrue p0.b, all -** mul z0.d, p0/m, z0.d, z1.d +** ptrue (p[0-7]).b, all +** mul z0.d, \1/m, z0.d, z1.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c index f1e78a83a9c..f7c93659f4d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c @@ -9,8 +9,8 @@ typedef unsigned int v4usi __attribute__((vector_size (16))); /* ** food: -** ptrue p0.b, all -** sdiv z0.d, p0/m, z0.d, z1.d +** ptrue (p[0-7]).b, all +** sdiv z0.d, \1/m, z0.d, z1.d ** ret */ @@ -22,8 +22,8 @@ food (v2di a, v2di b) /* ** fooud: -** ptrue p0.b, all -** udiv z0.d, p0/m, z0.d, z1.d +** ptrue (p[0-7]).b, all +** udiv z0.d, \1/m, z0.d, z1.d ** ret */ @@ -35,8 +35,8 @@ fooud (v2udi a, v2udi b) /* ** foos: -** ptrue p0.b, all -** sdiv z0.s, p0/m, z0.s, z1.s +** ptrue (p[0-7]).b, all +** sdiv z0.s, \1/m, z0.s, z1.s ** ret */ @@ -48,8 +48,8 @@ foos (v4si a, v4si b) /* ** foous: -** ptrue p0.b, all -** udiv z0.s, p0/m, z0.s, z1.s +** ptrue (p[0-7]).b, all +** udiv z0.s, \1/m, z0.s, z1.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c b/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c index 32905350c27..4d1f7969f7d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c @@ -64,7 +64,7 @@ void sve_load_8_s (int8_t *a) asm volatile ("" :: "w" (*(vnx16qi *)&a[i])); } -/* { dg-final { scan-assembler-times {\tld1d\tz0\.d, p[0-7]/z, \[x0, x1, lsl 3\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tld1w\tz0\.s, p[0-7]/z, \[x0, x1, lsl 2\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tld1h\tz0\.h, p[0-7]/z, \[x0, x1, lsl 1\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tld1b\tz0\.b, p[0-7]/z, \[x0, x1\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x0, x1, lsl 3\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x0, x1, lsl 2\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.h, p[0-7]/z, \[x0, x1, lsl 1\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.b, p[0-7]/z, \[x0, x1\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c index e9b63a45dc3..4002e047977 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** st2h {\2 - \1}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** st2h {\3 - \2}, p0, \[x0\] ** | -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** st2h {\3 - \4}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** st2h {\4 - \5}, p0, \[x0\] ** ) ** st4h {z0\.h - z3\.h}, p1, \[x0\] ** st3h {z4\.h - z6\.h}, p2, \[x0\] ** st1h z7\.h, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c index 4152f91255a..6faf8a3d547 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** st2h {\2 - \1}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** st2h {\3 - \2}, p0, \[x0\] ** | -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** st2h {\3 - \4}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** st2h {\4 - \5}, p0, \[x0\] ** ) ** st4h {z0\.h - z3\.h}, p1, \[x0\] ** st3h {z4\.h - z6\.h}, p2, \[x0\] ** st1h z7\.h, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c index 0f78fac7947..7abd279f21f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** st2w {\2 - \1}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** st2w {\3 - \2}, p0, \[x0\] ** | -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** st2w {\3 - \4}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** st2w {\4 - \5}, p0, \[x0\] ** ) ** st4w {z0\.s - z3\.s}, p1, \[x0\] ** st3w {z4\.s - z6\.s}, p2, \[x0\] ** st1w z7\.s, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c index fe832d0d0a4..eea79659593 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** st2d {\2 - \1}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** st2d {\3 - \2}, p0, \[x0\] ** | -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** st2d {\3 - \4}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** st2d {\4 - \5}, p0, \[x0\] ** ) ** st4d {z0\.d - z3\.d}, p1, \[x0\] ** st3d {z4\.d - z6\.d}, p2, \[x0\] ** st1d z7\.d, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c index 3f708e0f011..59b17a4c9e3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** st2h {\2 - \1}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** st2h {\3 - \2}, p0, \[x0\] ** | -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** st2h {\3 - \4}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** st2h {\4 - \5}, p0, \[x0\] ** ) ** st4h {z0\.h - z3\.h}, p1, \[x0\] ** st3h {z4\.h - z6\.h}, p2, \[x0\] ** st1h z7\.h, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c index 8c57190ea56..8988f9c9ba9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** st2w {\2 - \1}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** st2w {\3 - \2}, p0, \[x0\] ** | -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** st2w {\3 - \4}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** st2w {\4 - \5}, p0, \[x0\] ** ) ** st4w {z0\.s - z3\.s}, p1, \[x0\] ** st3w {z4\.s - z6\.s}, p2, \[x0\] ** st1w z7\.s, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c index e60d049fbd3..4719b4120e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** st2d {\2 - \1}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** st2d {\3 - \2}, p0, \[x0\] ** | -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** st2d {\3 - \4}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** st2d {\4 - \5}, p0, \[x0\] ** ) ** st4d {z0\.d - z3\.d}, p1, \[x0\] ** st3d {z4\.d - z6\.d}, p2, \[x0\] ** st1d z7\.d, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c index bc0058372cb..995f3e70bf2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1b (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\] -** ld1b (z[0-9]+\.b), p4/z, \[x1\] -** st2b {\2 - \1}, p0, \[x0\] +** ld1b (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\] +** ld1b (z[0-9]+\.b), \1/z, \[x1\] +** st2b {\3 - \2}, p0, \[x0\] ** | -** ld1b (z[0-9]+\.b), p4/z, \[x1\] -** ld1b (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\] -** st2b {\3 - \4}, p0, \[x0\] +** ld1b (z[0-9]+\.b), \1/z, \[x1\] +** ld1b (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\] +** st2b {\4 - \5}, p0, \[x0\] ** ) ** st4b {z0\.b - z3\.b}, p1, \[x0\] ** st3b {z4\.b - z6\.b}, p2, \[x0\] ** st1b z7\.b, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c index 8aa651a415e..0b84622ad4a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** st2h {\2 - \1}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** st2h {\3 - \2}, p0, \[x0\] ** | -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** st2h {\3 - \4}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** st2h {\4 - \5}, p0, \[x0\] ** ) ** st4h {z0\.h - z3\.h}, p1, \[x0\] ** st3h {z4\.h - z6\.h}, p2, \[x0\] ** st1h z7\.h, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c index 9ea3066edea..a5892f7b63b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** st2w {\2 - \1}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** st2w {\3 - \2}, p0, \[x0\] ** | -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** st2w {\3 - \4}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** st2w {\4 - \5}, p0, \[x0\] ** ) ** st4w {z0\.s - z3\.s}, p1, \[x0\] ** st3w {z4\.s - z6\.s}, p2, \[x0\] ** st1w z7\.s, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c index b64f3b6d57b..67438e8e562 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** st2d {\2 - \1}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** st2d {\3 - \2}, p0, \[x0\] ** | -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** st2d {\3 - \4}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** st2d {\4 - \5}, p0, \[x0\] ** ) ** st4d {z0\.d - z3\.d}, p1, \[x0\] ** st3d {z4\.d - z6\.d}, p2, \[x0\] ** st1d z7\.d, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c index 5575673aeb3..61d694c6c9c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1b (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\] -** ld1b (z[0-9]+\.b), p4/z, \[x1\] -** st2b {\2 - \1}, p0, \[x0\] +** ld1b (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\] +** ld1b (z[0-9]+\.b), \1/z, \[x1\] +** st2b {\3 - \2}, p0, \[x0\] ** | -** ld1b (z[0-9]+\.b), p4/z, \[x1\] -** ld1b (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\] -** st2b {\3 - \4}, p0, \[x0\] +** ld1b (z[0-9]+\.b), \1/z, \[x1\] +** ld1b (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\] +** st2b {\4 - \5}, p0, \[x0\] ** ) ** st4b {z0\.b - z3\.b}, p1, \[x0\] ** st3b {z4\.b - z6\.b}, p2, \[x0\] ** st1b z7\.b, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c index de69d9a42ce..6c716ef7c34 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c @@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (128))); /* ** callee_s8: ** ptrue (p[0-7])\.b, vl128 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (s8, svint8_t) @@ -39,8 +39,8 @@ CALLEE (s8, svint8_t) /* ** callee_u8: ** ptrue (p[0-7])\.b, vl128 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (u8, svuint8_t) @@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t) /* ** callee_s16: ** ptrue (p[0-7])\.b, vl128 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (s16, svint16_t) @@ -57,8 +57,8 @@ CALLEE (s16, svint16_t) /* ** callee_u16: ** ptrue (p[0-7])\.b, vl128 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (u16, svuint16_t) @@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t) /* ** callee_f16: ** ptrue (p[0-7])\.b, vl128 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (f16, svfloat16_t) @@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t) /* ** callee_bf16: ** ptrue (p[0-7])\.b, vl128 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (bf16, svbfloat16_t) @@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t) /* ** callee_s32: ** ptrue (p[0-7])\.b, vl128 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (s32, svint32_t) @@ -93,8 +93,8 @@ CALLEE (s32, svint32_t) /* ** callee_u32: ** ptrue (p[0-7])\.b, vl128 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (u32, svuint32_t) @@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t) /* ** callee_f32: ** ptrue (p[0-7])\.b, vl128 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (f32, svfloat32_t) @@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t) /* ** callee_s64: ** ptrue (p[0-7])\.b, vl128 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (s64, svint64_t) @@ -120,8 +120,8 @@ CALLEE (s64, svint64_t) /* ** callee_u64: ** ptrue (p[0-7])\.b, vl128 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (u64, svuint64_t) @@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t) /* ** callee_f64: ** ptrue (p[0-7])\.b, vl128 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (f64, svfloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c index 0b64ff2e8c2..0eb9607d9db 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c @@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (256))); /* ** callee_s8: ** ptrue (p[0-7])\.b, vl256 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (s8, svint8_t) @@ -39,8 +39,8 @@ CALLEE (s8, svint8_t) /* ** callee_u8: ** ptrue (p[0-7])\.b, vl256 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (u8, svuint8_t) @@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t) /* ** callee_s16: ** ptrue (p[0-7])\.b, vl256 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (s16, svint16_t) @@ -57,8 +57,8 @@ CALLEE (s16, svint16_t) /* ** callee_u16: ** ptrue (p[0-7])\.b, vl256 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (u16, svuint16_t) @@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t) /* ** callee_f16: ** ptrue (p[0-7])\.b, vl256 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (f16, svfloat16_t) @@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t) /* ** callee_bf16: ** ptrue (p[0-7])\.b, vl256 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (bf16, svbfloat16_t) @@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t) /* ** callee_s32: ** ptrue (p[0-7])\.b, vl256 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (s32, svint32_t) @@ -93,8 +93,8 @@ CALLEE (s32, svint32_t) /* ** callee_u32: ** ptrue (p[0-7])\.b, vl256 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (u32, svuint32_t) @@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t) /* ** callee_f32: ** ptrue (p[0-7])\.b, vl256 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (f32, svfloat32_t) @@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t) /* ** callee_s64: ** ptrue (p[0-7])\.b, vl256 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (s64, svint64_t) @@ -120,8 +120,8 @@ CALLEE (s64, svint64_t) /* ** callee_u64: ** ptrue (p[0-7])\.b, vl256 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (u64, svuint64_t) @@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t) /* ** callee_f64: ** ptrue (p[0-7])\.b, vl256 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (f64, svfloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c index 9eb71e3dcc3..749eb332599 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c @@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (32))); /* ** callee_s8: ** ptrue (p[0-7])\.b, vl32 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (s8, svint8_t) @@ -39,8 +39,8 @@ CALLEE (s8, svint8_t) /* ** callee_u8: ** ptrue (p[0-7])\.b, vl32 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (u8, svuint8_t) @@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t) /* ** callee_s16: ** ptrue (p[0-7])\.b, vl32 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (s16, svint16_t) @@ -57,8 +57,8 @@ CALLEE (s16, svint16_t) /* ** callee_u16: ** ptrue (p[0-7])\.b, vl32 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (u16, svuint16_t) @@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t) /* ** callee_f16: ** ptrue (p[0-7])\.b, vl32 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (f16, svfloat16_t) @@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t) /* ** callee_bf16: ** ptrue (p[0-7])\.b, vl32 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (bf16, svbfloat16_t) @@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t) /* ** callee_s32: ** ptrue (p[0-7])\.b, vl32 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (s32, svint32_t) @@ -93,8 +93,8 @@ CALLEE (s32, svint32_t) /* ** callee_u32: ** ptrue (p[0-7])\.b, vl32 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (u32, svuint32_t) @@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t) /* ** callee_f32: ** ptrue (p[0-7])\.b, vl32 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (f32, svfloat32_t) @@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t) /* ** callee_s64: ** ptrue (p[0-7])\.b, vl32 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (s64, svint64_t) @@ -120,8 +120,8 @@ CALLEE (s64, svint64_t) /* ** callee_u64: ** ptrue (p[0-7])\.b, vl32 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (u64, svuint64_t) @@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t) /* ** callee_f64: ** ptrue (p[0-7])\.b, vl32 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (f64, svfloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c index 8b8d0c7c860..f6a64cc4944 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c @@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (64))); /* ** callee_s8: ** ptrue (p[0-7])\.b, vl64 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (s8, svint8_t) @@ -39,8 +39,8 @@ CALLEE (s8, svint8_t) /* ** callee_u8: ** ptrue (p[0-7])\.b, vl64 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (u8, svuint8_t) @@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t) /* ** callee_s16: ** ptrue (p[0-7])\.b, vl64 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (s16, svint16_t) @@ -57,8 +57,8 @@ CALLEE (s16, svint16_t) /* ** callee_u16: ** ptrue (p[0-7])\.b, vl64 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (u16, svuint16_t) @@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t) /* ** callee_f16: ** ptrue (p[0-7])\.b, vl64 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (f16, svfloat16_t) @@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t) /* ** callee_bf16: ** ptrue (p[0-7])\.b, vl64 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (bf16, svbfloat16_t) @@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t) /* ** callee_s32: ** ptrue (p[0-7])\.b, vl64 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (s32, svint32_t) @@ -93,8 +93,8 @@ CALLEE (s32, svint32_t) /* ** callee_u32: ** ptrue (p[0-7])\.b, vl64 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (u32, svuint32_t) @@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t) /* ** callee_f32: ** ptrue (p[0-7])\.b, vl64 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (f32, svfloat32_t) @@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t) /* ** callee_s64: ** ptrue (p[0-7])\.b, vl64 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (s64, svint64_t) @@ -120,8 +120,8 @@ CALLEE (s64, svint64_t) /* ** callee_u64: ** ptrue (p[0-7])\.b, vl64 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (u64, svuint64_t) @@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t) /* ** callee_f64: ** ptrue (p[0-7])\.b, vl64 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (f64, svfloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c index ff9550c9109..d65aa94a52a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c @@ -15,7 +15,7 @@ unsigned char in2[N]; ** add (z[0-9]+\.b), (\1, \2|\2, \1) ** orr (z[0-9]+)\.d, z[0-9]+\.d, z[0-9]+\.d ** and (z[0-9]+\.b), \5\.b, #0x1 -** add z0\.b, (\3, \6|\6, \3) +** add z[0-9]+\.b, (\3, \6|\6, \3) ** ... */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c index da345fe8bd6..1de44df96c9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c @@ -15,7 +15,7 @@ unsigned char in2[N]; ** add (z[0-9]+\.b), (\1, \2|\2, \1) ** and (z[0-9]+)\.d, z[0-9]+\.d, z[0-9]+\.d ** and (z[0-9]+\.b), \5\.b, #0x1 -** add z0\.b, (\3, \6|\6, \3) +** add z[0-9]+\.b, (\3, \6|\6, \3) ** ... */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c b/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c index 4f0655f6d7c..c742b92b934 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c @@ -49,7 +49,7 @@ void sve_store_8_s (signed long i, int8_t *a) asm volatile ("" : "=w" (*(vnx16qi *) &a[i])); } -/* { dg-final { scan-assembler-times {\tst1d\tz0\.d, p[0-7], \[x0, x1, lsl 3\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1w\tz0\.s, p[0-7], \[x0, x1, lsl 2\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1h\tz0\.h, p[0-7], \[x0, x1, lsl 1\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1b\tz0\.b, p[0-7], \[x1, x0\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d, p[0-7], \[x0, x1, lsl 3\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s, p[0-7], \[x0, x1, lsl 2\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h, p[0-7], \[x0, x1, lsl 1\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.b, p[0-7], \[x1, x0\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c index 271a1c3e8c3..c158db3aa39 100644 --- a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c +++ b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c @@ -9,8 +9,8 @@ typedef int v4si __attribute__ ((vector_size (16))); /* **bar: ** ... -** addv s0, v0.4s -** fmov w0, s0 +** addv (s[0-9]+), v0.4s +** fmov w0, \1 ** lsr w1, w0, 16 ** add w0, w1, w0, uxth ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c index 0ad96954ff7..b4d4face2e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c +++ b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c @@ -9,8 +9,8 @@ /* **test: ** ... -** addv s0, v0.4s -** fmov w0, s0 +** addv (s[0-9]+), v[0-9]+.4s +** fmov w0, \1 ** and w1, w0, 65535 ** add w0, w1, w0, lsr 16 ** lsr w0, w0, 1