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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id tc7-20020a1709078d0700b00969ee4ffaf0si316801ejc.913.2023.05.08.19.20.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 19:20:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BE83F3857707 for ; Tue, 9 May 2023 02:20:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id 28C2D3858D35 for ; Tue, 9 May 2023 02:19:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 28C2D3858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp87t1683598776t6xr57xe Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 09 May 2023 10:19:35 +0800 (CST) X-QQ-SSF: 01400000000000F0Q000000A0000000 X-QQ-FEAT: CR3LFp2JE4kswbijyT8FSJ1sD0fLLflxIbte2yA9sigydYc7yVIrle2XmFONF eDkv572DI+lptjzP1gVN6Mz3IeZyEDLmvxD4sXkbvqR8Y8H7lRJow3oNKguKXtBOxfHzZX6 uLbbqrcnjZ5enmnSnQOiOyScOGYGjscG7yU7utgSDa3UK8df5GtlLXrsvzckQ8WAoQiUj+m mYVAe7J9xg2Z/BlxhAO0SgDwcRGXJC8R7E/o7Vw5fHHmQZHKpeViJXNntgpUSTFuQGcMmaG Se7NuM/dNZdJEuj/Wq2MPvVSoPYLCNIXsImJQ96vaTuTtcla/utR05XiqgReSFV5Uyg6yGa O0FJ9c4YRjY2aRezeYFo3YHry0YznTE2fZxPvpXz6zKdgJbwUMYYuiscRw20yBHk0GIxy9N b0ekOcAqtcU= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17627581487726670806 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix dead loop for user vsetvli intrinsic avl checking [PR109773] Date: Tue, 9 May 2023 10:19:34 +0800 Message-Id: <20230509021934.958640-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765381316947804515?= X-GMAIL-MSGID: =?utf-8?q?1765381316947804515?= From: Juzhe-Zhong This patch is fix dead loop in vsetvl intrinsic avl checking. vsetvli->get_def () has vsetvli->get_def () has vsetvli..... Then it will keep looping in the vsetvli avl checking which is a dead loop. PR target/109773 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (avl_source_has_vsetvl_p): New function. (source_equal_p): Fix dead loop in vsetvl avl checking. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: New test. * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 25 ++++++++++++++++++ .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c | 20 ++++++++++++++ .../gcc.target/riscv/rvv/vsetvl/pr109773-2.c | 26 +++++++++++++++++++ 3 files changed, 71 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 72aa2bfcf6f..2577b2bd9b7 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1056,6 +1056,24 @@ change_vsetvl_insn (const insn_info *insn, const vector_insn_info &info) change_insn (rinsn, new_pat); } +static bool +avl_source_has_vsetvl_p (set_info *avl_source) +{ + if (!avl_source) + return false; + if (!avl_source->insn ()) + return false; + if (avl_source->insn ()->is_real ()) + return vsetvl_insn_p (avl_source->insn ()->rtl ()); + hash_set sets = get_all_sets (avl_source, true, false, true); + for (const auto set : sets) + { + if (set->insn ()->is_real () && vsetvl_insn_p (set->insn ()->rtl ())) + return true; + } + return false; +} + static bool source_equal_p (insn_info *insn1, insn_info *insn2) { @@ -1098,6 +1116,13 @@ source_equal_p (insn_info *insn1, insn_info *insn2) vector_insn_info insn1_info, insn2_info; insn1_info.parse_insn (insn1); insn2_info.parse_insn (insn2); + + /* To avoid dead loop, we don't optimize a vsetvli def has vsetvli + instructions which will complicate the situation. */ + if (avl_source_has_vsetvl_p (insn1_info.get_avl_source ()) + || avl_source_has_vsetvl_p (insn2_info.get_avl_source ())) + return false; + if (insn1_info.same_vlmax_p (insn2_info) && insn1_info.compatible_avl_p (insn2_info)) return true; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c new file mode 100644 index 00000000000..8656e473117 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void f (int32_t *a, int32_t *b, int n) +{ + if (n <= 0) + return; + int i = n; + size_t vl = __riscv_vsetvl_e8mf4 (i); + for (; i >= 0; i--) + { + vint32m1_t v = __riscv_vle32_v_i32m1 (a + i, vl); + __riscv_vse32_v_i32m1 (b + i, v, vl); + vl = __riscv_vsetvl_e8mf4 (vl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c new file mode 100644 index 00000000000..7bfbaaf3713 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void f (int32_t * a, int32_t * b, int n) +{ + if (n <= 0) + return; + int i = n; + size_t vl = __riscv_vsetvl_e8mf4 (i); + for (; i >= 0; i--) + { + vint32m1_t v = __riscv_vle32_v_i32m1 (a + i, vl); + v = __riscv_vle32_v_i32m1_tu (v, a + i + 100, vl); + __riscv_vse32_v_i32m1 (b + i, v, vl); + + if (i >= vl) + continue; + if (i == 0) + return; + vl = __riscv_vsetvl_e8mf4 (vl); + } +} + +/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */