From patchwork Mon May 8 14:28:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91192 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2210400vqo; Mon, 8 May 2023 07:46:09 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7sed9fdENIw+WemLMt4JDX0hFOHvWwoqDBKzUW7CyJ4ZTws3T9h1aLGHwyWGFb0/aqNZvq X-Received: by 2002:a05:6a00:15d2:b0:642:fbed:2820 with SMTP id o18-20020a056a0015d200b00642fbed2820mr13809593pfu.30.1683557168731; Mon, 08 May 2023 07:46:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683557168; cv=none; d=google.com; s=arc-20160816; b=jBdx2Nnr0J6UK8M67S6+4sA0CU0EAFspzoa90D8zG+EV7l5G/CTa/zyKsW6Hs15TMG NicOLHWtRHfupQGHfQ1Nac33LU8Xo79AvaVMR4AVtJQTyL/yYfxqPQZ7WION+dulCrTu rPp3x3qNQEZPYcfBA8z3BNg9T0EQNtyfkwAPrAerUYS/i/B2EeiFCgVkC+ZZMvExc4vk R1yyuKQl8EKklK2TbMlgRoHU96LbJoLKkBatKW2rufMv+GWAuPIPvhZH4bffTVSUEaVR 8eXmNEMy3Ldxd9PjsJqUesbDDYbcbPKeH3gIAwEe4lRPQD+WkLBPUDss1ra4MX9WE5M9 bVlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rCnijZqZqbTFwmvqbOqYG9D3eO4SsXuxft0NUX8zz8A=; b=ziXCKilsK+OvlupVzD3Mc9+gfWgd8HhGW4h7H/cszkEKgFOTFNUAxRRFTRpie8DbJx yUL6TE5Ph3E7fEemldele5aVte8Ba/K/wvCaiDMrx9xaxLBtLj00Vo3EmvJkImAGlXz7 zaANvEM1hZLjcTeITefc8HQ7NmRJcFTGTzorcynyLcVcHAKW6ufIuhzdQyp1v+ciKv5B Ow+OzpOnIj2lO6c18zR5YA6ZkEqIRZsy07mfGH3eVj1JAZeLkqq6Zem1GFpK5XcWKfzn Kz/p4Jwm5fBuKBBvkwnbJcN9eeNErNyeivEZtmB6FkjyO4N1+79jlNwN63Md+wuqLkTz Aosw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=nsRbPLks; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a15-20020a63704f000000b0051322a8d2aesi8417326pgn.110.2023.05.08.07.45.53; Mon, 08 May 2023 07:46:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=nsRbPLks; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234546AbjEHO3M (ORCPT + 99 others); Mon, 8 May 2023 10:29:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234523AbjEHO3K (ORCPT ); Mon, 8 May 2023 10:29:10 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A60C72AB for ; Mon, 8 May 2023 07:29:05 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-643990c5373so4415605b3a.1 for ; Mon, 08 May 2023 07:29:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556145; x=1686148145; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rCnijZqZqbTFwmvqbOqYG9D3eO4SsXuxft0NUX8zz8A=; b=nsRbPLksBMxCFlI4Dk5W+JxUo5zwuNx1VEvGmsPZxoLBxbf7fhQP9i9unfigIlTOGz yBuJmPoM8nOnC5hnhATZOfDLAyouQ2Q7WduLsqd07D9e35BWU5kpZVAKtyHp/i3vATYz rjmsbzldIuJctLEnJmHxe0Ab8RabRHamwkH1Y2UGs20FDaQ+aPapOVNTV11A/sf8VxTF C1uahOKpgwutooogbk3seey0VKk8V0YhVIHz4k77bIvMfaA+CDPWhyz7WP87x4LYfU2u 94KStMnCfY6REGFJu8024uIkI9tQIuItHRT+VxNw3MnYO7oXswuE1gHKFDBl/FPRvUqX wy+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556145; x=1686148145; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rCnijZqZqbTFwmvqbOqYG9D3eO4SsXuxft0NUX8zz8A=; b=f2yBbTGeFDLbvJPdU7uzeKK5aK9tJA+vRX3Gw50B8IKaWE5DIlDXQZPD5bl69dSSrz 4WLxooeNhuqqHhecL+LQibU/4NtWtfM5iwy3v/tkMdswUMJAcIPWCnp3S0JStfAg1pxu vXigBGDGXG8dGrgrwlSWTgvAQKfETX5nOCOlnaimfMzG1uvLbXeVNao9WmaBrJLKf2Gh ZV6q/w0uijB6Q9RyF5Ek4wtGoWwTkPiAXYCOcLCQQU9Z2fiGqalLR+SLGcccQGUfL8tZ afl2Z6CipeRl99C2dSUxcZyVA1rJbHbA2Pgnz1cJ8CVDs9E/BSISpoUeohdvFiAf4Fz6 XzcQ== X-Gm-Message-State: AC+VfDzGDEoozynRkL/0358ETRPJjF5WfNz9ef/0V5NvdNPgmC4uak/3 DGQSeR1jQRJl1wJI0u4WyjuSBw== X-Received: by 2002:a05:6a00:a21:b0:62a:d752:acc5 with SMTP id p33-20020a056a000a2100b0062ad752acc5mr14331891pfh.32.1683556144804; Mon, 08 May 2023 07:29:04 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:04 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 01/11] RISC-V: Add riscv_fw_parent_hartid() function Date: Mon, 8 May 2023 19:58:32 +0530 Message-Id: <20230508142842.854564-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765337641885446734?= X-GMAIL-MSGID: =?utf-8?q?1765337641885446734?= We add common riscv_fw_parent_hartid() which help device drivers to get parent hartid of the INTC (i.e. local interrupt controller) fwnode. Currently, this new function only supports device tree but it can be extended to support ACPI as well. Signed-off-by: Anup Patel --- arch/riscv/include/asm/processor.h | 3 +++ arch/riscv/kernel/cpu.c | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..6fb8bbec8459 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -77,6 +77,9 @@ struct device_node; int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); +struct fwnode_handle; +int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid); + extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 5de6fb703cc2..1adbe48b2b58 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -73,6 +73,18 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) return -1; } +/* Find hart ID of the CPU fwnode under which given fwnode falls. */ +int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid) +{ + /* + * Currently, this function only supports DT but it can be + * extended to support ACPI as well. + */ + if (!is_of_node(node)) + return -EINVAL; + return riscv_of_parent_hartid(to_of_node(node), hartid); +} + DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); unsigned long riscv_cached_mvendorid(unsigned int cpu_id) From patchwork Mon May 8 14:28:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91179 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2202725vqo; Mon, 8 May 2023 07:33:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7ji/Zf/rkvpz3OXEqfKPP9Aw1O/DzcLWysydcQySWa+cEbxHhxFF1UpwjTFFa7D6mxMC4U X-Received: by 2002:a17:902:efc5:b0:1a6:566b:dd73 with SMTP id ja5-20020a170902efc500b001a6566bdd73mr9993302plb.60.1683556415091; Mon, 08 May 2023 07:33:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683556415; cv=none; d=google.com; s=arc-20160816; b=IvhJBwbXUwUdlRl/1LgphMPgXvKSjD9NY/AksNPhXCwRCkKx3bfTfteNoQDw0ImTGK m9/IK2O6M4hIe67t6DdLNjm00HNxN8YNaDvWJtBooFIITy0uYAP8WNfsZIEvEJ+h4M9Q nnIfJeE9w8UIjI2f/SBSD1IqDBGzZG3/CK3W+QvFUQHk8ECB/uDKdzSHe/Yi6YE+I/uJ h45ybqIZsyHNc8CKxodK0vxsoXYYOcJh2Vh6e4tzsYuni3cPOmncSeiYZ6cgLnvsHjZA E/x5Sl5DUI9js2MmwpBosUAeN2D3sAljLepyt6kMEG5sTR+IdL/L5fJwLSoaCpw1XShJ e1Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=m1nY2tFDgGEcA5BPTW/qPM4ksEcua9dIFA1MwwOUg+w=; b=llipa5dJBCkWGhjj+XHILGmSILMuP9gURrGSmEKOZr/iEtrWmemUsz9fJfTdua0TmK u/VWu5y61nTvIreeryNny/EXbLu2SS13fNs5Fu4XYs/NxuIwXx8w3DHh4NOWUfNuiPjg ZWC9CZWGPSV6nh/padnai84Ddfj3Fs2uaSXMo7qC91GOMnUGNVHGco5/UsuxFyKwx6Xr 9klRk1poETgw11UtyZ2WvAfKP+rSS3Ng4lVUsUdq5T6u3FVLvkHpGUvfzJfxl8JET1lb xc/CuZmn8zZudlUIB7PqMvdmJgpTcZISUSKXXPgC+h6isE5NTWlZD7LjDwAL6uG/pr1A cAEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Y4KeKeEH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z4-20020a170902708400b001ac82e8491dsi1383868plk.345.2023.05.08.07.33.20; Mon, 08 May 2023 07:33:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Y4KeKeEH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234576AbjEHO3h (ORCPT + 99 others); Mon, 8 May 2023 10:29:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234586AbjEHO33 (ORCPT ); Mon, 8 May 2023 10:29:29 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35D9E4C34 for ; Mon, 8 May 2023 07:29:10 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-64359d9c531so3371268b3a.3 for ; Mon, 08 May 2023 07:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556149; x=1686148149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m1nY2tFDgGEcA5BPTW/qPM4ksEcua9dIFA1MwwOUg+w=; b=Y4KeKeEH2HyNjQj1MvzsAagGgVRUdpfCpDFHN+2mKM/yIL5V4lC3/r8BWTBVPv8mr8 crG2m3zs5hnPIFNLt92hug/24EbFLZl8MHqF6s0UAd9n57VO1wIMukU5t9t3dDPg2PRO sO9zoJNKGTBkOC3klDG6HaL02odtnyoCMZY6HzIpeP2+t3qrT/fC9nsHjjuQ7NCuBZj+ aq2dtuWODDaoxaCpgUoNZGGP1z628C7yRSBp+4ZUOT0oExNHPCeb8h1cRwyar7P0p+2V wseYx1vo0wkd9RoXyot8Efac9RcekQ3hmC2u3e4HorVZQmu9AI0obr74p9qEtJZc0r2+ fkMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556149; x=1686148149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m1nY2tFDgGEcA5BPTW/qPM4ksEcua9dIFA1MwwOUg+w=; b=cXUGDhWyKS/TJGusTMWNpN3Gq5ltXzxSyScvFJFhi/mLFioh1564csrdz/fmn4OxHo o86jvi7Z1lzrwWhFs0BvDo2Dap80bkhLUTINdOm32pfBMD1x+Fnf+l90cmSzmIO4+bye P6kFxErv2XikPiFQ/zsAgDbN7lCy47m+KCHfu3YWEG8nn1SVmc0CzAD5H8xSEwDOCohj RR4rkpdMP7YMZaOq8kGPfMN3zCp6tBqfAqh3cKnu/mx9aEwrUNhX5ss9Dp0FCETBHro2 fFTjhEneD1KoLguYm9VS6Q7ipxW1weChxEYUdtupGaTYco5gEVkidjUMnHtb/iPnyCi0 PxDg== X-Gm-Message-State: AC+VfDwv/bLTKWpjPGiORY9CFCi23WkXakBcSTavnJK2phNUQ9oZ+/aD NVxy0Vi98D4X08mowcXkrG/Pfg== X-Received: by 2002:a05:6a00:1503:b0:643:96e:666b with SMTP id q3-20020a056a00150300b00643096e666bmr13783594pfu.34.1683556149506; Mon, 08 May 2023 07:29:09 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:09 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 02/11] of/irq: Set FWNODE_FLAG_BEST_EFFORT for the interrupt controller DT nodes Date: Mon, 8 May 2023 19:58:33 +0530 Message-Id: <20230508142842.854564-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765336851762239132?= X-GMAIL-MSGID: =?utf-8?q?1765336851762239132?= The RISC-V APLIC interrupt controller driver is a regular platform driver so we need to ensure that it is probed as soon as possible. To achieve this, we mark the interrupt controller device nodes with FWNODE_FLAG_BEST_EFFORT (just like console DT node). Fixes: 8f486cab263c ("driver core: fw_devlink: Allow firmware to mark devices as best effort") Signed-off-by: Anup Patel --- drivers/of/irq.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 174900072c18..94e1d9245cff 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -535,6 +535,16 @@ void __init of_irq_init(const struct of_device_id *matches) INIT_LIST_HEAD(&intc_desc_list); INIT_LIST_HEAD(&intc_parent_list); + /* + * We need interrupt controller platform drivers to work as soon + * as possible so mark the interrupt controller device nodes with + * FWNODE_FLAG_BEST_EFFORT so that fw_delink knows not to delay + * the probe of the interrupt controller device for suppliers + * without drivers. + */ + for_each_node_with_property(np, "interrupt-controller") + np->fwnode.flags |= FWNODE_FLAG_BEST_EFFORT; + for_each_matching_node_and_match(np, matches, &match) { if (!of_property_read_bool(np, "interrupt-controller") || !of_device_is_available(np)) From patchwork Mon May 8 14:28:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91177 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2202582vqo; Mon, 8 May 2023 07:33:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7aIeJKBP1LTQq4XJHB/s3qzNSerVSS/hm5qt/H5AUSVVHXK4GJZ2VRPb7MSTkG65d4mQdL X-Received: by 2002:a17:903:124f:b0:1ac:451d:34a with SMTP id u15-20020a170903124f00b001ac451d034amr13141384plh.33.1683556401981; Mon, 08 May 2023 07:33:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683556401; cv=none; d=google.com; s=arc-20160816; b=nLyWCDMktrq/nOvw9/n1FtgRwZP8yJhUEgy2jJ2duGadccU40CCJXgMGvm/8Xh0Bas 2iZ/0YVkvFG1832d37lfkcbsfR6cM6ljorxJYqI67DoC9YYk1O9LPJe3wZqteWhhuMrs QCo7ZFK3uCslDXrOXO6gDi1rSez3S4+FTboK0RGxPNvSRcFxDvU65hgCGkuXr5Pf1VEg fnw6XL89Q4JaWEcqAwdTeIP0vCFAvHgppVz/828L0y8LNKRIGUVnW/RnZwC4LDzKhUav YfxMSyk1SiofxFdp5hn5SOq5dfkKmNIR2JN7O/GZwnYQZWKnAEThRZgGuIGLdd1oU5YC SBrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XXSsvlQ/R6yHM0Hz/nbqBTRJ+migXFNIKunDjIZh+EE=; b=zgL5pA+EgzU7GMzW6gzfsclsm+AsIrBCjbEe4xhAdO8w2/CLlZhKDD4mu2sNwRHiXH OAaOBO63Vo4ZF+sDABi2HWuk/5WquUP77B9D5CrMbz5hPUlmT8sRziySPs6/NHiolhdY /XPboywGN9rFJ3M/dEdsPKzM0CND2cdgOR+rzaPj4thdGxHJs9RP4k1wj4oyI4646x0e 2MXWNOdPdEuDUeXqKeRXiJkBVgMPl7Vhpo+eB1K1WvuVTycOskjuCHWCCXTxwnGH/Lh/ FmrbnHjB3p9k4vPwqHpG+TUoVcaqsmgywDgHRZM2CZvHWbLmPbBXj5R7ViptfmVuQxhn u5Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="DweqYW/w"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h7-20020a170902ac8700b001a9f42553ddsi7933727plr.296.2023.05.08.07.33.06; Mon, 08 May 2023 07:33:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="DweqYW/w"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234592AbjEHO3r (ORCPT + 99 others); Mon, 8 May 2023 10:29:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234631AbjEHO3e (ORCPT ); Mon, 8 May 2023 10:29:34 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC50E769A for ; Mon, 8 May 2023 07:29:14 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-643990c5373so4415741b3a.1 for ; Mon, 08 May 2023 07:29:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556154; x=1686148154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XXSsvlQ/R6yHM0Hz/nbqBTRJ+migXFNIKunDjIZh+EE=; b=DweqYW/wrp2Hf6/tVp5eeVH4LnisiW9pU5JubLDyr0brsc0HBnW8Qgyr1eFnd5QfXK 8w4qBpjYMQah6H1nRgtuXFq59MELnCpNXOFOdjeszMPCrkyVCInlZgzLC1Jq6h3U0gzj 1U+VyQRCz1W2lHAYuK9sV/KyTfdpUh/o4R/Umu35gl0DHT+wQ5xhgCQf4yCT+UgnO877 5JzFxsXO14oRxKst0J6FSwH4DF1anEFXBqoEEqBt3Mjr3dS/UbPv59e+DaQhVgNeZPfw JyGEa7GHoWYIj/EDesISBqmzze/6QFm98thoAnFGsp2XFWF2ezTT8bdnc7chD2cr595N FHhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556154; x=1686148154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XXSsvlQ/R6yHM0Hz/nbqBTRJ+migXFNIKunDjIZh+EE=; b=WevlDJF5uIZCOSUmUI6POmfjFpY6tFm4kXFQ3OIA+LMdLsfYFPiiRCtljU3EldjoMq ipGit9o0fYL8G10ukpAkCN/LVfbfDhgWVScpHOYnVAy7UsJg7IcLioQ6TzLcxY/Se9jq TI8tk0bZYBGBvXVGvAPDb4CHEIOkPLP/LqVwzVO07JupCl5C91J7RwBoHodlzNnScQzA eyZB1q3Ri6yfYnh3J3H4lG7cWovxgtpjxIBZz23j6E2MuGmGYVqBIZwGi3CcI9BgpBeK XIa5Y0TLd2Tp3fpDi8deVO7nDK/ogDR1GhNI2hEzrYw9Kvi6dxtKy7h4ZypIQHlPS6Eh C3lw== X-Gm-Message-State: AC+VfDzcGWnu8BAExQtoVULFtwVPeb455RPG+N3w7r6crQNRDXn0bjlS ofHEkx9Qk7hHSoyCJd37S9tT2Q== X-Received: by 2002:a05:6a00:23c4:b0:63d:254a:3901 with SMTP id g4-20020a056a0023c400b0063d254a3901mr13848595pfc.25.1683556154240; Mon, 08 May 2023 07:29:14 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:13 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 03/11] irqchip/riscv-intc: Add support for RISC-V AIA Date: Mon, 8 May 2023 19:58:34 +0530 Message-Id: <20230508142842.854564-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765336837705181236?= X-GMAIL-MSGID: =?utf-8?q?1765336837705181236?= The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller This patch adds support for RISC-V AIA in the RISC-V intc driver. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 36 ++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 4adeee1bc391..e235bf1708a4 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include static struct irq_domain *intc_domain; @@ -30,6 +31,15 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) generic_handle_domain_irq(intc_domain, cause); } +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) +{ + unsigned long topi; + + while ((topi = csr_read(CSR_TOPI))) + generic_handle_domain_irq(intc_domain, + topi >> TOPI_IID_SHIFT); +} + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written @@ -39,12 +49,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) static void riscv_intc_irq_mask(struct irq_data *d) { - csr_clear(CSR_IE, BIT(d->hwirq)); + if (d->hwirq < BITS_PER_LONG) + csr_clear(CSR_IE, BIT(d->hwirq)); + else + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); } static void riscv_intc_irq_unmask(struct irq_data *d) { - csr_set(CSR_IE, BIT(d->hwirq)); + if (d->hwirq < BITS_PER_LONG) + csr_set(CSR_IE, BIT(d->hwirq)); + else + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); } static void riscv_intc_irq_eoi(struct irq_data *d) @@ -115,16 +131,22 @@ static struct fwnode_handle *riscv_intc_hwnode(void) static int __init riscv_intc_init_common(struct fwnode_handle *fn) { - int rc; + int rc, nr_irqs = BITS_PER_LONG; + + if (riscv_isa_extension_available(NULL, SxAIA) && BITS_PER_LONG == 32) + nr_irqs = nr_irqs * 2; - intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, + intc_domain = irq_domain_create_linear(fn, nr_irqs, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; } - rc = set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc = set_handle_irq(&riscv_intc_aia_irq); + else + rc = set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -132,7 +154,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + pr_info("%d local interrupts mapped%s\n", + nr_irqs, (riscv_isa_extension_available(NULL, SxAIA)) ? + " using AIA" : ""); return 0; } From patchwork Mon May 8 14:28:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91190 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2209968vqo; Mon, 8 May 2023 07:45:30 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5EXosnkud+9rjSWGnKIbm+Ecrx7l4NeT9H343TusoIuhYJ9g3yvh4erBfFR6+jyYRLKxWq X-Received: by 2002:a05:6a20:d81b:b0:f5:6cb8:f4 with SMTP id iv27-20020a056a20d81b00b000f56cb800f4mr12683771pzb.16.1683557129851; Mon, 08 May 2023 07:45:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683557129; cv=none; d=google.com; s=arc-20160816; b=zzIhIb+sNy4bl4UATYMXBKCHaZPtMO5BHXrp1xKJ5v2S1QH0aE85v+qtxgMCGcYTcY I3DtxvhIBm0twx5mvVzuTgX4gUfCXI+o/OAnT+ZREreo7wW2qV0i7X1bKiM07KcM0KaE CTXSJtQR1xZBJSjy/9DUCJf5I92PQHBBx4ZP6CWMPimZDF6chfjFbckmRRhcm8HnYq/0 /8WaqUEZVhkyyf5T6PUbVZyg9bVXIJB6lwBnX3tqyVdzxa0v9ApevyOf72z/NeLCS8Fw 4+krAQz6fxmssQhAazCjmsG7c2dfhkFTWKsptR1sIHtK+60Qmz77cW2ELrGzez5hMCtG 9nJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=N59rxkdYZA75SdcQLdoupuBl4MQdly/YxY4hY1fh15A=; b=x+/Kg54h0c877RQAWqcCzLTExfJ4O9cXV9CR0L7GMdpDq05RZiozTGR4DjzyMJJdSq MGAI+5i9WojC1cqIFQINFaMXNx2jT94DnR5PAXFoOlnKtonvFM6+x8XDkUo4yYPn2UgC 8H3dgBWNUl8iFGaDR3Kn4DfieSQOwHhFhtZ3dmzDTmY6b02OVdVOYMM6MdOsdyIEKpp5 PmS4UOruYbOMXvoEt71cspdMJumUWIgt8Dq1JaY/WiBx3sow+HoaVbfZKn17bQnWWMNg JOsk8TqOxHAYGbetgZlpnay9pbmJ1l/2gVL4fRKKz1oNWymxVaNxLzIiHb6mzPaU4rfs PaGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=UQaJc5hg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b15-20020a63714f000000b004dffd0e0409si8096751pgn.518.2023.05.08.07.45.14; Mon, 08 May 2023 07:45:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=UQaJc5hg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234498AbjEHO35 (ORCPT + 99 others); Mon, 8 May 2023 10:29:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234612AbjEHO3i (ORCPT ); Mon, 8 May 2023 10:29:38 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BF579010 for ; Mon, 8 May 2023 07:29:19 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-6434e263962so3401545b3a.2 for ; Mon, 08 May 2023 07:29:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556159; x=1686148159; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N59rxkdYZA75SdcQLdoupuBl4MQdly/YxY4hY1fh15A=; b=UQaJc5hgt0zxDb26qFqMa3zhzlc20Btk/7b3pmoyfGVMwuQff0ihQFCpFbr2FLVL+d KM72UcUFTXoxZJaiLbBjX2wq3EEsoQIhxCe2kCzSKDJ8XA07NcfhYewApVvumbXgr/l6 Wdjg62Veayj8efnEif0ynVpiK1rRXTGoitkljHvIGo8OhxjcDL+bxVQSeegZ9k2leDA4 Sy13dFYuDO0CDwwZsAzsts9iPyDX0cnxCOGDfQC1Co4Ff91SHwWUd4Ajms+REbJYZm90 qN879ANhf9KsNTOKQTv9S4iD+xeYJcSJVMq6u9KnCKqrKWYR3jLQY8JaphntOgxbKtml m+Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556159; x=1686148159; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N59rxkdYZA75SdcQLdoupuBl4MQdly/YxY4hY1fh15A=; b=E2kq28pj7nwqa9cS+AsaJnkKg7FZHSjCiHzSwB171u0YDAJpcgFpGqAUMEKY/gqzWH Gg7/1wh5aSb+Q0U3bbsC7ZIbBaWAGNsLZ3ygtCIVBRKt9x1jXVj3y1Y6SGhbL1lHOnCS 9XF//wLHHo6fg91aZjeSKLA0c/4+QQ3e4ciTRG0GAX5S3ZI/uE1uwCBOY4j9OoFuBHtz 6f/uauOIsvNZrImCFV8N+0Lw4itN7Vc50V0cFr7+Vb1Ng7vWqHMsN/iIXjjaW3DstL6i f3N78VPBKBgR9MANkIAIeSgJnrCTzWxyMrsMmFPuXe0GlBl2AklEwHiWSM1b+sm2hTI7 Q6VQ== X-Gm-Message-State: AC+VfDzEqzY5aR/Pkhw/NkgUeCs8oJsUlfCPEebs/hFR5GOC74xrx4ji isYFFhlcuGibQ5sQgeg1W2szhQ== X-Received: by 2002:aa7:888c:0:b0:63b:859f:f094 with SMTP id z12-20020aa7888c000000b0063b859ff094mr14232648pfe.20.1683556158925; Mon, 08 May 2023 07:29:18 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:18 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 04/11] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Date: Mon, 8 May 2023 19:58:35 +0530 Message-Id: <20230508142842.854564-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765337601134525250?= X-GMAIL-MSGID: =?utf-8?q?1765337601134525250?= We add DT bindings document for the RISC-V incoming MSI controller (IMSIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- .../interrupt-controller/riscv,imsics.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml new file mode 100644 index 000000000000..b2e70fc44dd0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Incoming MSI Controller (IMSIC) + +maintainers: + - Anup Patel + +description: | + The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming + MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V + AIA specification can be found at https://github.com/riscv/riscv-aia. + + The IMSIC is a per-CPU (or per-HART) device with separate interrupt file + for each privilege level (machine or supervisor). The configuration of + a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO + space to receive MSIs from devices. Each IMSIC interrupt file supports a + fixed number of interrupt identities (to distinguish MSIs from devices) + which is same for given privilege level across CPUs (or HARTs). + + The device tree of a RISC-V platform will have one IMSIC device tree node + for each privilege level (machine or supervisor) which collectively describe + IMSIC interrupt files at that privilege level across CPUs (or HARTs). + + The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform + follows a particular scheme defined by the RISC-V AIA specification. A IMSIC + group is a set of IMSIC interrupt files co-located in MMIO space and we can + have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a + RISC-V platform. The MSI target address of a IMSIC interrupt file at given + privilege level (machine or supervisor) encodes group index, HART index, + and guest index (shown below). + + XLEN-1 > (HART Index MSB) 12 0 + | | | | + ------------------------------------------------------------- + |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | + ------------------------------------------------------------- + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,imsics + - const: riscv,imsics + + reg: + minItems: 1 + maxItems: 16384 + description: + Base address of each IMSIC group. + + interrupt-controller: true + + "#interrupt-cells": + const: 0 + + msi-controller: true + + "#msi-cells": + const: 0 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + This property represents the set of CPUs (or HARTs) for which given + device tree node describes the IMSIC interrupt files. Each node pointed + to should be a riscv,cpu-intc node, which has a riscv node (i.e. RISC-V + HART) as parent. + + riscv,num-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities supported by IMSIC interrupt file. + + riscv,num-guest-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities are supported by IMSIC guest interrupt + file. When not specified it is assumed to be same as specified by the + riscv,num-ids property. + + riscv,guest-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of guest index bits in the MSI target address. + + riscv,hart-index-bits: + minimum: 0 + maximum: 15 + description: + Number of HART index bits in the MSI target address. When not + specified it is calculated based on the interrupts-extended property. + + riscv,group-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of group index bits in the MSI target address. + + riscv,group-index-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 55 + default: 24 + description: + The least significant bit position of the group index bits in the + MSI target address. + +required: + - compatible + - reg + - interrupt-controller + - msi-controller + - "#msi-cells" + - interrupts-extended + - riscv,num-ids + +unevaluatedProperties: false + +examples: + - | + // Example 1 (Machine-level IMSIC files with just one group): + + interrupt-controller@24000000 { + compatible = "qemu,imsics", "riscv,imsics"; + interrupts-extended = <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg = <0x28000000 0x4000>; + interrupt-controller; + #interrupt-cells = <0>; + msi-controller; + #msi-cells = <0>; + riscv,num-ids = <127>; + }; + + - | + // Example 2 (Supervisor-level IMSIC files with two groups): + + interrupt-controller@28000000 { + compatible = "qemu,imsics", "riscv,imsics"; + interrupts-extended = <&cpu1_intc 9>, + <&cpu2_intc 9>, + <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg = <0x28000000 0x2000>, /* Group0 IMSICs */ + <0x29000000 0x2000>; /* Group1 IMSICs */ + interrupt-controller; + #interrupt-cells = <0>; + msi-controller; + #msi-cells = <0>; + riscv,num-ids = <127>; + riscv,group-index-bits = <1>; + riscv,group-index-shift = <24>; + }; +... From patchwork Mon May 8 14:28:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91181 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2203068vqo; Mon, 8 May 2023 07:34:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4fQV8xSO/vbSj95I24MsphWzyhedKV6YnhrYBkAiMv023BD4bWtD24SsB7q/pGxGNH9hR3 X-Received: by 2002:a17:902:cec9:b0:19a:a9d8:e47f with SMTP id d9-20020a170902cec900b0019aa9d8e47fmr14951983plg.36.1683556445531; Mon, 08 May 2023 07:34:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683556445; cv=none; d=google.com; s=arc-20160816; b=s97VC7TxcZUwmoe+5c1OXGfHPep1QCKiRtSK7XHmQpuVWAVevLGNJdjDHpYNZMFGZs aUwf8pIoPoZ7AEdOlQI2KjuyQq1zB0oosEiG1xFUDImh825T5WT8zKKGQg3DIUQhMcwZ gm7DHCgL288pWritB9r55mBBgClXq/nyGcauxqiDW8VIy4uvDdK4TMRo9MVY5XVaXH2K Neu1N0NgbCkbrVjoOC8GVn04nmZMxYxkRbgSAWFM9VE+zehyQHP9MVO0eNDIy8ulXoko MTK5uUGUPQC4pLvnhQJJIINcTjDl5/yZ4GwEgKyMXl7HwTXahnmynmYcJ+vy3RhL5FhM CXiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JwW95pqHScvrGvuBIm+iu5PF6Ncj9C+0HTf8I6zEdmU=; b=ptwNJCH9Ik69PVHMn+VEcuQN8IeripPu9GfiDYLKbEydrzxcwaYnJdZgi3biYtxLz8 SmKNo08u/Ha9lO8fgrhOO8I1d4qygxeydgMSn1epT/2RMQ35eoHBWrj2/cJjz3CNJZo8 UIWHhX8WeK/SpLM7oWGKvjnp1LQzhpOmx45RSvSKdpDzf1A1qPl0Sz4or1tjDCeqQY+5 T/MCtA8WFdRim/eqzehfCyzShUDUjp3A02HT3PcrWnfWQkubVFcsu13UO8BfMK80FAlk H8/Lc+6OcG6FR2LoZSBgKAne+bSRosevRzLn+OlSA3orLcTzpjxtxabWhLTn+Cuck3ty o5wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="Ky/BQIZB"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w23-20020a1709027b9700b001aafb6fcf51si7978169pll.253.2023.05.08.07.33.50; Mon, 08 May 2023 07:34:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="Ky/BQIZB"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234377AbjEHOaF (ORCPT + 99 others); Mon, 8 May 2023 10:30:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234705AbjEHO3r (ORCPT ); Mon, 8 May 2023 10:29:47 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0012383EC for ; Mon, 8 May 2023 07:29:24 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-643bb9cdd6eso2120533b3a.1 for ; Mon, 08 May 2023 07:29:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556164; x=1686148164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JwW95pqHScvrGvuBIm+iu5PF6Ncj9C+0HTf8I6zEdmU=; b=Ky/BQIZB0G9pMUQbno9qy5fbMuEXExmaD5wSVNd7mB5ZDoUzCCkON0rjJf5LxZzmEp 7n52tpq5O9tRQjfp6AZaO3C9CiuaavydxaGKEW0ElGqQlp40mehfWp1tmDeNIJ4/v1ay GcU8wQ9m5ZP0g9CI+6KBxBr4njrvk/bvvKG9Z9ir5NMCPX1m1fw2X+2MesuvW7M3vlk2 rxfRj8P6ims3hSm1DMR9tQVjequf020QWoX1qUu7LXnr2hanL/opdyjFe9pTCNPmWl28 Eg6PAuTWyTVyfPR/wXpUMWg/I6VVQzELDONU51j6Z6ILBwfZg0n74ofIuaDlJ/gIhxtd LlAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556164; x=1686148164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JwW95pqHScvrGvuBIm+iu5PF6Ncj9C+0HTf8I6zEdmU=; b=Lyzo4Ojy71gLVhq1ToM9keaXLjhpwCkgYSAS4QcSvkSEqd1HB+/Xt70671i9j/YIgF 4KVIHJLziuELX+Y2HXRVtAmvFmWHsM64Tub/jY30rW0KbhQOWTJyRGJLGabPAED4PwX8 QSXjfM4nzdHwVJGY8tNsPWJebk1H40S8ezntCPqWUheH7nNKz0MbFC8+NQDUUxI623HO 0xjWHtGhASMHfOam3VM0pQTM7NvX88QjAl1yx0kzoc/5zXfHiLly4dBPDHBHUSGOZuWN 2IIWZid21GLezgF4Jabvp1ctNtcEJHbj2p6Wp7479NTaIhfuK1ft5WNQMamKYDimSXNU SZUw== X-Gm-Message-State: AC+VfDwshiDhoTq/llN/7dOj4yvjkjs/bZxrT19F7pQkoBXqFVksWKfK O/RCAHdL9CVnRCuO+8bzTUll1A== X-Received: by 2002:a05:6a00:1794:b0:645:b13e:e674 with SMTP id s20-20020a056a00179400b00645b13ee674mr5245141pfg.26.1683556163953; Mon, 08 May 2023 07:29:23 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:23 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 05/11] irqchip: Add RISC-V incoming MSI controller driver Date: Mon, 8 May 2023 19:58:36 +0530 Message-Id: <20230508142842.854564-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765336883488883778?= X-GMAIL-MSGID: =?utf-8?q?1765336883488883778?= The RISC-V advanced interrupt architecture (AIA) specification defines a new MSI controller for managing MSIs and IPIs on a RISC-V platform. This new MSI controller is referred to as incoming message signalled interrupt controller (IMSIC) which manages MSI on per-HART (or per-CPU) basis. (For more details refer https://github.com/riscv/riscv-aia) This patch adds an irqchip driver for RISC-V IMSIC which provides IPIs and platform MSIs to the Linux RISC-V kernel. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 +- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-imsic.c | 1028 +++++++++++++++++++++++++++ include/linux/irqchip/riscv-imsic.h | 86 +++ 4 files changed, 1121 insertions(+), 1 deletion(-) create mode 100644 drivers/irqchip/irq-riscv-imsic.c create mode 100644 include/linux/irqchip/riscv-imsic.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 09e422da482f..8ef18be5f37b 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -30,7 +30,6 @@ config ARM_GIC_V2M config GIC_NON_BANKED bool - config ARM_GIC_V3 bool select IRQ_DOMAIN_HIERARCHY @@ -545,6 +544,12 @@ config SIFIVE_PLIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP +config RISCV_IMSIC + bool + depends on RISCV + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index ffd945fe71aa..577bde3e986b 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o +obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic.o obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c new file mode 100644 index 000000000000..971fad638c9f --- /dev/null +++ b/drivers/irqchip/irq-riscv-imsic.c @@ -0,0 +1,1028 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv-imsic: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMSIC_DISABLE_EIDELIVERY 0 +#define IMSIC_ENABLE_EIDELIVERY 1 +#define IMSIC_DISABLE_EITHRESHOLD 1 +#define IMSIC_ENABLE_EITHRESHOLD 0 + +/* + * The IMSIC driver uses 1 IPI for ID synchronization and + * arch/riscv/kernel/smp.c require 6 IPIs so we fix the + * total number of IPIs to 8. + */ +#define IMSIC_NR_IPI 8 + +#define imsic_csr_write(__c, __v) \ +do { \ + csr_write(CSR_ISELECT, __c); \ + csr_write(CSR_IREG, __v); \ +} while (0) + +#define imsic_csr_read(__c) \ +({ \ + unsigned long __v; \ + csr_write(CSR_ISELECT, __c); \ + __v = csr_read(CSR_IREG); \ + __v; \ +}) + +#define imsic_csr_set(__c, __v) \ +do { \ + csr_write(CSR_ISELECT, __c); \ + csr_set(CSR_IREG, __v); \ +} while (0) + +#define imsic_csr_clear(__c, __v) \ +do { \ + csr_write(CSR_ISELECT, __c); \ + csr_clear(CSR_IREG, __v); \ +} while (0) + +struct imsic_priv { + /* Global configuration common for all HARTs */ + struct imsic_global_config global; + + /* Global state of interrupt identities */ + raw_spinlock_t ids_lock; + unsigned long *ids_used_bimap; + unsigned long *ids_enabled_bimap; + unsigned int *ids_target_cpu; + + /* Mask for connected CPUs */ + struct cpumask lmask; + + /* IPI interrupt identity and synchronization */ + u32 ipi_id; + int ipi_virq; + struct irq_desc *ipi_lsync_desc; + + /* IRQ domains */ + struct irq_domain *base_domain; + struct irq_domain *plat_domain; +}; + +static struct imsic_priv *imsic; +static int imsic_parent_irq; + +const struct imsic_global_config *imsic_get_global_config(void) +{ + return (imsic) ? &imsic->global : NULL; +} +EXPORT_SYMBOL_GPL(imsic_get_global_config); + +static int imsic_cpu_page_phys(unsigned int cpu, + unsigned int guest_index, + phys_addr_t *out_msi_pa) +{ + struct imsic_global_config *global; + struct imsic_local_config *local; + + global = &imsic->global; + local = per_cpu_ptr(global->local, cpu); + + if (BIT(global->guest_index_bits) <= guest_index) + return -EINVAL; + + if (out_msi_pa) + *out_msi_pa = local->msi_pa + + (guest_index * IMSIC_MMIO_PAGE_SZ); + + return 0; +} + +static int imsic_get_cpu(const struct cpumask *mask_val, bool force, + unsigned int *out_target_cpu) +{ + struct cpumask amask; + unsigned int cpu; + + cpumask_and(&amask, &imsic->lmask, mask_val); + + if (force) + cpu = cpumask_first(&amask); + else + cpu = cpumask_any_and(&amask, cpu_online_mask); + + if (cpu >= nr_cpu_ids) + return -EINVAL; + + if (out_target_cpu) + *out_target_cpu = cpu; + + return 0; +} + +static void imsic_id_set_target(unsigned int id, unsigned int target_cpu) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + imsic->ids_target_cpu[id] = target_cpu; + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); +} + +static unsigned int imsic_id_get_target(unsigned int id) +{ + unsigned int ret; + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + ret = imsic->ids_target_cpu[id]; + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + return ret; +} + +static void __imsic_eix_update(unsigned long base_id, + unsigned long num_id, bool pend, bool val) +{ + unsigned long i, isel, ireg; + unsigned long id = base_id, last_id = base_id + num_id; + + while (id < last_id) { + isel = id / BITS_PER_LONG; + isel *= BITS_PER_LONG / IMSIC_EIPx_BITS; + isel += (pend) ? IMSIC_EIP0 : IMSIC_EIE0; + + ireg = 0; + for (i = id & (__riscv_xlen - 1); + (id < last_id) && (i < __riscv_xlen); i++) { + ireg |= BIT(i); + id++; + } + + /* + * The IMSIC EIEx and EIPx registers are indirectly + * accessed via using ISELECT and IREG CSRs so we + * need to access these CSRs without getting preempted. + * + * All existing users of this function call this + * function with local IRQs disabled so we don't + * need to do anything special here. + */ + if (val) + imsic_csr_set(isel, ireg); + else + imsic_csr_clear(isel, ireg); + } +} + +#define __imsic_id_enable(__id) \ + __imsic_eix_update((__id), 1, false, true) +#define __imsic_id_disable(__id) \ + __imsic_eix_update((__id), 1, false, false) + +static void imsic_ids_local_sync(void) +{ + int i; + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + for (i = 1; i <= imsic->global.nr_ids; i++) { + if (imsic->ipi_id == i) + continue; + + if (test_bit(i, imsic->ids_enabled_bimap)) + __imsic_id_enable(i); + else + __imsic_id_disable(i); + } + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); +} + +static void imsic_ids_local_delivery(bool enable) +{ + if (enable) { + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD); + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY); + } else { + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_DISABLE_EIDELIVERY); + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_DISABLE_EITHRESHOLD); + } +} + +#ifdef CONFIG_SMP +static irqreturn_t imsic_ids_sync_handler(int irq, void *data) +{ + imsic_ids_local_sync(); + return IRQ_HANDLED; +} + +static void imsic_ids_remote_sync(void) +{ + struct cpumask amask; + + /* + * We simply inject ID synchronization IPI to all target CPUs + * except current CPU. The ipi_send_mask() implementation of + * IPI mux will inject ID synchronization IPI only for CPUs + * that have enabled it so offline CPUs won't receive IPI. + * An offline CPU will unconditionally synchronize IDs through + * imsic_starting_cpu() when the CPU is brought up. + */ + cpumask_andnot(&amask, &imsic->lmask, cpumask_of(smp_processor_id())); + __ipi_send_mask(imsic->ipi_lsync_desc, &amask); +} +#else +#define imsic_ids_remote_sync() +#endif + +static int imsic_ids_alloc(unsigned int order) +{ + int ret; + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + ret = bitmap_find_free_region(imsic->ids_used_bimap, + imsic->global.nr_ids + 1, order); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + return ret; +} + +static void imsic_ids_free(unsigned int base_id, unsigned int order) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + bitmap_release_region(imsic->ids_used_bimap, base_id, order); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); +} + +static int __init imsic_ids_init(void) +{ + int i; + struct imsic_global_config *global = &imsic->global; + + raw_spin_lock_init(&imsic->ids_lock); + + /* Allocate used bitmap */ + imsic->ids_used_bimap = bitmap_zalloc(global->nr_ids + 1, GFP_KERNEL); + if (!imsic->ids_used_bimap) + return -ENOMEM; + + /* Allocate enabled bitmap */ + imsic->ids_enabled_bimap = bitmap_zalloc(global->nr_ids + 1, + GFP_KERNEL); + if (!imsic->ids_enabled_bimap) { + kfree(imsic->ids_used_bimap); + return -ENOMEM; + } + + /* Allocate target CPU array */ + imsic->ids_target_cpu = kcalloc(global->nr_ids + 1, + sizeof(unsigned int), GFP_KERNEL); + if (!imsic->ids_target_cpu) { + bitmap_free(imsic->ids_enabled_bimap); + bitmap_free(imsic->ids_used_bimap); + return -ENOMEM; + } + for (i = 0; i <= global->nr_ids; i++) + imsic->ids_target_cpu[i] = UINT_MAX; + + /* Reserve ID#0 because it is special and never implemented */ + bitmap_set(imsic->ids_used_bimap, 0, 1); + + return 0; +} + +static void __init imsic_ids_cleanup(void) +{ + kfree(imsic->ids_target_cpu); + bitmap_free(imsic->ids_enabled_bimap); + bitmap_free(imsic->ids_used_bimap); +} + +#ifdef CONFIG_SMP +static void imsic_ipi_send(unsigned int cpu) +{ + struct imsic_local_config *local = + per_cpu_ptr(imsic->global.local, cpu); + + writel(imsic->ipi_id, local->msi_va); +} + +static void imsic_ipi_starting_cpu(void) +{ + /* Enable IPIs for current CPU. */ + __imsic_id_enable(imsic->ipi_id); + + /* Enable virtual IPI used for IMSIC ID synchronization */ + enable_percpu_irq(imsic->ipi_virq, 0); +} + +static void imsic_ipi_dying_cpu(void) +{ + /* + * Disable virtual IPI used for IMSIC ID synchronization so + * that we don't receive ID synchronization requests. + */ + disable_percpu_irq(imsic->ipi_virq); +} + +static int __init imsic_ipi_domain_init(void) +{ + int virq; + + /* Allocate interrupt identity for IPIs */ + virq = imsic_ids_alloc(get_count_order(1)); + if (virq < 0) + return virq; + imsic->ipi_id = virq; + + /* Create IMSIC IPI multiplexing */ + virq = ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send); + if (virq <= 0) { + imsic_ids_free(imsic->ipi_id, get_count_order(1)); + return (virq < 0) ? virq : -ENOMEM; + } + imsic->ipi_virq = virq; + + /* First vIRQ is used for IMSIC ID synchronization */ + virq = request_percpu_irq(imsic->ipi_virq, imsic_ids_sync_handler, + "riscv-imsic-lsync", imsic->global.local); + if (virq) { + imsic_ids_free(imsic->ipi_id, get_count_order(1)); + return virq; + } + irq_set_status_flags(imsic->ipi_virq, IRQ_HIDDEN); + imsic->ipi_lsync_desc = irq_to_desc(imsic->ipi_virq); + + /* Set vIRQ range */ + riscv_ipi_set_virq_range(imsic->ipi_virq + 1, IMSIC_NR_IPI - 1, true); + + return 0; +} + +static void __init imsic_ipi_domain_cleanup(void) +{ + if (imsic->ipi_lsync_desc) + free_percpu_irq(imsic->ipi_virq, imsic->global.local); + imsic_ids_free(imsic->ipi_id, get_count_order(1)); +} +#else +static void imsic_ipi_starting_cpu(void) +{ +} + +static void imsic_ipi_dying_cpu(void) +{ +} + +static int __init imsic_ipi_domain_init(void) +{ + /* Clear the IPI id because we are not using IPIs */ + imsic->ipi_id = 0; + return 0; +} + +static void __init imsic_ipi_domain_cleanup(void) +{ +} +#endif + +static void imsic_irq_mask(struct irq_data *d) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + bitmap_clear(imsic->ids_enabled_bimap, d->hwirq, 1); + __imsic_id_disable(d->hwirq); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + imsic_ids_remote_sync(); +} + +static void imsic_irq_unmask(struct irq_data *d) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + bitmap_set(imsic->ids_enabled_bimap, d->hwirq, 1); + __imsic_id_enable(d->hwirq); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + imsic_ids_remote_sync(); +} + +static void imsic_irq_compose_msi_msg(struct irq_data *d, + struct msi_msg *msg) +{ + struct msi_desc *desc = irq_data_get_msi_desc(d); + phys_addr_t msi_addr; + unsigned int cpu; + int err; + + cpu = imsic_id_get_target(d->hwirq); + if (WARN_ON(cpu == UINT_MAX)) + return; + + err = imsic_cpu_page_phys(cpu, 0, &msi_addr); + if (WARN_ON(err)) + return; + + msg->address_hi = upper_32_bits(msi_addr); + msg->address_lo = lower_32_bits(msi_addr); + msg->data = d->hwirq; + iommu_dma_compose_msi_msg(desc, msg); +} + +#ifdef CONFIG_SMP +static int imsic_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, + bool force) +{ + unsigned int target_cpu; + int rc; + + rc = imsic_get_cpu(mask_val, force, &target_cpu); + if (rc) + return rc; + + imsic_id_set_target(d->hwirq, target_cpu); + irq_data_update_effective_affinity(d, cpumask_of(target_cpu)); + + return IRQ_SET_MASK_OK; +} +#endif + +static struct irq_chip imsic_irq_base_chip = { + .name = "RISC-V IMSIC-BASE", + .irq_mask = imsic_irq_mask, + .irq_unmask = imsic_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity = imsic_irq_set_affinity, +#endif + .irq_compose_msi_msg = imsic_irq_compose_msi_msg, + .flags = IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int imsic_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + msi_alloc_info_t *info = args; + phys_addr_t msi_addr; + int i, hwirq, err = 0; + unsigned int cpu; + + err = imsic_get_cpu(&imsic->lmask, false, &cpu); + if (err) + return err; + + err = imsic_cpu_page_phys(cpu, 0, &msi_addr); + if (err) + return err; + + hwirq = imsic_ids_alloc(get_count_order(nr_irqs)); + if (hwirq < 0) + return hwirq; + + err = iommu_dma_prepare_msi(info->desc, msi_addr); + if (err) + goto fail; + + for (i = 0; i < nr_irqs; i++) { + imsic_id_set_target(hwirq + i, cpu); + irq_domain_set_info(domain, virq + i, hwirq + i, + &imsic_irq_base_chip, imsic, + handle_simple_irq, NULL, NULL); + irq_set_noprobe(virq + i); + irq_set_affinity(virq + i, &imsic->lmask); + /* + * IMSIC does not implement irq_disable() so Linux interrupt + * subsystem will take a lazy approach for disabling an IMSIC + * interrupt. This means IMSIC interrupts are left unmasked + * upon system suspend and interrupts are not processed + * immediately upon system wake up. To tackle this, we disable + * the lazy approach for all IMSIC interrupts. + */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; + +fail: + imsic_ids_free(hwirq, get_count_order(nr_irqs)); + return err; +} + +static void imsic_irq_domain_free(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + + imsic_ids_free(d->hwirq, get_count_order(nr_irqs)); + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +} + +static const struct irq_domain_ops imsic_base_domain_ops = { + .alloc = imsic_irq_domain_alloc, + .free = imsic_irq_domain_free, +}; + +static struct irq_chip imsic_plat_irq_chip = { + .name = "RISC-V IMSIC-PLAT", +}; + +static struct msi_domain_ops imsic_plat_domain_ops = { +}; + +static struct msi_domain_info imsic_plat_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .ops = &imsic_plat_domain_ops, + .chip = &imsic_plat_irq_chip, +}; + +static int __init imsic_irq_domains_init(struct fwnode_handle *fwnode) +{ + /* Create Base IRQ domain */ + imsic->base_domain = irq_domain_create_tree(fwnode, + &imsic_base_domain_ops, imsic); + if (!imsic->base_domain) { + pr_err("Failed to create IMSIC base domain\n"); + return -ENOMEM; + } + irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); + + /* Create Platform MSI domain */ + imsic->plat_domain = platform_msi_create_irq_domain(fwnode, + &imsic_plat_domain_info, + imsic->base_domain); + if (!imsic->plat_domain) { + pr_err("Failed to create IMSIC platform domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } + + return 0; +} + +/* + * To handle an interrupt, we read the TOPEI CSR and write zero in one + * instruction. If TOPEI CSR is non-zero then we translate TOPEI.ID to + * Linux interrupt number and let Linux IRQ subsystem handle it. + */ +static void imsic_handle_irq(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + irq_hw_number_t hwirq; + int err; + + chained_irq_enter(chip, desc); + + while ((hwirq = csr_swap(CSR_TOPEI, 0))) { + hwirq = hwirq >> TOPEI_ID_SHIFT; + + if (hwirq == imsic->ipi_id) { +#ifdef CONFIG_SMP + ipi_mux_process(); +#endif + continue; + } + + err = generic_handle_domain_irq(imsic->base_domain, hwirq); + if (unlikely(err)) + pr_warn_ratelimited( + "hwirq %lu mapping not found\n", hwirq); + } + + chained_irq_exit(chip, desc); +} + +static int imsic_starting_cpu(unsigned int cpu) +{ + /* Enable per-CPU parent interrupt */ + enable_percpu_irq(imsic_parent_irq, + irq_get_trigger_type(imsic_parent_irq)); + + /* Setup IPIs */ + imsic_ipi_starting_cpu(); + + /* + * Interrupts identities might have been enabled/disabled while + * this CPU was not running so sync-up local enable/disable state. + */ + imsic_ids_local_sync(); + + /* Enable local interrupt delivery */ + imsic_ids_local_delivery(true); + + return 0; +} + +static int imsic_dying_cpu(unsigned int cpu) +{ + /* Cleanup IPIs */ + imsic_ipi_dying_cpu(); + + return 0; +} + +static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, + u32 index, unsigned long *hartid) +{ + int rc; + struct fwnode_reference_args parent; + + rc = fwnode_property_get_reference_args(fwnode, + "interrupts-extended", "#interrupt-cells", + 0, index, &parent); + if (rc) + return rc; + + /* + * Skip interrupts other than external interrupts for + * current privilege level. + */ + if (parent.args[0] != RV_IRQ_EXT) + return -EINVAL; + + return riscv_fw_parent_hartid(parent.fwnode, hartid); +} + +static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, + u32 index, struct resource *res) +{ + /* + * Currently, only OF fwnode is support so extend this function + * for other types of fwnode for ACPI support. + */ + if (!is_of_node(fwnode)) + return -EINVAL; + return of_address_to_resource(to_of_node(fwnode), index, res); +} + +static int __init imsic_init(struct fwnode_handle *fwnode) +{ + int rc, cpu; + phys_addr_t base_addr; + struct irq_domain *domain; + void __iomem **mmios_va = NULL; + struct resource res, *mmios = NULL; + struct imsic_local_config *local; + struct imsic_global_config *global; + unsigned long reloff, hartid; + u32 i, j, index, nr_parent_irqs, nr_handlers = 0, num_mmios = 0; + + /* + * Only one IMSIC instance allowed in a platform for clean + * implementation of SMP IRQ affinity and per-CPU IPIs. + * + * This means on a multi-socket (or multi-die) platform we + * will have multiple MMIO regions for one IMSIC instance. + */ + if (imsic) { + pr_err("%pfwP: already initialized hence ignoring\n", + fwnode); + return -ENODEV; + } + + if (!riscv_isa_extension_available(NULL, SxAIA)) { + pr_err("%pfwP: AIA support not available\n", fwnode); + return -ENODEV; + } + + imsic = kzalloc(sizeof(*imsic), GFP_KERNEL); + if (!imsic) + return -ENOMEM; + global = &imsic->global; + + global->local = alloc_percpu(typeof(*(global->local))); + if (!global->local) { + rc = -ENOMEM; + goto out_free_priv; + } + + /* Find number of parent interrupts */ + nr_parent_irqs = 0; + while (!imsic_get_parent_hartid(fwnode, nr_parent_irqs, &hartid)) + nr_parent_irqs++; + if (!nr_parent_irqs) { + pr_err("%pfwP: no parent irqs available\n", fwnode); + rc = -EINVAL; + goto out_free_local; + } + + /* Find number of guest index bits in MSI address */ + rc = fwnode_property_read_u32_array(fwnode, "riscv,guest-index-bits", + &global->guest_index_bits, 1); + if (rc) + global->guest_index_bits = 0; + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; + if (i < global->guest_index_bits) { + pr_err("%pfwP: guest index bits too big\n", fwnode); + rc = -EINVAL; + goto out_free_local; + } + + /* Find number of HART index bits */ + rc = fwnode_property_read_u32_array(fwnode, "riscv,hart-index-bits", + &global->hart_index_bits, 1); + if (rc) { + /* Assume default value */ + global->hart_index_bits = __fls(nr_parent_irqs); + if (BIT(global->hart_index_bits) < nr_parent_irqs) + global->hart_index_bits++; + } + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - global->guest_index_bits; + if (i < global->hart_index_bits) { + pr_err("%pfwP: HART index bits too big\n", fwnode); + rc = -EINVAL; + goto out_free_local; + } + + /* Find number of group index bits */ + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-bits", + &global->group_index_bits, 1); + if (rc) + global->group_index_bits = 0; + i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - + global->guest_index_bits - global->hart_index_bits; + if (i < global->group_index_bits) { + pr_err("%pfwP: group index bits too big\n", fwnode); + rc = -EINVAL; + goto out_free_local; + } + + /* + * Find first bit position of group index. + * If not specified assumed the default APLIC-IMSIC configuration. + */ + rc = fwnode_property_read_u32_array(fwnode, "riscv,group-index-shift", + &global->group_index_shift, 1); + if (rc) + global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2; + i = global->group_index_bits + global->group_index_shift - 1; + if (i >= BITS_PER_LONG) { + pr_err("%pfwP: group index shift too big\n", fwnode); + rc = -EINVAL; + goto out_free_local; + } + + /* Find number of interrupt identities */ + rc = fwnode_property_read_u32_array(fwnode, "riscv,num-ids", + &global->nr_ids, 1); + if (rc) { + pr_err("%pfwP: number of interrupt identities not found\n", + fwnode); + goto out_free_local; + } + if ((global->nr_ids < IMSIC_MIN_ID) || + (global->nr_ids >= IMSIC_MAX_ID) || + ((global->nr_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { + pr_err("%pfwP: invalid number of interrupt identities\n", + fwnode); + rc = -EINVAL; + goto out_free_local; + } + + /* Find number of guest interrupt identities */ + if (fwnode_property_read_u32_array(fwnode, "riscv,num-guest-ids", + &global->nr_guest_ids, 1)) + global->nr_guest_ids = global->nr_ids; + if ((global->nr_guest_ids < IMSIC_MIN_ID) || + (global->nr_guest_ids >= IMSIC_MAX_ID) || + ((global->nr_guest_ids & IMSIC_MIN_ID) != IMSIC_MIN_ID)) { + pr_err("%pfwP: invalid number of guest interrupt identities\n", + fwnode); + rc = -EINVAL; + goto out_free_local; + } + + /* Compute base address */ + rc = imsic_get_mmio_resource(fwnode, 0, &res); + if (rc) { + pr_err("%pfwP: first MMIO resource not found\n", fwnode); + rc = -EINVAL; + goto out_free_local; + } + global->base_addr = res.start; + global->base_addr &= ~(BIT(global->guest_index_bits + + global->hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT) - 1); + global->base_addr &= ~((BIT(global->group_index_bits) - 1) << + global->group_index_shift); + + /* Find number of MMIO register sets */ + while (!imsic_get_mmio_resource(fwnode, num_mmios, &res)) + num_mmios++; + + /* Allocate MMIO resource array */ + mmios = kcalloc(num_mmios, sizeof(*mmios), GFP_KERNEL); + if (!mmios) { + rc = -ENOMEM; + goto out_free_local; + } + + /* Allocate MMIO virtual address array */ + mmios_va = kcalloc(num_mmios, sizeof(*mmios_va), GFP_KERNEL); + if (!mmios_va) { + rc = -ENOMEM; + goto out_iounmap; + } + + /* Parse and map MMIO register sets */ + for (i = 0; i < num_mmios; i++) { + rc = imsic_get_mmio_resource(fwnode, i, &mmios[i]); + if (rc) { + pr_err("%pfwP: unable to parse MMIO regset %d\n", + fwnode, i); + goto out_iounmap; + } + + base_addr = mmios[i].start; + base_addr &= ~(BIT(global->guest_index_bits + + global->hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT) - 1); + base_addr &= ~((BIT(global->group_index_bits) - 1) << + global->group_index_shift); + if (base_addr != global->base_addr) { + rc = -EINVAL; + pr_err("%pfwP: address mismatch for regset %d\n", + fwnode, i); + goto out_iounmap; + } + + mmios_va[i] = ioremap(mmios[i].start, resource_size(&mmios[i])); + if (!mmios_va[i]) { + rc = -EIO; + pr_err("%pfwP: unable to map MMIO regset %d\n", + fwnode, i); + goto out_iounmap; + } + } + + /* Initialize interrupt identity management */ + rc = imsic_ids_init(); + if (rc) { + pr_err("%pfwP: failed to initialize interrupt management\n", + fwnode); + goto out_iounmap; + } + + /* Configure handlers for target CPUs */ + for (i = 0; i < nr_parent_irqs; i++) { + rc = imsic_get_parent_hartid(fwnode, i, &hartid); + if (rc) { + pr_warn("%pfwP: hart ID for parent irq%d not found\n", + fwnode, i); + continue; + } + + cpu = riscv_hartid_to_cpuid(hartid); + if (cpu < 0) { + pr_warn("%pfwP: invalid cpuid for parent irq%d\n", + fwnode, i); + continue; + } + + /* Find MMIO location of MSI page */ + index = num_mmios; + reloff = i * BIT(global->guest_index_bits) * + IMSIC_MMIO_PAGE_SZ; + for (j = 0; num_mmios; j++) { + if (reloff < resource_size(&mmios[j])) { + index = j; + break; + } + + /* + * MMIO region size may not be aligned to + * BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ + * if holes are present. + */ + reloff -= ALIGN(resource_size(&mmios[j]), + BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ); + } + if (index >= num_mmios) { + pr_warn("%pfwP: MMIO not found for parent irq%d\n", + fwnode, i); + continue; + } + + cpumask_set_cpu(cpu, &imsic->lmask); + + local = per_cpu_ptr(global->local, cpu); + local->msi_pa = mmios[index].start + reloff; + local->msi_va = mmios_va[index] + reloff; + + nr_handlers++; + } + + /* If no CPU handlers found then can't take interrupts */ + if (!nr_handlers) { + pr_err("%pfwP: No CPU handlers found\n", fwnode); + rc = -ENODEV; + goto out_ids_cleanup; + } + + /* Find parent domain and register chained handler */ + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!domain) { + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); + rc = -ENOENT; + goto out_ids_cleanup; + } + imsic_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); + if (!imsic_parent_irq) { + pr_err("%pfwP: Failed to create INTC mapping\n", fwnode); + rc = -ENOENT; + goto out_ids_cleanup; + } + irq_set_chained_handler(imsic_parent_irq, imsic_handle_irq); + + /* Initialize IPI domain */ + rc = imsic_ipi_domain_init(); + if (rc) { + pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode); + goto out_ids_cleanup; + } + + /* Initialize IRQ and MSI domains */ + rc = imsic_irq_domains_init(fwnode); + if (rc) { + pr_err("%pfwP: Failed to initialize IRQ and MSI domains\n", + fwnode); + goto out_ipi_domain_cleanup; + } + + /* + * Setup cpuhp state (must be done after setting imsic_parent_irq) + * + * Don't disable per-CPU IMSIC file when CPU goes offline + * because this affects IPI and the masking/unmasking of + * virtual IPIs is done via generic IPI-Mux + */ + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "irqchip/riscv/imsic:starting", + imsic_starting_cpu, imsic_dying_cpu); + + /* We don't need MMIO arrays anymore so let's free-up */ + kfree(mmios_va); + kfree(mmios); + + pr_info("%pfwP: hart-index-bits: %d, guest-index-bits: %d\n", + fwnode, global->hart_index_bits, global->guest_index_bits); + pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n", + fwnode, global->group_index_bits, global->group_index_shift); + pr_info("%pfwP: mapped %d interrupts for %d CPUs at %pa\n", + fwnode, global->nr_ids, nr_handlers, &global->base_addr); + if (imsic->ipi_id) + pr_info("%pfwP: providing IPIs using interrupt %d\n", + fwnode, imsic->ipi_id); + + return 0; + +out_ipi_domain_cleanup: + imsic_ipi_domain_cleanup(); +out_ids_cleanup: + imsic_ids_cleanup(); +out_iounmap: + for (i = 0; i < num_mmios; i++) { + if (mmios_va[i]) + iounmap(mmios_va[i]); + } + kfree(mmios_va); + kfree(mmios); +out_free_local: + free_percpu(imsic->global.local); +out_free_priv: + kfree(imsic); + imsic = NULL; + return rc; +} + +static int __init imsic_dt_init(struct device_node *node, + struct device_node *parent) +{ + return imsic_init(&node->fwnode); +} +IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_dt_init); diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h new file mode 100644 index 000000000000..1f6fc9a57218 --- /dev/null +++ b/include/linux/irqchip/riscv-imsic.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ +#ifndef __LINUX_IRQCHIP_RISCV_IMSIC_H +#define __LINUX_IRQCHIP_RISCV_IMSIC_H + +#include +#include + +#define IMSIC_MMIO_PAGE_SHIFT 12 +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) +#define IMSIC_MMIO_PAGE_LE 0x00 +#define IMSIC_MMIO_PAGE_BE 0x04 + +#define IMSIC_MIN_ID 63 +#define IMSIC_MAX_ID 2048 + +#define IMSIC_EIDELIVERY 0x70 + +#define IMSIC_EITHRESHOLD 0x72 + +#define IMSIC_EIP0 0x80 +#define IMSIC_EIP63 0xbf +#define IMSIC_EIPx_BITS 32 + +#define IMSIC_EIE0 0xc0 +#define IMSIC_EIE63 0xff +#define IMSIC_EIEx_BITS 32 + +#define IMSIC_FIRST IMSIC_EIDELIVERY +#define IMSIC_LAST IMSIC_EIE63 + +#define IMSIC_MMIO_SETIPNUM_LE 0x00 +#define IMSIC_MMIO_SETIPNUM_BE 0x04 + +struct imsic_local_config { + phys_addr_t msi_pa; + void __iomem *msi_va; +}; + +struct imsic_global_config { + /* + * MSI Target Address Scheme + * + * XLEN-1 12 0 + * | | | + * ------------------------------------------------------------- + * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | + * ------------------------------------------------------------- + */ + + /* Bits representing Guest index, HART index, and Group index */ + u32 guest_index_bits; + u32 hart_index_bits; + u32 group_index_bits; + u32 group_index_shift; + + /* Global base address matching all target MSI addresses */ + phys_addr_t base_addr; + + /* Number of interrupt identities */ + u32 nr_ids; + + /* Number of guest interrupt identities */ + u32 nr_guest_ids; + + /* Per-CPU IMSIC addresses */ + struct imsic_local_config __percpu *local; +}; + +#ifdef CONFIG_RISCV_IMSIC + +extern const struct imsic_global_config *imsic_get_global_config(void); + +#else + +static inline const struct imsic_global_config *imsic_get_global_config(void) +{ + return NULL; +} + +#endif + +#endif From patchwork Mon May 8 14:28:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91180 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2202910vqo; Mon, 8 May 2023 07:33:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7FYUvGD/to69UnQP7vj6gfzYPQNFJjOjrnsI9ch+YC3mP24vaWM7E31S0elwspDGNSl1Ry X-Received: by 2002:a05:6a20:1444:b0:f0:827f:4aff with SMTP id a4-20020a056a20144400b000f0827f4affmr13007573pzi.0.1683556431655; Mon, 08 May 2023 07:33:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683556431; cv=none; d=google.com; s=arc-20160816; b=pFnE3gmYqJ29iST72QZswC3f855PgKkB0+EH1SfPpvgOYtniGBAYnRKtqAxSgdRkfi dfYTxl8X0DkAR215HqwnVMZd00BazWC4FsoOBoEyg/1w5BsSrLMMeNyyCM4Gnwaf3F/I 17hY2liHv56YNqF08TQH/zPik5xZaLr17xj8ki135peXggImIk/ogvn9BW45v79x40Tj zw2j26FQO+VaSWUx8Vvc4cNnEXbFk9LddBOQ65sZj/sWHkPHjIaLB0JaXgR+ytCGaw7u Sbarkb6FcTK0hHwUWMpZ0aMM1lVELyLGo1qDg4KEW9MVfxeZlXCIKHnlbbT67ONwO3DP QdXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WZx8pVyFJqTIpr4BnDr/88VmIIeD0a98LNl1bXs4aCI=; b=ZJR7+ocH6RVYqhqH3O2FNqPy0HedPqFwfxkjNJoRQEGbkwfw/NTRKNfRbOkGQDyr9M 2YwM6hvtyNvfN+1Y6kiMeEEExH1eWp8oOqwkyzGXmbaZ3PQn3zTStVunmWhTtLVUZjUJ ftPqBRNrsN7WwN6XDB++CER3tBX2QfAQP1NtASc4p0lUwIvz5kdqxM0Dt67zRMs0Nipu FX24SGNxLQDbtfdQWSLyfKZYjeEtJ63+skx/gcJZtAvH1pOc/DV4pnHEGapKTe/DnVMp hSdNdO8Ar5oCwkkJhbjPqczR6Incz26UNsfV1goTjuR+6D2TKqwZe+uO6rf7EpabjdbI G62Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=dTnj8jF9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 77-20020a621850000000b0063d2b810fcbsi45343pfy.208.2023.05.08.07.33.35; Mon, 08 May 2023 07:33:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=dTnj8jF9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234899AbjEHOaL (ORCPT + 99 others); Mon, 8 May 2023 10:30:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234901AbjEHO3x (ORCPT ); Mon, 8 May 2023 10:29:53 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03BDDAD24 for ; Mon, 8 May 2023 07:29:30 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-643990c5319so3055802b3a.2 for ; Mon, 08 May 2023 07:29:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556169; x=1686148169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WZx8pVyFJqTIpr4BnDr/88VmIIeD0a98LNl1bXs4aCI=; b=dTnj8jF9WIu+jQo5yru3eJjRqiAEHZBZJ/aJ7cgeYj1zF9lv1xflSCfcl+LSKqGaIV jfZ1+t1HwtTt4GwgZN4XIOqbWYNhXDuQf/JKZTk9qPDhdLmaU8lezhkQeblu/H1yu1E1 Cv1IzlK841t90PK+K6bgn9E61JdlrFKX+7uMjSs2uLq/7V3lN2WDOAc3v3Pzwoyzqp7f QnN2moOnjD+ijPu/4+Rjz6CoJ+FC/Gg6vZ2w9ps1LXA1H50BzOFIWUUp2TeV+G3C3cjD w+2EcfAuNkf2HweC4ChcYrYIR7rD9bHgJBlMPvEf31IwarO+gcTz/fKSUPbeyqTAuUBL 2ttA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556169; x=1686148169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WZx8pVyFJqTIpr4BnDr/88VmIIeD0a98LNl1bXs4aCI=; b=i+v2YI76XN38X+gekZTiQYoxYx46RvOL9+95uKAIv3cR92kyrvp9DEBctaxSqIUgVu tE1RKQRYaaHZTGtTmLx7yr0YIAGMZu9laQ2/Ssr7m8ZcB3oGWBvAnOjP1hvfV6tWm9zE 3ZxiGVWo8B+xFgmBbXB6bEem0ECA0jeTEh+pYqG4SBYS5JoqFHk24paLebG3YxYOSKeX xGwPj/vZmQAtPQB8HCf8KXo2Ol3cqCmyV2rTfQ1gyqjnvqFPdlNeadIFHpqHacRjVUc4 XEUj43Lv/cbt/HWVUB28DbRhEAy6qI1cT2NRxgkUXWak76qkqhhAWnfJigiu723zjQfz j6nw== X-Gm-Message-State: AC+VfDzEeautvhh7SL5hjmlGjYg0f9QU+OEIh7v3Utf4eeMuwOhOMRUR 8n7l12zSB9yZZfzpHbTQUk99kA== X-Received: by 2002:a05:6a21:339c:b0:100:2c5c:8e69 with SMTP id yy28-20020a056a21339c00b001002c5c8e69mr5992538pzb.49.1683556168895; Mon, 08 May 2023 07:29:28 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:28 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 06/11] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Date: Mon, 8 May 2023 19:58:37 +0530 Message-Id: <20230508142842.854564-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765336868788579884?= X-GMAIL-MSGID: =?utf-8?q?1765336868788579884?= The Linux PCI framework requires it's own dedicated MSI irqdomain so let us create PCI MSI irqdomain as child of the IMSIC base irqdomain. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 +++++ drivers/irqchip/irq-riscv-imsic.c | 49 +++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 8ef18be5f37b..d700980372ef 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -550,6 +550,13 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ +config RISCV_IMSIC_PCI + bool + depends on RISCV_IMSIC + depends on PCI + depends on PCI_MSI + default RISCV_IMSIC + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c index 971fad638c9f..30247c84a6b0 100644 --- a/drivers/irqchip/irq-riscv-imsic.c +++ b/drivers/irqchip/irq-riscv-imsic.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -81,6 +82,7 @@ struct imsic_priv { /* IRQ domains */ struct irq_domain *base_domain; + struct irq_domain *pci_domain; struct irq_domain *plat_domain; }; @@ -547,6 +549,39 @@ static const struct irq_domain_ops imsic_base_domain_ops = { .free = imsic_irq_domain_free, }; +#ifdef CONFIG_RISCV_IMSIC_PCI + +static void imsic_pci_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void imsic_pci_unmask_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip imsic_pci_irq_chip = { + .name = "RISC-V IMSIC-PCI", + .irq_mask = imsic_pci_mask_irq, + .irq_unmask = imsic_pci_unmask_irq, + .irq_eoi = irq_chip_eoi_parent, +}; + +static struct msi_domain_ops imsic_pci_domain_ops = { +}; + +static struct msi_domain_info imsic_pci_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), + .ops = &imsic_pci_domain_ops, + .chip = &imsic_pci_irq_chip, +}; + +#endif + static struct irq_chip imsic_plat_irq_chip = { .name = "RISC-V IMSIC-PLAT", }; @@ -571,12 +606,26 @@ static int __init imsic_irq_domains_init(struct fwnode_handle *fwnode) } irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); +#ifdef CONFIG_RISCV_IMSIC_PCI + /* Create PCI MSI domain */ + imsic->pci_domain = pci_msi_create_irq_domain(fwnode, + &imsic_pci_domain_info, + imsic->base_domain); + if (!imsic->pci_domain) { + pr_err("Failed to create IMSIC PCI domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } +#endif + /* Create Platform MSI domain */ imsic->plat_domain = platform_msi_create_irq_domain(fwnode, &imsic_plat_domain_info, imsic->base_domain); if (!imsic->plat_domain) { pr_err("Failed to create IMSIC platform domain\n"); + if (imsic->pci_domain) + irq_domain_remove(imsic->pci_domain); irq_domain_remove(imsic->base_domain); return -ENOMEM; } From patchwork Mon May 8 14:28:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91191 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2210139vqo; Mon, 8 May 2023 07:45:43 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6LT/ubP5SXbNaoByeCOo5+cdLKqLyRVbzY22yTbwThTAGBSy2qJBGUNsKjOWzVaobOXVKO X-Received: by 2002:a05:6a00:ac2:b0:63d:2f13:200 with SMTP id c2-20020a056a000ac200b0063d2f130200mr16173356pfl.16.1683557143237; Mon, 08 May 2023 07:45:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683557143; cv=none; d=google.com; s=arc-20160816; b=q2mmSTYutX2l+93Fs8OX1NW2acjqXmDlPi5UYSSosoVOz0u/3o3+t4wFA6BH3Umv49 h1qbwdlvBDtduVfe87vL68iC7lWIOzcX23dRpb07Wr07m2YGgPGIbeW1wlG4a81v/P0N K1uHOB+L8ivq/PoTT0Ckz19h4AAC3DhCjH5QyoDDPkeghFIEzXvKXMGgjQiqpCV6+SfU +RfI0EyhumrBUzEtReaQB45+NCJxLXe/yQsK5/lnuMbpNlFYsvsDsmq3ZzbPjI5+FWNp VVjKvxVg1lFH6lj/h9Fv+kr/cLNf/Pzv9Dd+FnGKkoKV9WV9REFqsiCOPbaV4kBJcDf5 myCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2E+vPnkV/6+u4KNq32vBTTiL8TGRt65LegkILCc8n2k=; b=DCXYZPWKBwf0nJ6kq7dVBDBNbzR2j51AL2t6aEuBc58ddRThj9QPZq0ll3DcKi8m5b 2G6H6AxAc57eqvbNhRj49q6qOwQ5CVkZSaCA0MBhF/9nkQLC91TanKeezZq5wElz/WGc FRE0hCT9x9M69k3i+YPUNgrdqlJaMvWaKQlJB8RoWcukMBfZBuMxsbchduU1REzQPyEK bqCkMY4mykcx4yuOa6Rs7KDsCYqa8G0lbwtcGgcwer0mZ9sfdlNk4PraUw2UZOX11caf EMUd8GT324K6vsP4VUMdVsUrrUe7/27q1RiBv2Md4WjIoUnfsrHSzub/fVVUQ3h/5mNT ACiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=KT3ZEhjc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h65-20020a625344000000b00638f2eb16f9si16640pfb.343.2023.05.08.07.45.28; Mon, 08 May 2023 07:45:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=KT3ZEhjc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235197AbjEHOaZ (ORCPT + 99 others); Mon, 8 May 2023 10:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234591AbjEHO35 (ORCPT ); Mon, 8 May 2023 10:29:57 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1137C2120 for ; Mon, 8 May 2023 07:29:35 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-64384274895so3208671b3a.2 for ; Mon, 08 May 2023 07:29:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556174; x=1686148174; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2E+vPnkV/6+u4KNq32vBTTiL8TGRt65LegkILCc8n2k=; b=KT3ZEhjc9ES8ZVsBr2ikNMw73wtSWzh4Z47d8zPtu1lgyPuFMqA7VwwV9vGZ5SW37y MBSQZQzUOXlqyAH/WPlhJEruUeA6vRH09JsKCeJloRHHdGN+44VRCKznMVlqb6dAACEX rY4QqvEig87kN7V+kDf9uNihu9VwP08GNpbHcAv0sxuZ3WEs8RWfd34N6igOBg/yTMoe 7GNzMzfOxpE93Y/1poLdOn9sU0wwciXW+YTUPjnu+jExlWcVkXq8tQ5iwF61Ewdy1p/y 7+yJleoMtrVZAc9UDgmKmrkwOMZww8DaLoH7t7SGqTiSON85DurBae5XHh9Q+JFPQp27 qWBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556174; x=1686148174; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2E+vPnkV/6+u4KNq32vBTTiL8TGRt65LegkILCc8n2k=; b=I4GLUBDVHKb4xqQ6jx1G9nctMZGsWdJTPdQJWA/E/spfqes1+hggqFegSqZSHvt+iK m/C2eCaE4PU7IXkoUqCNK6WDm3TR/KKpwPtb+C0DmaEoaxIK1lfOz2WaQ6OxPFIWre7w /4cQPCqDxUexB4e3hVaq3b4DvHYf9bWJu2KobZCxKwDngXjU4LNznru6L5WmnieDgXcO QiaIs9IvJNkAKIoAHYnGL+10mIUX56uCxC8zPM+OwvPYUjNy+4nXVRRbpiB+Y3meCVcn 2ZfbJdhdx/JMEFUUz0qF3BughRXXK6lIQiqpjoZIKA+sJf3BqJMW0zAWtd/kBp37g5Iy feVw== X-Gm-Message-State: AC+VfDxyeEdZJkGr693iXgQsTWzQyc6GTG9FjQqIqUdAShIoxozPH6Ly 6/bxnS6yO7mIqDW7NwAAYqbuHg== X-Received: by 2002:a05:6a00:b8a:b0:646:663a:9d60 with SMTP id g10-20020a056a000b8a00b00646663a9d60mr2974528pfj.10.1683556174393; Mon, 08 May 2023 07:29:34 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:34 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel , Vincent Chen Subject: [PATCH v3 07/11] irqchip/riscv-imsic: Improve IOMMU DMA support Date: Mon, 8 May 2023 19:58:38 +0530 Message-Id: <20230508142842.854564-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765337615205928312?= X-GMAIL-MSGID: =?utf-8?q?1765337615205928312?= We have a separate RISC-V IMSIC MSI address for each CPU so changing MSI (or IRQ) affinity results in re-programming of MSI address in the PCIe (or platform) device. Currently, the iommu_dma_prepare_msi() is called only once at the time of IRQ allocation so IOMMU DMA domain will only have mapping for one MSI page. This means iommu_dma_compose_msi_msg() called by imsic_irq_compose_msi_msg() will always use the same MSI page irrespective to target CPU MSI address. In other words, changing MSI (or IRQ) affinity for device using IOMMU DMA domain will not work. To address above issue, we do the following: 1) Map MSI pages for all CPUs in imsic_irq_domain_alloc() using iommu_dma_prepare_msi(). 2) Add a new iommu_dma_select_msi() API to select a specific MSI page from a set of already mapped MSI pages. 3) Use iommu_dma_select_msi() to select a specific MSI page before calling iommu_dma_compose_msi_msg() in imsic_irq_compose_msi_msg(). Reported-by: Vincent Chen Signed-off-by: Anup Patel --- drivers/iommu/dma-iommu.c | 38 +++++++++++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic.c | 27 ++++++++++++---------- include/linux/iommu.h | 6 +++++ 3 files changed, 59 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 7a9f0b0bddbd..07782c77a6eb 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -1677,6 +1677,44 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) return 0; } +/** + * iommu_dma_select_msi() - Select a MSI page from a set of + * already mapped MSI pages in the IOMMU domain. + * + * @desc: MSI descriptor prepared by iommu_dma_prepare_msi() + * @msi_addr: physical address of the MSI page to be selected + * + * Return: 0 on success or negative error code if the select failed. + */ +int iommu_dma_select_msi(struct msi_desc *desc, phys_addr_t msi_addr) +{ + struct device *dev = msi_desc_to_dev(desc); + struct iommu_domain *domain = iommu_get_domain_for_dev(dev); + const struct iommu_dma_msi_page *msi_page; + struct iommu_dma_cookie *cookie; + + if (!domain || !domain->iova_cookie) { + desc->iommu_cookie = NULL; + return 0; + } + + cookie = domain->iova_cookie; + msi_addr &= ~(phys_addr_t)(cookie_msi_granule(cookie) - 1); + + msi_page = msi_desc_get_iommu_cookie(desc); + if (msi_page && msi_page->phys == msi_addr) + return 0; + + list_for_each_entry(msi_page, &cookie->msi_page_list, list) { + if (msi_page->phys == msi_addr) { + msi_desc_set_iommu_cookie(desc, msi_page); + return 0; + } + } + + return -ENOENT; +} + /** * iommu_dma_compose_msi_msg() - Apply translation to an MSI message * @desc: MSI descriptor prepared by iommu_dma_prepare_msi() diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c index 30247c84a6b0..ec61c599e0c5 100644 --- a/drivers/irqchip/irq-riscv-imsic.c +++ b/drivers/irqchip/irq-riscv-imsic.c @@ -446,6 +446,10 @@ static void imsic_irq_compose_msi_msg(struct irq_data *d, if (WARN_ON(err)) return; + err = iommu_dma_select_msi(desc, msi_addr); + if (WARN_ON(err)) + return; + msg->address_hi = upper_32_bits(msi_addr); msg->address_lo = lower_32_bits(msi_addr); msg->data = d->hwirq; @@ -493,11 +497,18 @@ static int imsic_irq_domain_alloc(struct irq_domain *domain, int i, hwirq, err = 0; unsigned int cpu; - err = imsic_get_cpu(&imsic->lmask, false, &cpu); - if (err) - return err; + /* Map MSI address of all CPUs */ + for_each_cpu(cpu, &imsic->lmask) { + err = imsic_cpu_page_phys(cpu, 0, &msi_addr); + if (err) + return err; - err = imsic_cpu_page_phys(cpu, 0, &msi_addr); + err = iommu_dma_prepare_msi(info->desc, msi_addr); + if (err) + return err; + } + + err = imsic_get_cpu(&imsic->lmask, false, &cpu); if (err) return err; @@ -505,10 +516,6 @@ static int imsic_irq_domain_alloc(struct irq_domain *domain, if (hwirq < 0) return hwirq; - err = iommu_dma_prepare_msi(info->desc, msi_addr); - if (err) - goto fail; - for (i = 0; i < nr_irqs; i++) { imsic_id_set_target(hwirq + i, cpu); irq_domain_set_info(domain, virq + i, hwirq + i, @@ -528,10 +535,6 @@ static int imsic_irq_domain_alloc(struct irq_domain *domain, } return 0; - -fail: - imsic_ids_free(hwirq, get_count_order(nr_irqs)); - return err; } static void imsic_irq_domain_free(struct irq_domain *domain, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index e8c9a7da1060..41e8613832ab 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1117,6 +1117,7 @@ void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit); int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base); int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr); +int iommu_dma_select_msi(struct msi_desc *desc, phys_addr_t msi_addr); void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg); #else /* CONFIG_IOMMU_DMA */ @@ -1138,6 +1139,11 @@ static inline int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_a return 0; } +static inline int iommu_dma_select_msi(struct msi_desc *desc, phys_addr_t msi_addr) +{ + return 0; +} + static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg) { } From patchwork Mon May 8 14:28:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91188 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2209361vqo; Mon, 8 May 2023 07:44:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ63+PBwGHztkh7Au4Bf2x7mhxNAgJliuYLzW9xbHt6teAn+vAANVtic82gyEBGNJ3xCLp/A X-Received: by 2002:a05:6a21:3a43:b0:f6:55c:5371 with SMTP id zu3-20020a056a213a4300b000f6055c5371mr11095003pzb.49.1683557063120; Mon, 08 May 2023 07:44:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683557063; cv=none; d=google.com; s=arc-20160816; b=JKI43TjEtP4XcDfkcZ8ZyVpnYR/EU9BVzLj4tlGm2HCU63yg1qjSAXuze9+xKzpU4p eyc+GF6fvGj28Q+kPCoIYcfxdZFfyrHRgbyJXi7yXOWrYOfJmoE6ejsbmmRnLpcY3VYL 4Zxpg7vEIt7/0YEiQihXiFksObmHOnNKyDhmliWPUnsho3wlnG2gwdgj1kbSqyCTaTXk hYMmA2YGH6ysD02SAKdmT772lPVu28tXFl4COcQdwF5OmfeYWU7RWpvAkYqScW3ocX7g Ov4Mu3Mw+gFAkPLpoSwF1iK5tsRHhRJFEuFEtg/UnGFahg3XJjU6Ekw6d3b+UbqRkpoY zqfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gulDdhHMZRSrLXU3iHwqBSdOOAUh5cBhxAXZTyp6yp4=; b=fo7sn18n51a4iekZ7oiqMCD9njvCWT42EG69mEEk5bU2rqkvBCfyRuRsUZkzE5DzcH NmftGHFM7Hfvp4pVqNoyXlzO7DqXZX+p0Fn/FJ3zJT6tEDBFabdPRHGyVKGahfojTpfu wXr3dVH9vdutx9t5/gWLldBQ01U5U6qZXvSuVAaV4eVMp9YWRx4v0tugpXynjOP2dUb8 t+WY2hzVNLqVOJ4GZwUqmPe4mVe4B48GBCLgviS1os9G6wFUHB4myPzlgiL1jLJeDGDe YTzmhqTh9WwgQKybO12EQmS8ZZOE08KGJF+1NVn1uT8w5aBOgGIQNToicqVvzgJW+DXm XDTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=GzUgbjK2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l189-20020a6388c6000000b0053028c15ad1si1182496pgd.97.2023.05.08.07.44.08; Mon, 08 May 2023 07:44:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=GzUgbjK2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234654AbjEHOa3 (ORCPT + 99 others); Mon, 8 May 2023 10:30:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234623AbjEHO37 (ORCPT ); Mon, 8 May 2023 10:29:59 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C470F65AC for ; Mon, 8 May 2023 07:29:39 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6439b410679so2651596b3a.0 for ; Mon, 08 May 2023 07:29:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556179; x=1686148179; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gulDdhHMZRSrLXU3iHwqBSdOOAUh5cBhxAXZTyp6yp4=; b=GzUgbjK2FUWi8gDMJBV0XJUciYOiIyt5d9RrZk+TfhgBZoDqKJc1FznkgqIk7ptZTS aWa0mTmryvNxQ7tlRkfXhyruNQaL+4KamL+M1isNxAAN2yZ4DZbIJex5oHoKifz/MVmI O10tPe31ve+KgIR8T2C3S27/3Bv+igVxvfOlSu924IFlg0I50x4MRJYWDsQA50zjwnsW 7NX0G4KrLMfAiBGr+UH8xsQ5bYzVRbdhrkTpRINqXUbO7U8c6QKe/H/FntNkOZKO+Gp4 r/hY3d2o1UblKsNdsqjdp897n519YAp1cznFj1bpNA9jqT9ZpmdtECPwIIORcCHtD6LV xijQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556179; x=1686148179; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gulDdhHMZRSrLXU3iHwqBSdOOAUh5cBhxAXZTyp6yp4=; b=OyWthrc/bgkbL6JoSQ6Zd0gW5kTPXZC0WfYqgimZ8sCP4J+biy5RH964LxLLL2GkQv Fc+gIorS4jDbppORY/gYlwt7kX4hz3/Zhx1UkV6TwybcnQAdwDBNYnQRuxlGDwZMgeFF ci5ZI0tTtBYdAm7xPY/cQlnCi4NhPdSqm0vxPNBK6e8r0XV7/vN8w+B4HklCGksebN/A ybMtJirQFg3YzRltgq8maCVAdhxLI/PKv7VUVWRXWZOFxI54BUk34IH1Nu7BRHIPg8q4 nH7Vej1Dv2mGYLf1kZTxyfw6KPLvBV2NcwEAb31ATZYV1Z2U8EMOrteeoDkeq60Dwx8+ HIyw== X-Gm-Message-State: AC+VfDwY03MLMRJALPQPJ9OCkU5aJiQQdmH4+oLdVmw4ntuij+z4H1zi tYNSHssDqB38wVygr81LnXideQ== X-Received: by 2002:a05:6a00:cc8:b0:644:d220:64ac with SMTP id b8-20020a056a000cc800b00644d22064acmr8720065pfv.2.1683556179130; Mon, 08 May 2023 07:29:39 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:38 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 08/11] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Date: Mon, 8 May 2023 19:58:39 +0530 Message-Id: <20230508142842.854564-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765337530650626862?= X-GMAIL-MSGID: =?utf-8?q?1765337530650626862?= We add DT bindings document for RISC-V advanced platform level interrupt controller (APLIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel --- .../interrupt-controller/riscv,aplic.yaml | 162 ++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml new file mode 100644 index 000000000000..b47a7987b774 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Advanced Platform Level Interrupt Controller (APLIC) + +maintainers: + - Anup Patel + +description: + The RISC-V advanced interrupt architecture (AIA) defines an advanced + platform level interrupt controller (APLIC) for handling wired interrupts + in a RISC-V platform. The RISC-V AIA specification can be found at + https://github.com/riscv/riscv-aia. + + The RISC-V APLIC is implemented as hierarchical APLIC domains where all + interrupt sources connect to the root domain which can further delegate + interrupts to child domains. There is one device tree node for each APLIC + domain. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,aplic + - const: riscv,aplic + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + Given APLIC domain directly injects external interrupts to a set of + RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc + node, which has a riscv node (i.e. RISC-V HART) as parent. + + msi-parent: + description: + Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming + message signaled interrupt controller (IMSIC). If both "msi-parent" and + "interrupts-extended" properties are present then it means the APLIC + domain supports both MSI mode and Direct mode in HW. In this case, the + APLIC driver has to choose between MSI mode or Direct mode. + + riscv,num-sources: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 1023 + description: + Specifies the number of wired interrupt sources supported by this + APLIC domain. + + riscv,children: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + maxItems: 1 + description: + A list of child APLIC domains for the given APLIC domain. Each child + APLIC domain is assigned a child index in increasing order, with the + first child APLIC domain assigned child index 0. The APLIC domain child + index is used by firmware to delegate interrupts from the given APLIC + domain to a particular child APLIC domain. + + riscv,delegate: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + items: + - description: child APLIC domain phandle + - description: first interrupt number of this APLIC domain (inclusive) + - description: last interrupt number of this APLIC domain (inclusive) + description: + A interrupt delegation list where each entry is a triple consisting of + child APLIC domain phandle, first interrupt number of this APLIC domain, + and last interrupt number of this APLIC domain. Firmware must configure + interrupt delegation registers based on interrupt delegation list. + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - riscv,num-sources + +unevaluatedProperties: false + +examples: + - | + // Example 1 (APLIC domains directly injecting interrupt to HARTs): + + interrupt-controller@c000000 { + compatible = "qemu,aplic", "riscv,aplic"; + interrupts-extended = <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg = <0xc000000 0x4080>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + riscv,children = <&aplic1>, <&aplic2>; + riscv,delegate = <&aplic1 1 63>; + }; + + aplic1: interrupt-controller@d000000 { + compatible = "qemu,aplic", "riscv,aplic"; + interrupts-extended = <&cpu1_intc 9>, + <&cpu2_intc 9>; + reg = <0xd000000 0x4080>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + }; + + aplic2: interrupt-controller@e000000 { + compatible = "qemu,aplic", "riscv,aplic"; + interrupts-extended = <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg = <0xe000000 0x4080>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + }; + + - | + // Example 2 (APLIC domains forwarding interrupts as MSIs): + + interrupt-controller@c000000 { + compatible = "qemu,aplic", "riscv,aplic"; + msi-parent = <&imsic_mlevel>; + reg = <0xc000000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + riscv,children = <&aplic3>; + riscv,delegate = <&aplic3 1 63>; + }; + + aplic3: interrupt-controller@d000000 { + compatible = "qemu,aplic", "riscv,aplic"; + msi-parent = <&imsic_slevel>; + reg = <0xd000000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + }; +... From patchwork Mon May 8 14:28:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91178 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2202572vqo; Mon, 8 May 2023 07:33:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5K2ArSn4/HZ83p+QuslE9L3jVfcC64ydzTLNWq8tn/B5wbTIVG/UguYu21mijczSwk8MQc X-Received: by 2002:a17:902:c94b:b0:1ab:14f2:e7e6 with SMTP id i11-20020a170902c94b00b001ab14f2e7e6mr12500038pla.65.1683556401691; Mon, 08 May 2023 07:33:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683556401; cv=none; d=google.com; s=arc-20160816; b=QNvnk9fUN3gFergJQOrmIKvQZbXhxCh0IvMknelRGAAwg3AaE+hByA8DcbfqjBYYUF UigSbhHVz40V9vqFF4rr3YyeSgJjq/I48BEm6MRSqYJPY7j6wrkkR5No9lM/+1kQE4+Y 9i+SZcErIp3TgJnP9eQGBfPydfmBhE6yxA0Pw0L/BaEA+1XIHMyQrgc3PfarzXNCwQMT iS9hs0Vd2ZFM0Dkh4a7GSXhCoJLWNh8fKzos+4FA8C8tn/gI7JWBL8i0KwAVRlp89H6a nCis699otDIT3MebgTOqigTNXE5hZDi3+U6Q1kxN5WB5fOsa80/gGbEybJlRuU25dQK7 Yo7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hmnZIR+PkD3LCkRKYUkeh0Lq9PqKZdSPpnDL/aaklyI=; b=vZmghwf4WmadBx8VjM4eaC65acC70+c+OT1rCnsU+Wi4tV/KvhAhw6dgAVcOk3E+Jq XzRIC+kK0RRN24oLBV0c3eh081PXl4Pr4zxB2DQNLuxsckcDACk28cn5ty9kwwds8T0Z TclkOpP3xrjql12YUA1mZYLdcVQX4la9rVNXCx+ugWv6HAlz1rPwaXABnyp81VNRVagN b5HF5i3SFkO57ZQwl4HU05K0xT61nyeWkkHeYee5yM27m/u/JLAhLZn0L75vevoqYo3u cRxTGOLT8OToumIVQQwXr2fnob9f5y8WbaRRlbf+iqT8pBhrTt1DU0Hs7i/fY4/XSSKL EdVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=ZsJZ3NaU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j13-20020a170902da8d00b001ab10a72d7asi8762543plx.584.2023.05.08.07.33.05; Mon, 08 May 2023 07:33:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=ZsJZ3NaU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234072AbjEHOal (ORCPT + 99 others); Mon, 8 May 2023 10:30:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234690AbjEHOaI (ORCPT ); Mon, 8 May 2023 10:30:08 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B023F6E9F for ; Mon, 8 May 2023 07:29:44 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6434e65d808so4888595b3a.3 for ; Mon, 08 May 2023 07:29:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556184; x=1686148184; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hmnZIR+PkD3LCkRKYUkeh0Lq9PqKZdSPpnDL/aaklyI=; b=ZsJZ3NaU8HdYuDz880RSfryjmdnSSGFlinXEQM7tcguRbLQttYp8ifuwXorqFaLJg7 M+7NgwwuNTmTbCpJY2lRXBlkMRkYXhHQpWmFDB+wULS5DwyzsM60Nk4YPm0X1OYPviZG Hk7BzLGLc+oTaBNgaVDNCeMVIjirjznOfIzO+2Qwb922685l3i72RtxNsW7+8RbsNS8v 0qAhdzTwfRiHib4JCOu6d9zHnLD6Lkyjm2qjt85UiUE3s1fDoPZAkNUmfL8Hc3E/H9bL WRT7WCT2keps4j2vjqFtNd/yzgqiiHgDQd7tNMVdZsjg5dEUNbPX4Ze80K+OcTEaAbdY 3a+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556184; x=1686148184; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hmnZIR+PkD3LCkRKYUkeh0Lq9PqKZdSPpnDL/aaklyI=; b=Tj6W0XZPXTOKGtJn5rfrwMmRX2li3mncB8guUfz3BtXogBpo5DfAAAqpE+so0BXvTh Y24Ml8AOZWW7EBM2wYwPJRCJqKV9huifzD4zCGwEWoCQhO98n05Kjv+nGJeZz1ap27L6 qEqT6BJZhj6ybIJZNKr+gwLfacWS+eGQHPvENNf/myY29eassn2jJjgpcvwJ9KVVyNrx 5y0lkNv9Tbl8BDQMHcWM3MmsHyMOC4DrECqVCAjRMviyXxLxZdTGB2NWLa+4QtcF6HRI /5wz3CP+VVpjVJzrhUbQzK8nqHfcmbxAfOsN2pTNRt4eyHJmuVFJgwhubCdnlnLxDKOr uIew== X-Gm-Message-State: AC+VfDyT17UiNPNyuxRRV6nSvMZ1O3yhYfh5ujydcj9Ul1BgB5TTuOHv C8Sl3P6vXRtJRSPvtxCeAblKcA== X-Received: by 2002:a05:6a00:10cd:b0:645:fc7b:63d6 with SMTP id d13-20020a056a0010cd00b00645fc7b63d6mr4518998pfu.6.1683556183964; Mon, 08 May 2023 07:29:43 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:43 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 09/11] irqchip: Add RISC-V advanced PLIC driver Date: Mon, 8 May 2023 19:58:40 +0530 Message-Id: <20230508142842.854564-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765336837939041180?= X-GMAIL-MSGID: =?utf-8?q?1765336837939041180?= The RISC-V advanced interrupt architecture (AIA) specification defines a new interrupt controller for managing wired interrupts on a RISC-V platform. This new interrupt controller is referred to as advanced platform-level interrupt controller (APLIC) which can forward wired interrupts to CPUs (or HARTs) as local interrupts OR as message signaled interrupts. (For more details refer https://github.com/riscv/riscv-aia) This patch adds an irqchip driver for RISC-V APLIC found on RISC-V platforms. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-aplic.c | 750 ++++++++++++++++++++++++++++ include/linux/irqchip/riscv-aplic.h | 119 +++++ 4 files changed, 876 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-aplic.c create mode 100644 include/linux/irqchip/riscv-aplic.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index d700980372ef..834c0329f583 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -544,6 +544,12 @@ config SIFIVE_PLIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP +config RISCV_APLIC + bool + depends on RISCV + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ + config RISCV_IMSIC bool depends on RISCV diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 577bde3e986b..438b8e1a152c 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o +obj-$(CONFIG_RISCV_APLIC) += irq-riscv-aplic.o obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic.o obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o diff --git a/drivers/irqchip/irq-riscv-aplic.c b/drivers/irqchip/irq-riscv-aplic.c new file mode 100644 index 000000000000..207138ee0e92 --- /dev/null +++ b/drivers/irqchip/irq-riscv-aplic.c @@ -0,0 +1,750 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv-aplic: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define APLIC_DEFAULT_PRIORITY 1 +#define APLIC_DISABLE_IDELIVERY 0 +#define APLIC_ENABLE_IDELIVERY 1 +#define APLIC_DISABLE_ITHRESHOLD 1 +#define APLIC_ENABLE_ITHRESHOLD 0 + +struct aplic_msicfg { + phys_addr_t base_ppn; + u32 hhxs; + u32 hhxw; + u32 lhxs; + u32 lhxw; +}; + +struct aplic_idc { + unsigned int hart_index; + void __iomem *regs; + struct aplic_priv *priv; +}; + +struct aplic_priv { + struct fwnode_handle *fwnode; + u32 gsi_base; + u32 nr_irqs; + u32 nr_idcs; + void __iomem *regs; + struct irq_domain *irqdomain; + struct aplic_msicfg msicfg; + struct cpumask lmask; +}; + +static unsigned int aplic_idc_parent_irq; +static DEFINE_PER_CPU(struct aplic_idc, aplic_idcs); + +static void aplic_irq_unmask(struct irq_data *d) +{ + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); + + writel(d->hwirq, priv->regs + APLIC_SETIENUM); + + if (!priv->nr_idcs) + irq_chip_unmask_parent(d); +} + +static void aplic_irq_mask(struct irq_data *d) +{ + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); + + writel(d->hwirq, priv->regs + APLIC_CLRIENUM); + + if (!priv->nr_idcs) + irq_chip_mask_parent(d); +} + +static int aplic_set_type(struct irq_data *d, unsigned int type) +{ + u32 val = 0; + void __iomem *sourcecfg; + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); + + switch (type) { + case IRQ_TYPE_NONE: + val = APLIC_SOURCECFG_SM_INACTIVE; + break; + case IRQ_TYPE_LEVEL_LOW: + val = APLIC_SOURCECFG_SM_LEVEL_LOW; + break; + case IRQ_TYPE_LEVEL_HIGH: + val = APLIC_SOURCECFG_SM_LEVEL_HIGH; + break; + case IRQ_TYPE_EDGE_FALLING: + val = APLIC_SOURCECFG_SM_EDGE_FALL; + break; + case IRQ_TYPE_EDGE_RISING: + val = APLIC_SOURCECFG_SM_EDGE_RISE; + break; + default: + return -EINVAL; + } + + sourcecfg = priv->regs + APLIC_SOURCECFG_BASE; + sourcecfg += (d->hwirq - 1) * sizeof(u32); + writel(val, sourcecfg); + + return 0; +} + +static void aplic_irq_eoi(struct irq_data *d) +{ + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); + u32 reg_off, reg_mask; + + /* + * EOI handling only required only for level-triggered + * interrupts in APLIC MSI mode. + */ + + if (priv->nr_idcs) + return; + + reg_off = APLIC_CLRIP_BASE + ((d->hwirq / APLIC_IRQBITS_PER_REG) * 4); + reg_mask = BIT(d->hwirq % APLIC_IRQBITS_PER_REG); + switch (irqd_get_trigger_type(d)) { + case IRQ_TYPE_LEVEL_LOW: + if (!(readl(priv->regs + reg_off) & reg_mask)) + writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); + break; + case IRQ_TYPE_LEVEL_HIGH: + if (readl(priv->regs + reg_off) & reg_mask) + writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); + break; + } +} + +#ifdef CONFIG_SMP +static int aplic_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, bool force) +{ + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); + struct aplic_idc *idc; + unsigned int cpu, val; + struct cpumask amask; + void __iomem *target; + + if (!priv->nr_idcs) + return irq_chip_set_affinity_parent(d, mask_val, force); + + cpumask_and(&amask, &priv->lmask, mask_val); + + if (force) + cpu = cpumask_first(&amask); + else + cpu = cpumask_any_and(&amask, cpu_online_mask); + + if (cpu >= nr_cpu_ids) + return -EINVAL; + + idc = per_cpu_ptr(&aplic_idcs, cpu); + target = priv->regs + APLIC_TARGET_BASE; + target += (d->hwirq - 1) * sizeof(u32); + val = idc->hart_index & APLIC_TARGET_HART_IDX_MASK; + val <<= APLIC_TARGET_HART_IDX_SHIFT; + val |= APLIC_DEFAULT_PRIORITY; + writel(val, target); + + irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK_DONE; +} +#endif + +static struct irq_chip aplic_chip = { + .name = "RISC-V APLIC", + .irq_mask = aplic_irq_mask, + .irq_unmask = aplic_irq_unmask, + .irq_set_type = aplic_set_type, + .irq_eoi = aplic_irq_eoi, +#ifdef CONFIG_SMP + .irq_set_affinity = aplic_set_affinity, +#endif + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int aplic_irqdomain_translate(struct irq_fwspec *fwspec, + u32 gsi_base, + unsigned long *hwirq, + unsigned int *type) +{ + if (WARN_ON(fwspec->param_count < 2)) + return -EINVAL; + if (WARN_ON(!fwspec->param[0])) + return -EINVAL; + + /* For DT, gsi_base is always zero. */ + *hwirq = fwspec->param[0] - gsi_base; + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + + WARN_ON(*type == IRQ_TYPE_NONE); + + return 0; +} + +static int aplic_irqdomain_msi_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct aplic_priv *priv = platform_msi_get_host_data(d); + + return aplic_irqdomain_translate(fwspec, priv->gsi_base, hwirq, type); +} + +static int aplic_irqdomain_msi_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + int i, ret; + unsigned int type; + irq_hw_number_t hwirq; + struct irq_fwspec *fwspec = arg; + struct aplic_priv *priv = platform_msi_get_host_data(domain); + + ret = aplic_irqdomain_translate(fwspec, priv->gsi_base, &hwirq, &type); + if (ret) + return ret; + + ret = platform_msi_device_domain_alloc(domain, virq, nr_irqs); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &aplic_chip, priv, handle_fasteoi_irq, + NULL, NULL); + /* + * APLIC does not implement irq_disable() so Linux interrupt + * subsystem will take a lazy approach for disabling an APLIC + * interrupt. This means APLIC interrupts are left unmasked + * upon system suspend and interrupts are not processed + * immediately upon system wake up. To tackle this, we disable + * the lazy approach for all APLIC interrupts. + */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; +} + +static const struct irq_domain_ops aplic_irqdomain_msi_ops = { + .translate = aplic_irqdomain_msi_translate, + .alloc = aplic_irqdomain_msi_alloc, + .free = platform_msi_device_domain_free, +}; + +static int aplic_irqdomain_idc_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct aplic_priv *priv = d->host_data; + + return aplic_irqdomain_translate(fwspec, priv->gsi_base, hwirq, type); +} + +static int aplic_irqdomain_idc_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + int i, ret; + unsigned int type; + irq_hw_number_t hwirq; + struct irq_fwspec *fwspec = arg; + struct aplic_priv *priv = domain->host_data; + + ret = aplic_irqdomain_translate(fwspec, priv->gsi_base, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &aplic_chip, priv, handle_fasteoi_irq, + NULL, NULL); + irq_set_affinity(virq + i, &priv->lmask); + /* See the reason described in aplic_irqdomain_msi_alloc() */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; +} + +static const struct irq_domain_ops aplic_irqdomain_idc_ops = { + .translate = aplic_irqdomain_idc_translate, + .alloc = aplic_irqdomain_idc_alloc, + .free = irq_domain_free_irqs_top, +}; + +static void aplic_init_hw_irqs(struct aplic_priv *priv) +{ + int i; + + /* Disable all interrupts */ + for (i = 0; i <= priv->nr_irqs; i += 32) + writel(-1U, priv->regs + APLIC_CLRIE_BASE + + (i / 32) * sizeof(u32)); + + /* Set interrupt type and default priority for all interrupts */ + for (i = 1; i <= priv->nr_irqs; i++) { + writel(0, priv->regs + APLIC_SOURCECFG_BASE + + (i - 1) * sizeof(u32)); + writel(APLIC_DEFAULT_PRIORITY, + priv->regs + APLIC_TARGET_BASE + + (i - 1) * sizeof(u32)); + } + + /* Clear APLIC domaincfg */ + writel(0, priv->regs + APLIC_DOMAINCFG); +} + +static void aplic_init_hw_global(struct aplic_priv *priv) +{ + u32 val; +#ifdef CONFIG_RISCV_M_MODE + u32 valH; + + if (!priv->nr_idcs) { + val = priv->msicfg.base_ppn; + valH = (priv->msicfg.base_ppn >> 32) & + APLIC_xMSICFGADDRH_BAPPN_MASK; + valH |= (priv->msicfg.lhxw & APLIC_xMSICFGADDRH_LHXW_MASK) + << APLIC_xMSICFGADDRH_LHXW_SHIFT; + valH |= (priv->msicfg.hhxw & APLIC_xMSICFGADDRH_HHXW_MASK) + << APLIC_xMSICFGADDRH_HHXW_SHIFT; + valH |= (priv->msicfg.lhxs & APLIC_xMSICFGADDRH_LHXS_MASK) + << APLIC_xMSICFGADDRH_LHXS_SHIFT; + valH |= (priv->msicfg.hhxs & APLIC_xMSICFGADDRH_HHXS_MASK) + << APLIC_xMSICFGADDRH_HHXS_SHIFT; + writel(val, priv->regs + APLIC_xMSICFGADDR); + writel(valH, priv->regs + APLIC_xMSICFGADDRH); + } +#endif + + /* Setup APLIC domaincfg register */ + val = readl(priv->regs + APLIC_DOMAINCFG); + val |= APLIC_DOMAINCFG_IE; + if (!priv->nr_idcs) + val |= APLIC_DOMAINCFG_DM; + writel(val, priv->regs + APLIC_DOMAINCFG); + if (readl(priv->regs + APLIC_DOMAINCFG) != val) + pr_warn("%pfwP: unable to write 0x%x in domaincfg\n", + priv->fwnode, val); +} + +static void aplic_msi_write_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + unsigned int group_index, hart_index, guest_index, val; + struct irq_data *d = irq_get_irq_data(desc->irq); + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); + struct aplic_msicfg *mc = &priv->msicfg; + phys_addr_t tppn, tbppn, msg_addr; + void __iomem *target; + + /* For zeroed MSI, simply write zero into the target register */ + if (!msg->address_hi && !msg->address_lo && !msg->data) { + target = priv->regs + APLIC_TARGET_BASE; + target += (d->hwirq - 1) * sizeof(u32); + writel(0, target); + return; + } + + /* Sanity check on message data */ + WARN_ON(msg->data > APLIC_TARGET_EIID_MASK); + + /* Compute target MSI address */ + msg_addr = (((u64)msg->address_hi) << 32) | msg->address_lo; + tppn = msg_addr >> APLIC_xMSICFGADDR_PPN_SHIFT; + + /* Compute target HART Base PPN */ + tbppn = tppn; + tbppn &= ~APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); + tbppn &= ~APLIC_xMSICFGADDR_PPN_LHX(mc->lhxw, mc->lhxs); + tbppn &= ~APLIC_xMSICFGADDR_PPN_HHX(mc->hhxw, mc->hhxs); + WARN_ON(tbppn != mc->base_ppn); + + /* Compute target group and hart indexes */ + group_index = (tppn >> APLIC_xMSICFGADDR_PPN_HHX_SHIFT(mc->hhxs)) & + APLIC_xMSICFGADDR_PPN_HHX_MASK(mc->hhxw); + hart_index = (tppn >> APLIC_xMSICFGADDR_PPN_LHX_SHIFT(mc->lhxs)) & + APLIC_xMSICFGADDR_PPN_LHX_MASK(mc->lhxw); + hart_index |= (group_index << mc->lhxw); + WARN_ON(hart_index > APLIC_TARGET_HART_IDX_MASK); + + /* Compute target guest index */ + guest_index = tppn & APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); + WARN_ON(guest_index > APLIC_TARGET_GUEST_IDX_MASK); + + /* Update IRQ TARGET register */ + target = priv->regs + APLIC_TARGET_BASE; + target += (d->hwirq - 1) * sizeof(u32); + val = (hart_index & APLIC_TARGET_HART_IDX_MASK) + << APLIC_TARGET_HART_IDX_SHIFT; + val |= (guest_index & APLIC_TARGET_GUEST_IDX_MASK) + << APLIC_TARGET_GUEST_IDX_SHIFT; + val |= (msg->data & APLIC_TARGET_EIID_MASK); + writel(val, target); +} + +static int aplic_setup_msi(struct aplic_priv *priv) +{ + struct aplic_msicfg *mc = &priv->msicfg; + const struct imsic_global_config *imsic_global; + + /* + * The APLIC outgoing MSI config registers assume target MSI + * controller to be RISC-V AIA IMSIC controller. + */ + imsic_global = imsic_get_global_config(); + if (!imsic_global) { + pr_err("%pfwP: IMSIC global config not found\n", + priv->fwnode); + return -ENODEV; + } + + /* Find number of guest index bits (LHXS) */ + mc->lhxs = imsic_global->guest_index_bits; + if (APLIC_xMSICFGADDRH_LHXS_MASK < mc->lhxs) { + pr_err("%pfwP: IMSIC guest index bits big for APLIC LHXS\n", + priv->fwnode); + return -EINVAL; + } + + /* Find number of HART index bits (LHXW) */ + mc->lhxw = imsic_global->hart_index_bits; + if (APLIC_xMSICFGADDRH_LHXW_MASK < mc->lhxw) { + pr_err("%pfwP: IMSIC hart index bits big for APLIC LHXW\n", + priv->fwnode); + return -EINVAL; + } + + /* Find number of group index bits (HHXW) */ + mc->hhxw = imsic_global->group_index_bits; + if (APLIC_xMSICFGADDRH_HHXW_MASK < mc->hhxw) { + pr_err("%pfwP: IMSIC group index bits big for APLIC HHXW\n", + priv->fwnode); + return -EINVAL; + } + + /* Find first bit position of group index (HHXS) */ + mc->hhxs = imsic_global->group_index_shift; + if (mc->hhxs < (2 * APLIC_xMSICFGADDR_PPN_SHIFT)) { + pr_err("%pfwP: IMSIC group index shift should be >= %d\n", + priv->fwnode, (2 * APLIC_xMSICFGADDR_PPN_SHIFT)); + return -EINVAL; + } + mc->hhxs -= (2 * APLIC_xMSICFGADDR_PPN_SHIFT); + if (APLIC_xMSICFGADDRH_HHXS_MASK < mc->hhxs) { + pr_err("%pfwP: IMSIC group index shift big for APLIC HHXS\n", + priv->fwnode); + return -EINVAL; + } + + /* Compute PPN base */ + mc->base_ppn = imsic_global->base_addr >> APLIC_xMSICFGADDR_PPN_SHIFT; + mc->base_ppn &= ~APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); + mc->base_ppn &= ~APLIC_xMSICFGADDR_PPN_LHX(mc->lhxw, mc->lhxs); + mc->base_ppn &= ~APLIC_xMSICFGADDR_PPN_HHX(mc->hhxw, mc->hhxs); + + /* Use all possible CPUs as lmask */ + cpumask_copy(&priv->lmask, cpu_possible_mask); + + return 0; +} + +/* + * To handle an APLIC IDC interrupts, we just read the CLAIMI register + * which will return highest priority pending interrupt and clear the + * pending bit of the interrupt. This process is repeated until CLAIMI + * register return zero value. + */ +static void aplic_idc_handle_irq(struct irq_desc *desc) +{ + struct aplic_idc *idc = this_cpu_ptr(&aplic_idcs); + struct irq_chip *chip = irq_desc_get_chip(desc); + irq_hw_number_t hw_irq; + int irq; + + chained_irq_enter(chip, desc); + + while ((hw_irq = readl(idc->regs + APLIC_IDC_CLAIMI))) { + hw_irq = hw_irq >> APLIC_IDC_TOPI_ID_SHIFT; + irq = irq_find_mapping(idc->priv->irqdomain, hw_irq); + + if (unlikely(irq <= 0)) + pr_warn_ratelimited("hw_irq %lu mapping not found\n", + hw_irq); + else + generic_handle_irq(irq); + } + + chained_irq_exit(chip, desc); +} + +static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) +{ + u32 de = (en) ? APLIC_ENABLE_IDELIVERY : APLIC_DISABLE_IDELIVERY; + u32 th = (en) ? APLIC_ENABLE_ITHRESHOLD : APLIC_DISABLE_ITHRESHOLD; + + /* Priority must be less than threshold for interrupt triggering */ + writel(th, idc->regs + APLIC_IDC_ITHRESHOLD); + + /* Delivery must be set to 1 for interrupt triggering */ + writel(de, idc->regs + APLIC_IDC_IDELIVERY); +} + +static int aplic_idc_dying_cpu(unsigned int cpu) +{ + if (aplic_idc_parent_irq) + disable_percpu_irq(aplic_idc_parent_irq); + + return 0; +} + +static int aplic_idc_starting_cpu(unsigned int cpu) +{ + if (aplic_idc_parent_irq) + enable_percpu_irq(aplic_idc_parent_irq, + irq_get_trigger_type(aplic_idc_parent_irq)); + + return 0; +} + +static int aplic_setup_idc(struct aplic_priv *priv) +{ + int i, j, rc, cpu, setup_count = 0; + struct fwnode_reference_args parent; + struct irq_domain *domain; + unsigned long hartid; + struct aplic_idc *idc; + u32 val; + + /* Setup per-CPU IDC and target CPU mask */ + for (i = 0; i < priv->nr_idcs; i++) { + rc = fwnode_property_get_reference_args(priv->fwnode, + "interrupts-extended", "#interrupt-cells", + 0, i, &parent); + if (rc) { + pr_warn("%pfwP: parent irq for IDC%d not found\n", + priv->fwnode, i); + continue; + } + + /* + * Skip interrupts other than external interrupts for + * current privilege level. + */ + if (parent.args[0] != RV_IRQ_EXT) + continue; + + rc = riscv_fw_parent_hartid(parent.fwnode, &hartid); + if (rc) { + pr_warn("%pfwP: invalid hartid for IDC%d\n", + priv->fwnode, i); + continue; + } + + cpu = riscv_hartid_to_cpuid(hartid); + if (cpu < 0) { + pr_warn("%pfwP: invalid cpuid for IDC%d\n", + priv->fwnode, i); + continue; + } + + cpumask_set_cpu(cpu, &priv->lmask); + + idc = per_cpu_ptr(&aplic_idcs, cpu); + idc->hart_index = i; + idc->regs = priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; + idc->priv = priv; + + aplic_idc_set_delivery(idc, true); + + /* + * Boot cpu might not have APLIC hart_index = 0 so check + * and update target registers of all interrupts. + */ + if (cpu == smp_processor_id() && idc->hart_index) { + val = idc->hart_index & APLIC_TARGET_HART_IDX_MASK; + val <<= APLIC_TARGET_HART_IDX_SHIFT; + val |= APLIC_DEFAULT_PRIORITY; + for (j = 1; j <= priv->nr_irqs; j++) + writel(val, priv->regs + APLIC_TARGET_BASE + + (j - 1) * sizeof(u32)); + } + + setup_count++; + } + + /* Find parent domain and register chained handler */ + domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!aplic_idc_parent_irq && domain) { + aplic_idc_parent_irq = irq_create_mapping(domain, RV_IRQ_EXT); + if (aplic_idc_parent_irq) { + irq_set_chained_handler(aplic_idc_parent_irq, + aplic_idc_handle_irq); + + /* + * Setup CPUHP notifier to enable IDC parent + * interrupt on all CPUs + */ + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "irqchip/riscv/aplic:starting", + aplic_idc_starting_cpu, + aplic_idc_dying_cpu); + } + } + + /* Fail if we were not able to setup IDC for any CPU */ + return (setup_count) ? 0 : -ENODEV; +} + +static int aplic_probe(struct platform_device *pdev) +{ + struct fwnode_handle *fwnode = pdev->dev.fwnode; + struct fwnode_reference_args parent; + struct aplic_priv *priv; + struct resource *res; + phys_addr_t pa; + int rc; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->fwnode = fwnode; + + /* Map the MMIO registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + pr_err("%pfwP: failed to get MMIO resource\n", fwnode); + return -EINVAL; + } + priv->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!priv->regs) { + pr_err("%pfwP: failed map MMIO registers\n", fwnode); + return -ENOMEM; + } + + /* + * Find out GSI base number + * + * Note: DT does not define "riscv,gsi-base" property so GSI + * base is always zero for DT. + */ + rc = fwnode_property_read_u32_array(fwnode, "riscv,gsi-base", + &priv->gsi_base, 1); + if (rc) + priv->gsi_base = 0; + + /* Find out number of interrupt sources */ + rc = fwnode_property_read_u32_array(fwnode, "riscv,num-sources", + &priv->nr_irqs, 1); + if (rc) { + pr_err("%pfwP: failed to get number of interrupt sources\n", + fwnode); + return rc; + } + + /* Setup initial state APLIC interrupts */ + aplic_init_hw_irqs(priv); + + /* + * Find out number of IDCs based on parent interrupts + * + * If "msi-parent" property is present then we ignore the + * APLIC IDCs which forces the APLIC driver to use MSI mode. + */ + if (!fwnode_property_present(fwnode, "msi-parent")) { + while (!fwnode_property_get_reference_args(fwnode, + "interrupts-extended", "#interrupt-cells", + 0, priv->nr_idcs, &parent)) + priv->nr_idcs++; + } + + /* Setup IDCs or MSIs based on number of IDCs */ + if (priv->nr_idcs) + rc = aplic_setup_idc(priv); + else + rc = aplic_setup_msi(priv); + if (rc) { + pr_err("%pfwP: failed setup %s\n", + fwnode, priv->nr_idcs ? "IDCs" : "MSIs"); + return rc; + } + + /* Setup global config and interrupt delivery */ + aplic_init_hw_global(priv); + + /* Create irq domain instance for the APLIC */ + if (priv->nr_idcs) + priv->irqdomain = irq_domain_create_linear( + priv->fwnode, + priv->nr_irqs + 1, + &aplic_irqdomain_idc_ops, + priv); + else + priv->irqdomain = platform_msi_create_device_domain( + &pdev->dev, + priv->nr_irqs + 1, + aplic_msi_write_msg, + &aplic_irqdomain_msi_ops, + priv); + if (!priv->irqdomain) { + pr_err("%pfwP: failed to add irq domain\n", priv->fwnode); + return -ENOMEM; + } + + /* Advertise the interrupt controller */ + if (priv->nr_idcs) { + pr_info("%pfwP: %d interrupts directly connected to %d CPUs\n", + priv->fwnode, priv->nr_irqs, priv->nr_idcs); + } else { + pa = priv->msicfg.base_ppn << APLIC_xMSICFGADDR_PPN_SHIFT; + pr_info("%pfwP: %d interrupts forwared to MSI base %pa\n", + priv->fwnode, priv->nr_irqs, &pa); + } + + return 0; +} + +static const struct of_device_id aplic_match[] = { + { .compatible = "riscv,aplic" }, + {} +}; + +static struct platform_driver aplic_driver = { + .driver = { + .name = "riscv-aplic", + .of_match_table = aplic_match, + }, + .probe = aplic_probe, +}; + +static int __init aplic_init(void) +{ + return platform_driver_register(&aplic_driver); +} +core_initcall(aplic_init); diff --git a/include/linux/irqchip/riscv-aplic.h b/include/linux/irqchip/riscv-aplic.h new file mode 100644 index 000000000000..97e198ea0109 --- /dev/null +++ b/include/linux/irqchip/riscv-aplic.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ +#ifndef __LINUX_IRQCHIP_RISCV_APLIC_H +#define __LINUX_IRQCHIP_RISCV_APLIC_H + +#include + +#define APLIC_MAX_IDC BIT(14) +#define APLIC_MAX_SOURCE 1024 + +#define APLIC_DOMAINCFG 0x0000 +#define APLIC_DOMAINCFG_RDONLY 0x80000000 +#define APLIC_DOMAINCFG_IE BIT(8) +#define APLIC_DOMAINCFG_DM BIT(2) +#define APLIC_DOMAINCFG_BE BIT(0) + +#define APLIC_SOURCECFG_BASE 0x0004 +#define APLIC_SOURCECFG_D BIT(10) +#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff +#define APLIC_SOURCECFG_SM_MASK 0x00000007 +#define APLIC_SOURCECFG_SM_INACTIVE 0x0 +#define APLIC_SOURCECFG_SM_DETACH 0x1 +#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 +#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 +#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 +#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 + +#define APLIC_MMSICFGADDR 0x1bc0 +#define APLIC_MMSICFGADDRH 0x1bc4 +#define APLIC_SMSICFGADDR 0x1bc8 +#define APLIC_SMSICFGADDRH 0x1bcc + +#ifdef CONFIG_RISCV_M_MODE +#define APLIC_xMSICFGADDR APLIC_MMSICFGADDR +#define APLIC_xMSICFGADDRH APLIC_MMSICFGADDRH +#else +#define APLIC_xMSICFGADDR APLIC_SMSICFGADDR +#define APLIC_xMSICFGADDRH APLIC_SMSICFGADDRH +#endif + +#define APLIC_xMSICFGADDRH_L BIT(31) +#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f +#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24 +#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7 +#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20 +#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7 +#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16 +#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf +#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12 +#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff + +#define APLIC_xMSICFGADDR_PPN_SHIFT 12 + +#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \ + (BIT(__lhxs) - 1) + +#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \ + (BIT(__lhxw) - 1) +#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \ + ((__lhxs)) +#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \ + (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \ + APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs)) + +#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \ + (BIT(__hhxw) - 1) +#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \ + ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT) +#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \ + (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \ + APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs)) + +#define APLIC_IRQBITS_PER_REG 32 + +#define APLIC_SETIP_BASE 0x1c00 +#define APLIC_SETIPNUM 0x1cdc + +#define APLIC_CLRIP_BASE 0x1d00 +#define APLIC_CLRIPNUM 0x1ddc + +#define APLIC_SETIE_BASE 0x1e00 +#define APLIC_SETIENUM 0x1edc + +#define APLIC_CLRIE_BASE 0x1f00 +#define APLIC_CLRIENUM 0x1fdc + +#define APLIC_SETIPNUM_LE 0x2000 +#define APLIC_SETIPNUM_BE 0x2004 + +#define APLIC_GENMSI 0x3000 + +#define APLIC_TARGET_BASE 0x3004 +#define APLIC_TARGET_HART_IDX_SHIFT 18 +#define APLIC_TARGET_HART_IDX_MASK 0x3fff +#define APLIC_TARGET_GUEST_IDX_SHIFT 12 +#define APLIC_TARGET_GUEST_IDX_MASK 0x3f +#define APLIC_TARGET_IPRIO_MASK 0xff +#define APLIC_TARGET_EIID_MASK 0x7ff + +#define APLIC_IDC_BASE 0x4000 +#define APLIC_IDC_SIZE 32 + +#define APLIC_IDC_IDELIVERY 0x00 + +#define APLIC_IDC_IFORCE 0x04 + +#define APLIC_IDC_ITHRESHOLD 0x08 + +#define APLIC_IDC_TOPI 0x18 +#define APLIC_IDC_TOPI_ID_SHIFT 16 +#define APLIC_IDC_TOPI_ID_MASK 0x3ff +#define APLIC_IDC_TOPI_PRIO_MASK 0xff + +#define APLIC_IDC_CLAIMI 0x1c + +#endif From patchwork Mon May 8 14:28:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91193 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2210488vqo; Mon, 8 May 2023 07:46:16 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6QSIKvsTcmVJPYx79TZQbIOuemfe6L12pJ6nEaORvBR1v/bQbIGIFv29Ns0gD7gwhFZm5H X-Received: by 2002:a05:6a00:1828:b0:643:9b40:103e with SMTP id y40-20020a056a00182800b006439b40103emr14081720pfa.30.1683557176536; Mon, 08 May 2023 07:46:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683557176; cv=none; d=google.com; s=arc-20160816; b=ZWipHkiPAGtZAIPG1sb1k8R8KHY1D8g/zSy/L+/TipcLUeNw5FkUb8SMstKs2pt4PH 8PUqr8yS6VmGDgNFRCJJ59G/CMtwI2cKMpx1GBbmnsyH1WujDO5G4ZdsKRys00ipD4y8 wmMWzMVRU/afx9RmVhKsWtsukW5lAjleCUCSC4FjGZ78Rmtib8rQfJA+tpYSRQ4lKDQ6 fFIJJSnWOQxwN3CWXcdeaGvjFHyCJVIT/uaeVh6j8mTQUyvxCLhnskD5YtVAP8gVXmCu TMQrIxzqvNJcWlZV8VOPCL0CL/EoZweLQAXRZEb5mI4ho6kVvIwNU0vHh/QsvInIr/vz jlkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ib+AURYSmjIxuoqk+PR8Eg/Z3fYq7w+OW68J7DC1sRs=; b=K/63WwJSOQAugG5gfNXmyWBte71OZUaAS3VN7jAGgFEpbnjVXDbtYv/6VBLcvdebRr qnljNDlOTOkLKRqBb4cgJAzUlH+8qvmPSUg9DXYzJ/pLExHY0Rpd5CnPLNrvGavw4+gq 57gMxdDr5ZrXbl9YEQLWGlw/UjQzXXC5IJyODla9J/zmYDtoAw4zTAk1CoujiVqk6Lmh L2dBbPnemkfDmhaVu/qKR62m30bHjokCo3qTLBI59dBcTlRLzuibiYfjJeOOvqL26KEF +vPAUb794e3zmAqjoti13DtAxlrYkpUxFHk9MgemFgonJCjuas38te9SjkpOcaF3rdUZ vCEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=lhf0yTrL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y1-20020aa79ae1000000b0063b8f3a4d42si71707pfp.163.2023.05.08.07.46.02; Mon, 08 May 2023 07:46:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=lhf0yTrL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235005AbjEHOaq (ORCPT + 99 others); Mon, 8 May 2023 10:30:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233973AbjEHOaN (ORCPT ); Mon, 8 May 2023 10:30:13 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F9218A61 for ; Mon, 8 May 2023 07:29:49 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-64384274895so3208907b3a.2 for ; Mon, 08 May 2023 07:29:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556189; x=1686148189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ib+AURYSmjIxuoqk+PR8Eg/Z3fYq7w+OW68J7DC1sRs=; b=lhf0yTrL5foE3dgkCXYnbKFaPVDfELgWh9Qfu/YV+eeRXTgmNBLamrISJGm/kf8awb /Q+x7COPipzhN8O060faYDbfE9mfR23SP9HjXYhGusmHffrOHXqsmpI1CeuvtIza3iJb D2HJTugPooWWFNeSmHWphhPLl9HTV5glDX0ktJXkQfOxo9GqBoI+XQwkhqqVu2fbXa++ 7IVbVAbG5rwHmJWxdfwxWkg8E8AvJFCGWiFL1GD/XfG5ng5yS3gQtpftU4y0mQXFcrjF WuX4XDgTcmDX0aYWje38GHBLesDKvbasYOydQcOSSX1etOg97JceszynFQC+Wv6vzJdq tXiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556189; x=1686148189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ib+AURYSmjIxuoqk+PR8Eg/Z3fYq7w+OW68J7DC1sRs=; b=QlaNf+m7ag/oKR2Jf5WnPTKmH1g0XpTrF2XM45lhejzoEsAzk6rWKV0XGnFgV8Ahba xrSPTyxgejdv7yix+8tJwDnxfA+D9U42QeDt9QaEczkhPVThnmgYTMghFsve4SX7PYnt 8Rq2Ed2x6nJ+oIvsO20NSuKzo+3Bsv5Ks9bCzDF7m13pFwfnKHnIHT5fH7UWm1zFL/Cp WhWySQoefDRkRlLeI9e3tHa5aAZIaKrp4kpbHBjujVTONFOXGWBuhSTSBxfZtCOXolby NuOdTlE6Nvr04mxRcIaZerwg6W6t47Ctdn5pC5Y7Bfqk/+JKRYEU5GeuwqhJX7LRoz+j NrSg== X-Gm-Message-State: AC+VfDwNAxlPJzUS757A0mAijVSEWj5mo22KaCppk6TQcEU+cVlVa9y2 QdEwyzzaiNyx8WpRNqKw9Q6r6Q== X-Received: by 2002:a05:6a00:b8a:b0:646:663a:9d60 with SMTP id g10-20020a056a000b8a00b00646663a9d60mr2975346pfj.10.1683556188702; Mon, 08 May 2023 07:29:48 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:48 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 10/11] RISC-V: Select APLIC and IMSIC drivers Date: Mon, 8 May 2023 19:58:41 +0530 Message-Id: <20230508142842.854564-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765337649942559951?= X-GMAIL-MSGID: =?utf-8?q?1765337649942559951?= The QEMU virt machine supports AIA emulation and we also have quite a few RISC-V platforms with AIA support under development so let us select APLIC and IMSIC drivers for all RISC-V platforms. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- arch/riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 491ecd7d2336..1bc2c7659b7d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -135,6 +135,8 @@ config RISCV select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL + select RISCV_APLIC + select RISCV_IMSIC select RISCV_INTC select RISCV_TIMER if RISCV_SBI select SIFIVE_PLIC From patchwork Mon May 8 14:28:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 91183 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2203293vqo; Mon, 8 May 2023 07:34:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4OeDx7HU0LA9fNIBr9oEQq1KtcWrweTeaLCflBcwXqJJCmiyj0GsplsKmxQJyFD95Xygi2 X-Received: by 2002:a05:6a20:8f25:b0:f2:bb0:4622 with SMTP id b37-20020a056a208f2500b000f20bb04622mr12849603pzk.12.1683556464440; Mon, 08 May 2023 07:34:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683556464; cv=none; d=google.com; s=arc-20160816; b=CtVxvc0zi50y0YvT9t/FQTRrrH/OJymmB8R/J+CaZt1rqDAScDC7EVJ3T129uVNOL5 8jm8gOYNsqRbtVwC++8dFvMJMlSC1ZyK5SMzWwqTmYC/180OeC52pPkFZrHlGeYzgXrS f2LJUP0Diz4sXk8HUS1OAgs4nYLYunMX71zVKR4v0+awMGsWIHERAwB95J1Y51/lnAB+ QUpza0liaH/2Vnvn+isuIf1flPxfaUsz7BR1nc8E02r9nNJrsUv+L8dqHA5yWmvL1sZu Xc3I/RPTpQjsmBz67D5fD2jVNLOYY5ASsdkN/PXBt7wRfA3YGgk5UKggZSOxC8HEpy9G X+kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ds73gnsFVEJ6u1RVbKPdKJnDIubBpKmFNgu55xzWEbU=; b=yzYc6/67F0Vmsc7gs00990bnJFW+vnjZiIByF1OOvFl91wwbPRVeo8yB+x8dIQQy9P f+Cfr2rHJR+wZQ/1MWSXzj1GtRvRT+w5kllE6VMoIDi5MvJfTstjY9eoKCMs8MSf5uc8 hYFknxt0m9VCyk3k/uC8+ixeo7nIehGa3ZTeku24JTm3aduo9Ao8O6nqBLISVtYOXjLg 9/YZ0hYlcC+MfQEZKRt7mMXMo3+UWCrbQraba2PaHfHVAdKwN9zwhpUCoU7u0O8iJm/o jiZRhF6Z2RBLOm199bjVnvruD/wYzVBskr0/OM/+BJrpDAgio8cf49jbEwPVM7gH04Ku Zjig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=lJgy3Bj1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g13-20020aa79dcd000000b0063d27c285c9si104687pfq.21.2023.05.08.07.34.09; Mon, 08 May 2023 07:34:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=lJgy3Bj1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235122AbjEHOa6 (ORCPT + 99 others); Mon, 8 May 2023 10:30:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235116AbjEHOaW (ORCPT ); Mon, 8 May 2023 10:30:22 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E01E2129 for ; Mon, 8 May 2023 07:29:54 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-64115eef620so34841917b3a.1 for ; Mon, 08 May 2023 07:29:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556193; x=1686148193; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ds73gnsFVEJ6u1RVbKPdKJnDIubBpKmFNgu55xzWEbU=; b=lJgy3Bj1z5Uiu48QnHfq5K+VBP28Zxgip9ER4Yf6hmQQ8lPjaEpD0RK119Wik1cOJJ iTNHWt1R/TFttkaNBKF61wx8kI5nvD0D/9ouPhVmGkGdKBAO/f6u7tSxBsDns2PtEpHY oIiE2l2cRByWteEpf1vB2MkOni0dvyrKrnVlA/aMsfRfyhdhsK9izbxuoBPC0x7czg3s juTXnjpVJf5pYCmVakR0Cgvp94ANIYMAK+LbvnfCPgH307fCgx//lO8LcLCqPQvCnR2s yrH86CmjZ09YK9L2qscqvWOhivunsdFbAzxUvjvEKMVRsEx5Gn4gHywXyeDI8k3mww/1 TxzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556193; x=1686148193; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ds73gnsFVEJ6u1RVbKPdKJnDIubBpKmFNgu55xzWEbU=; b=ZVZcoVA/yssf/MmS32OKLDHXf3F47VJ2Ehx0n8biDd/KDN60Va/ZTU4B79kpPpgXob t9IdKucb42WqcLm2sU4TdHazh29hw4jVm0+G7TQ19ws7SRMPYQQ6TNFf1wSiXCJ9LIOM UoGVVXX9KO+WN7eMyzCekcTRNeAl+WOLExXpiPZyhO6e2iIoSEC1BUE+S2Bw2EncRLHN hnpSQfCcFdXCBu8LqMd1f5JdEejCffV2bh6Tr7IMJ4ChdnCDX7yIr+q0UqNt9bHoZOcc /owiVN6r1r6Bxw94VsRbiJWUPcsX0B7soocNTX684OkIQg8KRC87ey8SdAkHxK7qjA2T t4iQ== X-Gm-Message-State: AC+VfDxQdeLCQZsZgLmb/7i8psmaIqYETnRHdRCaDJZN9mqTL02laUV7 385at7FYAdkrRWU8yh6MJmL0OQ== X-Received: by 2002:a05:6a20:a5a8:b0:d9:adc3:6a71 with SMTP id bc40-20020a056a20a5a800b000d9adc36a71mr10379138pzb.1.1683556193560; Mon, 08 May 2023 07:29:53 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:53 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 11/11] MAINTAINERS: Add entry for RISC-V AIA drivers Date: Mon, 8 May 2023 19:58:42 +0530 Message-Id: <20230508142842.854564-12-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765336902958810692?= X-GMAIL-MSGID: =?utf-8?q?1765336902958810692?= Add myself as maintainer for RISC-V AIA drivers including the RISC-V INTC driver which supports both AIA and non-AIA platforms. Signed-off-by: Anup Patel --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 083ba321fc7c..8f00b56ef8d5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18111,6 +18111,18 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c +RISC-V AIA DRIVERS +M: Anup Patel +L: linux-riscv@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +F: Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +F: drivers/irqchip/irq-riscv-aplic.c +F: drivers/irqchip/irq-riscv-imsic.c +F: drivers/irqchip/irq-riscv-intc.c +F: include/linux/irqchip/riscv-aplic.h +F: include/linux/irqchip/riscv-imsic.h + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt