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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:02 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Jisheng Zhang , Anup Patel , Atish Patra Subject: [PATCH V5 01/21] riscv: move sbi_init() earlier before jump_label_init() Date: Mon, 8 May 2023 17:22:17 +0530 Message-Id: <20230508115237.216337-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328915156237060?= X-GMAIL-MSGID: =?utf-8?q?1765328915156237060?= From: Jisheng Zhang We call jump_label_init() in setup_arch() is to use static key mechanism earlier, but riscv jump label relies on the sbi functions, If we enable static key before sbi_init(), the code path looks like: static_branch_enable() .. arch_jump_label_transform() patch_text_nosync() flush_icache_range() flush_icache_all() sbi_remote_fence_i() for CONFIG_RISCV_SBI case __sbi_rfence() Since sbi isn't initialized, so NULL deference! Here is a typical panic log: [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 [ 0.000000] Oops [#1] [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.18.0-rc7+ #79 [ 0.000000] Hardware name: riscv-virtio,qemu (DT) [ 0.000000] epc : 0x0 [ 0.000000] ra : sbi_remote_fence_i+0x1e/0x26 [ 0.000000] epc : 0000000000000000 ra : ffffffff80005826 sp : ffffffff80c03d50 [ 0.000000] gp : ffffffff80ca6178 tp : ffffffff80c0ad80 t0 : 6200000000000000 [ 0.000000] t1 : 0000000000000000 t2 : 62203a6b746e6972 s0 : ffffffff80c03d60 [ 0.000000] s1 : ffffffff80001af6 a0 : 0000000000000000 a1 : 0000000000000000 [ 0.000000] a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 [ 0.000000] a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000080200 [ 0.000000] s2 : ffffffff808b3e48 s3 : ffffffff808bf698 s4 : ffffffff80cb2818 [ 0.000000] s5 : 0000000000000001 s6 : ffffffff80c9c345 s7 : ffffffff80895aa0 [ 0.000000] s8 : 0000000000000001 s9 : 000000000000007f s10: 0000000000000000 [ 0.000000] s11: 0000000000000000 t3 : ffffffff80824d08 t4 : 0000000000000022 [ 0.000000] t5 : 000000000000003d t6 : 0000000000000000 [ 0.000000] status: 0000000000000100 badaddr: 0000000000000000 cause: 000000000000000c [ 0.000000] ---[ end trace 0000000000000000 ]--- [ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Fix this issue by moving sbi_init() earlier before jump_label_init() Signed-off-by: Jisheng Zhang Reviewed-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 36b026057503..9fb839074e16 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -270,6 +270,7 @@ void __init setup_arch(char **cmdline_p) *cmdline_p = boot_command_line; early_ioremap_setup(); + sbi_init(); jump_label_init(); parse_early_param(); @@ -283,7 +284,6 @@ void __init setup_arch(char **cmdline_p) misc_mem_init(); init_resources(); - sbi_init(); #ifdef CONFIG_KASAN kasan_init(); From patchwork Mon May 8 11:52:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91096 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2114829vqo; Mon, 8 May 2023 05:26:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7gdCVKfxh2Q274SRoShIu26X6ixVnpnmEHO08XpzImH1f5H/fDRk78dza1y772b84lRwxJ X-Received: by 2002:a17:90a:4e8a:b0:24e:458a:9543 with SMTP id o10-20020a17090a4e8a00b0024e458a9543mr10364873pjh.32.1683548799361; Mon, 08 May 2023 05:26:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548799; cv=none; d=google.com; s=arc-20160816; b=cIUAd7Q7urWFCnrOOHbtuIG7HotVj3ZwjvHNIw6vKFT7ESgiHCaXemj5P7H939FQ5u u4zvp0sVJ3q+VX4ISv29TQe22FZT+UFnBP2io32pi1R41v9ga9w0ZixyWCW0krS84dqT +9cdHD6R99W//vtsQmLEK+k1ak7wDIOCNeoxO1owdDZB/alCkNwM9CUPBp/UhXsAfdUv 1AGFikt0tNvyMgbUygmvJKdUsswAeDZKu/ujm4ngLdjAVpJ/SjhWyAd8wmGF/F9yaQtH heqzGPYvedNRbSWEZSF1NCwSLg5UIyeR+cxAdqD2e9J1O0CR84H/wnn2wez1I6/U20w+ /MoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+3BRBVSL8Q8oMs51cYTt5mS52il5fOg1fDJihGv43qY=; b=Nu6jD6jA/2Y2PW2NyKp20cuQkAHR2v4NO7hw/7R5ISvTCaUtwjDA+LLvfES71MYbuV r+vqCYj6lPVrn5hQRq0Rd3PFYgLc5dLbVQov6c6l/P+nBrono0HHLwmbKvKprKe6yCeW SQrSSylVGzVq0jfcuddl0dt2jVt/j/kUcvpRpcRmtI/kIZSLayVx5xoHUDwvLCdeIIMK k4eYuPXVm1d8zuyeBLPW0zxEF0y0jDbW+AE0Kb2zYnyynPqM2E7DfqOF/k0IQj2xgfFH UmZYLF2xIi3BhEMAv5bCt8xg3oLsXGVkgLJgjTCLG8mNHuUe/CmTmEARIIt4AOK6MLqE VR9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="ES80Pxi/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:11 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L Subject: [PATCH V5 02/21] platform/surface: Disable for RISC-V Date: Mon, 8 May 2023 17:22:18 +0530 Message-Id: <20230508115237.216337-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328865613670169?= X-GMAIL-MSGID: =?utf-8?q?1765328865613670169?= With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in allmodconfig build. However, RISC-V doesn't support sub-word atomics which is used by this driver. Due to this, the build fails with below error. In function ‘ssh_seq_next’, inlined from ‘ssam_request_write_data’ at drivers/platform/surface/aggregator/controller.c:1483:8: ././include/linux/compiler_types.h:399:45: error: call to ‘__compiletime_assert_335’ declared with attribute error: BUILD_BUG failed 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ ./include/linux/compiler.h:78:45: note: in definition of macro ‘unlikely’ 78 | # define unlikely(x) __builtin_expect(!!(x), 0) | ^ ././include/linux/compiler_types.h:387:9: note: in expansion of macro ‘__compiletime_assert’ 387 | __compiletime_assert(condition, msg, prefix, suffix) | ^~~~~~~~~~~~~~~~~~~~ ././include/linux/compiler_types.h:399:9: note: in expansion of macro ‘_compiletime_assert’ 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^~~~~~~~~~~~~~~~~~~ ./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’ 39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) | ^~~~~~~~~~~~~~~~~~ ./include/linux/build_bug.h:59:21: note: in expansion of macro ‘BUILD_BUG_ON_MSG’ 59 | #define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed") | ^~~~~~~~~~~~~~~~ ./arch/riscv/include/asm/cmpxchg.h:335:17: note: in expansion of macro ‘BUILD_BUG’ 335 | BUILD_BUG(); \ | ^~~~~~~~~ ./arch/riscv/include/asm/cmpxchg.h:344:30: note: in expansion of macro ‘__cmpxchg’ 344 | (__typeof__(*(ptr))) __cmpxchg((ptr), \ | ^~~~~~~~~ ./include/linux/atomic/atomic-instrumented.h:1916:9: note: in expansion of macro ‘arch_cmpxchg’ 1916 | arch_cmpxchg(__ai_ptr, __VA_ARGS__); \ | ^~~~~~~~~~~~ drivers/platform/surface/aggregator/controller.c:61:32: note: in expansion of macro ‘cmpxchg’ 61 | while (unlikely((ret = cmpxchg(&c->value, old, new)) != old)) { | ^~~~~~~ There is currently no plan to support this driver for RISC-V. So, disable this driver for RISC-V even when ACPI is enabled for now. Signed-off-by: Sunil V L Acked-by: Maximilian Luz --- drivers/platform/surface/aggregator/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/surface/aggregator/Kconfig b/drivers/platform/surface/aggregator/Kconfig index c114f9dd5fe1..88afc38ffdc5 100644 --- a/drivers/platform/surface/aggregator/Kconfig +++ b/drivers/platform/surface/aggregator/Kconfig @@ -4,7 +4,7 @@ menuconfig SURFACE_AGGREGATOR tristate "Microsoft Surface System Aggregator Module Subsystem and Drivers" depends on SERIAL_DEV_BUS - depends on ACPI + depends on ACPI && !RISCV select CRC_CCITT help The Surface System Aggregator Module (Surface SAM or SSAM) is an From patchwork Mon May 8 11:52:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91084 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2103390vqo; Mon, 8 May 2023 05:09:08 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ54aAUkQU+YdNVBPDu3uSrq7LX2UR6LOFjPNsvHEsOIw/TqPI/36T91sET7vzlgCWC+QvaH X-Received: by 2002:a17:903:2289:b0:1a6:6d9f:2fc9 with SMTP id b9-20020a170903228900b001a66d9f2fc9mr12144565plh.30.1683547748217; Mon, 08 May 2023 05:09:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683547748; cv=none; d=google.com; s=arc-20160816; b=TgI2jnL7kEe/P0+1lTe31Auq01ZQMnpOKjt6GCG+8V7hem2SScaVTJIjC9OKMt4gIQ R2LDde4JKraznaBriAJ467aVqeY3RGAGX09cA+lNRLve79IkpSYvaWvvqGXc8M6OilXV VOx6JGoc5A7yXp0doENlpk0A2xCa/5cTjBpSc+DwiDwXE3zpL06eN4mDqcGN5OxGrcKH sY/I3wAcODWkKxtKM+2wztVogJBb4an+yms67fH4Csur8zeIKv4KzGWMkL91efpZXhYY IxkU6FIUx9QxvX5iVQGdpH7QCKdQ7/Rn5cqzyLPU7nLDVhvoGHWZMqyZ50gOq7egCLVS 2fAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qd6PQ1vE/SZdiXRk2V4YVd/9ukw5PfEy62nQ6sf0Uk0=; b=YtsJmx01b0ICf5evVIAc+eQ8C92861GemWZrJWT06hXv30+bshK+K/v412sM8da5LZ mpkioak4aibGRWn8hxqMkO1Ch0CIzbREWt5iR/6/0y21Ol8hHndVCp3TX4yxvUJXE/Vc /6/3T8J9dQbX0ho6MU9iy7FVt2DPns5UdiYMcyZa3va7Fsr80qUC9CwOMzFuA0b/jnEn KIY3QgZcnaguXQ7x1ZPBFolxegKE5GZk5wkrLS/pRrGKUmFeXKDDuvr/sy7fY/mpIQMH 90oVkum32yJ1hsV9bqp027CM03ESVVvuLDiHYzppGDKHP7Kzeio7vKfNHRLu7Qv5ko/e gyLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Wj+BdFY0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:19 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L Subject: [PATCH V5 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Date: Mon, 8 May 2023 17:22:19 +0530 Message-Id: <20230508115237.216337-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765327763747215118?= X-GMAIL-MSGID: =?utf-8?q?1765327763747215118?= With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in allmodconfig build. However, build fails with clang and below error is seen. drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm "+Q" (*((char __iomem *)fun_base)) ^ This is expected error with clang due to the way it is designed. To fix this issue, move arm64 assembly code under #if. Link: https://github.com/ClangBuiltLinux/linux/issues/999 Signed-off-by: Nathan Chancellor [sunilvl@ventanamicro.com: Moved tmp0 and tmp1 into the #if] Signed-off-by: Sunil V L --- drivers/crypto/hisilicon/qm.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index ad0c042b5e66..2eaeaac2e246 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -610,13 +610,9 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); static void qm_mb_write(struct hisi_qm *qm, const void *src) { void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE; - unsigned long tmp0 = 0, tmp1 = 0; - if (!IS_ENABLED(CONFIG_ARM64)) { - memcpy_toio(fun_base, src, 16); - dma_wmb(); - return; - } +#if IS_ENABLED(CONFIG_ARM64) + unsigned long tmp0 = 0, tmp1 = 0; asm volatile("ldp %0, %1, %3\n" "stp %0, %1, %2\n" @@ -626,6 +622,11 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src) "+Q" (*((char __iomem *)fun_base)) : "Q" (*((char *)src)) : "memory"); +#else + memcpy_toio(fun_base, src, 16); + dma_wmb(); +#endif + } static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox) From patchwork Mon May 8 11:52:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91085 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2103496vqo; Mon, 8 May 2023 05:09:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6G+0FUyPfu/tgs1jPzy1/mpW4wzyndY4XDGpJK7Kr9NK38cJJU7/WYzjQTg+Thf92SKk0w X-Received: by 2002:a17:902:e802:b0:19d:297:f30b with SMTP id u2-20020a170902e80200b0019d0297f30bmr12999041plg.19.1683547756777; Mon, 08 May 2023 05:09:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683547756; cv=none; d=google.com; s=arc-20160816; b=ukqMqJMr1jRugjmxIS6wMGGJiQr/rmlFFQg6k/vEQoRtVPTCcE3oyHXLfFdmSICeXW eaHLt3pELTPHPL8NedVppBQmzaCF224XIBVs4a3D1Sm9icZrs67OyuMNGyhf9CTQUhWw rEoM5GIYtjEz3zJMSAjld99eft/1rp3hKdv0lr+kMq4k9yJEHCd5etYtCMLNvbp4SyQB +FPfup6zyo8cWmHUp/cB+x6irmbeWjD+Aq6AFBg/2m7vUlIiZAJyPxH9uEVPBKuLfLL3 FdI87PLp6WRJpDAP6a4sqTiaTC6VkwZOyf/T67klc1F2Rqe37FWNU0bG3SqgIt5kh7SH KCcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1wcGbfhUP5NrwGCYl7Q1yL0FMzRdJBr1PIlnUSkktJs=; b=hN+3kRv11y6u+T161TnVcO8Ncvp+ms1OkU+FWiiV6oKlpww6qzJ8f6D2WMPAeOBQJH RFrsHf2fqSYSgaOOdLchFFf/kHiztNCfviZrQgAmML+rKUZePOn3thL8b9eqjuZZ1RoT gt5fn469zhQESt4xMRsaaUvwmkizxxsaf9UalH7SRBUzzuMOLd2RnbsVP6LTUnTMFVg4 cSanDwKe3IK3Gts6Bj6EDZtvVhpGRuh1rgCuHYq6ATN6qHl0BqtJH+JEJj0iDD17L6VU pZ/mwQDPmlt6R8aQViopmV49P8HFrIFtDfVAQL3IcLbMFMZEgehY/4b5TCv844Bz+212 zOEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=fBHUfS8f; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Andrew Jones Subject: [PATCH V5 04/21] ACPI: tables: Print RINTC information when MADT is parsed Date: Mon, 8 May 2023 17:22:20 +0530 Message-Id: <20230508115237.216337-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765327772804598956?= X-GMAIL-MSGID: =?utf-8?q?1765327772804598956?= When MADT is parsed, print RINTC information as below: ACPI: RISC-V INTC (acpi_uid[0x0000] hart_id[0x0] enabled) ACPI: RISC-V INTC (acpi_uid[0x0001] hart_id[0x1] enabled) ... ACPI: RISC-V INTC (acpi_uid[0x000f] hart_id[0xf] enabled) This debug information will be very helpful during bring up. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- drivers/acpi/tables.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index 7b4680da57d7..8ab0a82b4da4 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -220,6 +220,16 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header) } break; + case ACPI_MADT_TYPE_RINTC: + { + struct acpi_madt_rintc *p = (struct acpi_madt_rintc *)header; + + pr_debug("RISC-V INTC (acpi_uid[0x%04x] hart_id[0x%llx] %s)\n", + p->uid, p->hart_id, + (p->flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled"); + } + break; + default: pr_warn("Found unsupported MADT entry (type = 0x%x)\n", header->type); From patchwork Mon May 8 11:52:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91086 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2104071vqo; Mon, 8 May 2023 05:10:02 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7bCVeCszBmi7qAtemU3uLSMXCaP4vKG9SrKGq8qPbhTGVDwSOaFB20UNnw/j8nxavXYyxN X-Received: by 2002:a17:902:b696:b0:1a9:bac2:21a2 with SMTP id c22-20020a170902b69600b001a9bac221a2mr9652093pls.21.1683547802577; Mon, 08 May 2023 05:10:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683547802; cv=none; d=google.com; s=arc-20160816; b=RMsG31wGONzBoXd8THA0ZepxrLCGOZGsu28GGaf8k24qs2FQP3yj44JQT/13RL0W2Z MssB0/h8iuWrdkRmSiDyNEHeGLZqy3j8SsdkPrcG6htrisndjrMVPyWaOh4l6AcDhpGZ 6vnlgq4+zOnhbQCX0aIYEWSynQq1zxWsWOU1PYSiydmmSnN8JAPVcQ4RRTJ3KX8IA/sA dE4FolLWHAMzjZNJqzPz45FpS9xtCfsB8vqYaNeGJ8xMhRBKvPta6hC7xxCfdtNFnAEy 0nsBYLhGqTiLG7Kh6iV0RQVz+aOLBniLvzvy9ETuHFp4Oumy2t4EM0uZ7CQVRcNsQe8C Jlbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g9sxg5LZ/1sJSiDItv56ESM72UWoohRRXZed1vK0StQ=; b=n8+Wgi3VcGbj23Nbi9J5ysGzXsJwRjAdl5QmZRQEeVY5lDRemv17X8qBkmhyeFZmdX oRjMh6RrUR3SrzuFdU5bHnabY8oZ/doPrjDZwl4v7XaxuDB+ylM6u+hzRpCKp1De96ng pPgwSCHBMFNaT29idMQ8Z8IKNuNHNRfXeUEwX+ho4UGd/eak7JlEc3XATpStKD06lsVq LkpV6/7UzGPyfAhI7KY77W35sN7VmPRtXEx1mBfhxP7WzvqlMo02ZW6ENrtHqypTlIc/ WeRbmbEpIPqcs5mMF2fGZZtKyDN0VwIiWyfGA1LYwgbkUXE/hXC65G5WG+7lbmyWVu0V 0bLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=LI6hJFWM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:36 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V5 05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Date: Mon, 8 May 2023 17:22:21 +0530 Message-Id: <20230508115237.216337-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765327820265308522?= X-GMAIL-MSGID: =?utf-8?q?1765327820265308522?= Without this, if the tables are larger than 4K, acpi_map() will fail. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- drivers/acpi/osl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 3269a888fb7a..f725813d0cce 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -276,7 +276,7 @@ acpi_map_lookup_virt(void __iomem *virt, acpi_size size) return NULL; } -#if defined(CONFIG_IA64) || defined(CONFIG_ARM64) +#if defined(CONFIG_IA64) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV) /* ioremap will take care of cache attributes */ #define should_use_kmap(pfn) 0 #else From patchwork Mon May 8 11:52:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91090 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2112810vqo; Mon, 8 May 2023 05:23:04 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6ktsHFeYcj2GMGlsGxUGEofvcxkyHr+LQJBknbad4y8Bz1+GqGHG7fINPcCLjPD4Tv0nSV X-Received: by 2002:a17:90a:f8d:b0:250:85ba:6c3d with SMTP id 13-20020a17090a0f8d00b0025085ba6c3dmr3133034pjz.6.1683548583766; Mon, 08 May 2023 05:23:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548583; cv=none; d=google.com; s=arc-20160816; b=B6Z9Pmj61EMC0lEX/MNKct5jmsSofjmh0H/aG2j1Thg7rTI/T/L0ZO+Qz0vNqWHSqG BB+Zxz8Hj5xpWWCEmEZOfex4qrIxtfW149BB1WEL8btWuRMvqGkRHMQ7qoi1F/p6q5Uc 1UaPZkBcLxlOmh5LfBUCTQGoZSDlqADvMw4LRMvx1LhrmKMXlbsVlBqq44ZP0ICEfJ9p NB/4ehPyg+mA1imEEMlVysK9wPWc4LnGF5CXfIHARQbQDUX2AsnOXSK3SJrw/2LTfnDF QJPXb7UQsVzCwmqYnO9jgRjori8wP8HLMlZOFI5JYDh4D3h/ntAN7xCLuLbDk35vUmoA kZtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hXB6eSvEhnIAtMiQWlMtfWUjRdd7V8Gch2IVA+HK6fk=; b=h8t5NrjV2Gx8QuIPz1f4XwuHvX+zH/vnr38uOhrZodT9MdGS25JSLg0w52wh/mzgq3 S+0t/D1z2Ij6NZUw2tTwG7G5+BFWCkdyhUxrwdiW6dxf6vQWy1fWzkEBvX5iNyMiocRf bSZYgZURo2RQfWNDybrVScXRDeJikJUDnlMJbt9wUAKGFVDPtQnY6GZdDDeg7N3qUhi5 cPgDpcpeaI4yal606KnWh8SGrq6+lt0N3VJijyl99a/XJbDnfKc8moBLMUg0ohTfiNCG ObmhEjrpjlUERqqc33Ugnzd4gZ/XESSP0Gb7JdNPPchpd7pBc2tVCF9x1/qj7WEQmBaz Ekbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=ebWTZvVa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:44 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley , Palmer Dabbelt Subject: [PATCH V5 06/21] RISC-V: Add support to build the ACPI core Date: Mon, 8 May 2023 17:22:22 +0530 Message-Id: <20230508115237.216337-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328639850021679?= X-GMAIL-MSGID: =?utf-8?q?1765328639850021679?= Enable ACPI core for RISC-V after adding architecture-specific interfaces and header files required to build the ACPI core. 1) Couple of header files are required unconditionally by the ACPI core. Add empty acenv.h and cpu.h header files. 2) If CONFIG_PCI is enabled, a few PCI related interfaces need to be provided by the architecture. Define dummy interfaces for now so that build succeeds. Actual implementation will be added when PCI support is added for ACPI along with external interrupt controller support. 3) A few globals and memory mapping related functions specific to the architecture need to be provided. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Palmer Dabbelt --- arch/riscv/Kconfig | 5 +++ arch/riscv/include/asm/acenv.h | 11 +++++ arch/riscv/include/asm/acpi.h | 61 ++++++++++++++++++++++++++ arch/riscv/include/asm/cpu.h | 8 ++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/acpi.c | 80 ++++++++++++++++++++++++++++++++++ 6 files changed, 166 insertions(+) create mode 100644 arch/riscv/include/asm/acenv.h create mode 100644 arch/riscv/include/asm/acpi.h create mode 100644 arch/riscv/include/asm/cpu.h create mode 100644 arch/riscv/kernel/acpi.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 348c0fa1fc8c..491ecd7d2336 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -12,6 +12,8 @@ config 32BIT config RISCV def_bool y + select ACPI_GENERIC_GSI if ACPI + select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 @@ -707,6 +709,7 @@ config EFI depends on OF && !XIP_KERNEL depends on MMU default y + select ARCH_SUPPORTS_ACPI if 64BIT select EFI_GENERIC_STUB select EFI_PARAMS_FROM_FDT select EFI_RUNTIME_WRAPPERS @@ -816,3 +819,5 @@ source "drivers/cpufreq/Kconfig" endmenu # "CPU Power Management" source "arch/riscv/kvm/Kconfig" + +source "drivers/acpi/Kconfig" diff --git a/arch/riscv/include/asm/acenv.h b/arch/riscv/include/asm/acenv.h new file mode 100644 index 000000000000..43ae2e32c779 --- /dev/null +++ b/arch/riscv/include/asm/acenv.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * RISC-V specific ACPICA environments and implementation + */ + +#ifndef _ASM_ACENV_H +#define _ASM_ACENV_H + +/* This header is required unconditionally by the ACPI core */ + +#endif /* _ASM_ACENV_H */ diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h new file mode 100644 index 000000000000..bcade255bd6e --- /dev/null +++ b/arch/riscv/include/asm/acpi.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2013-2014, Linaro Ltd. + * Author: Al Stone + * Author: Graeme Gregory + * Author: Hanjun Guo + * + * Copyright (C) 2021-2023, Ventana Micro Systems Inc. + * Author: Sunil V L + */ + +#ifndef _ASM_ACPI_H +#define _ASM_ACPI_H + +/* Basic configuration for ACPI */ +#ifdef CONFIG_ACPI + +/* ACPI table mapping after acpi_permanent_mmap is set */ +void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); +#define acpi_os_ioremap acpi_os_ioremap + +#define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */ +extern int acpi_disabled; +extern int acpi_noirq; +extern int acpi_pci_disabled; + +static inline void disable_acpi(void) +{ + acpi_disabled = 1; + acpi_pci_disabled = 1; + acpi_noirq = 1; +} + +static inline void enable_acpi(void) +{ + acpi_disabled = 0; + acpi_pci_disabled = 0; + acpi_noirq = 0; +} + +/* + * The ACPI processor driver for ACPI core code needs this macro + * to find out whether this cpu was already mapped (mapping from CPU hardware + * ID to CPU logical ID) or not. + */ +#define cpu_physical_id(cpu) cpuid_to_hartid_map(cpu) + +/* + * Since MADT must provide at least one RINTC structure, the + * CPU will be always available in MADT on RISC-V. + */ +static inline bool acpi_has_cpu_in_madt(void) +{ + return true; +} + +static inline void arch_fix_phys_package_id(int num, u32 slot) { } + +#endif /* CONFIG_ACPI */ + +#endif /*_ASM_ACPI_H*/ diff --git a/arch/riscv/include/asm/cpu.h b/arch/riscv/include/asm/cpu.h new file mode 100644 index 000000000000..28d45a6678ce --- /dev/null +++ b/arch/riscv/include/asm/cpu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ASM_CPU_H +#define _ASM_CPU_H + +/* This header is required unconditionally by the ACPI core */ + +#endif /* _ASM_CPU_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index fbdccc21418a..ed5fcd90036e 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -92,3 +92,4 @@ obj-$(CONFIG_COMPAT) += compat_signal.o obj-$(CONFIG_COMPAT) += compat_vdso/ obj-$(CONFIG_64BIT) += pi/ +obj-$(CONFIG_ACPI) += acpi.o diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c new file mode 100644 index 000000000000..81d448c41714 --- /dev/null +++ b/arch/riscv/kernel/acpi.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RISC-V Specific Low-Level ACPI Boot Support + * + * Copyright (C) 2013-2014, Linaro Ltd. + * Author: Al Stone + * Author: Graeme Gregory + * Author: Hanjun Guo + * Author: Tomasz Nowicki + * Author: Naresh Bhat + * + * Copyright (C) 2021-2023, Ventana Micro Systems Inc. + * Author: Sunil V L + */ + +#include +#include +#include + +int acpi_noirq = 1; /* skip ACPI IRQ initialization */ +int acpi_disabled = 1; +EXPORT_SYMBOL(acpi_disabled); + +int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ +EXPORT_SYMBOL(acpi_pci_disabled); + +/* + * __acpi_map_table() will be called before paging_init(), so early_ioremap() + * or early_memremap() should be called here to for ACPI table mapping. + */ +void __init __iomem *__acpi_map_table(unsigned long phys, unsigned long size) +{ + if (!size) + return NULL; + + return early_memremap(phys, size); +} + +void __init __acpi_unmap_table(void __iomem *map, unsigned long size) +{ + if (!map || !size) + return; + + early_memunmap(map, size); +} + +void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) +{ + return memremap(phys, size, MEMREMAP_WB); +} + +#ifdef CONFIG_PCI + +/* + * These interfaces are defined just to enable building ACPI core. + * TODO: Update it with actual implementation when external interrupt + * controller support is added in RISC-V ACPI. + */ +int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 *val) +{ + return PCIBIOS_DEVICE_NOT_FOUND; +} + +int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 val) +{ + return PCIBIOS_DEVICE_NOT_FOUND; +} + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + return -1; +} + +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + return NULL; +} +#endif /* CONFIG_PCI */ From patchwork Mon May 8 11:52:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91095 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2114587vqo; Mon, 8 May 2023 05:26:13 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7rm+zzKztWNOnP0VGuonQrds6pYWvkoqXf6mjs9fiCT6yfGJcqnhJMDBJUkyopKJVAZPsd X-Received: by 2002:a17:902:c411:b0:1a9:3c1d:66de with SMTP id k17-20020a170902c41100b001a93c1d66demr13575328plk.15.1683548772663; Mon, 08 May 2023 05:26:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548772; cv=none; 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:52 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V5 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Date: Mon, 8 May 2023 17:22:23 +0530 Message-Id: <20230508115237.216337-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328837619646505?= X-GMAIL-MSGID: =?utf-8?q?1765328837619646505?= processor_core needs arch-specific functions to map the ACPI ID to the physical ID. In RISC-V platforms, hartid is the physical id and RINTC structure in MADT provides this mapping. Add arch-specific function to get this mapping from RINTC. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 3 +++ drivers/acpi/processor_core.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index bcade255bd6e..9be52b6ffae1 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -15,6 +15,9 @@ /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI +typedef u64 phys_cpuid_t; +#define PHYS_CPUID_INVALID INVALID_HARTID + /* ACPI table mapping after acpi_permanent_mmap is set */ void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); #define acpi_os_ioremap acpi_os_ioremap diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 2ac48cda5b20..d6606a9f2da6 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -106,6 +106,32 @@ static int map_gicc_mpidr(struct acpi_subtable_header *entry, return -EINVAL; } +/* + * Retrieve the RISC-V hartid for the processor + */ +static int map_rintc_hartid(struct acpi_subtable_header *entry, + int device_declaration, u32 acpi_id, + phys_cpuid_t *hartid) +{ + struct acpi_madt_rintc *rintc = + container_of(entry, struct acpi_madt_rintc, header); + + if (!(rintc->flags & ACPI_MADT_ENABLED)) + return -ENODEV; + + /* device_declaration means Device object in DSDT, in the + * RISC-V, logical processors are required to + * have a Processor Device object in the DSDT, so we should + * check device_declaration here + */ + if (device_declaration && rintc->uid == acpi_id) { + *hartid = rintc->hart_id; + return 0; + } + + return -EINVAL; +} + static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, int type, u32 acpi_id) { @@ -136,6 +162,9 @@ static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { if (!map_gicc_mpidr(header, type, acpi_id, &phys_id)) break; + } else if (header->type == ACPI_MADT_TYPE_RINTC) { + if (!map_rintc_hartid(header, type, acpi_id, &phys_id)) + break; } entry += header->length; } From patchwork Mon May 8 11:52:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91091 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2113248vqo; Mon, 8 May 2023 05:23:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4Pvlgp6Y01++VQ4gzibnKMIBE63BIUUounrNwdY+iyhEdr/HbeWj83UyW3ltgAlT0XM/E5 X-Received: by 2002:a05:6a20:6a04:b0:f0:cef6:9d2e with SMTP id p4-20020a056a206a0400b000f0cef69d2emr13077224pzk.28.1683548626154; Mon, 08 May 2023 05:23:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548626; cv=none; d=google.com; s=arc-20160816; b=kJbH3NytwDvESLJYndtHGEQlnYGCZLTWpvrrYPGGO5UUvgqT7g8P3nkxAshbJC5wAS MrQ+ptcNmDbDrZB83vm3RBjXfxEUPGlq8KkFPM+YU766ozLs+8LyV8frl7MNquhQqk99 7SZx5kai+hhvLZN5QA56NyuS3bnzGCOYBShik3H/pfAA5J+QBhkNHXZ2w/E4y0VsVNYW cRrALVACAwVsaycE/r7I6sOm8rQzi8b3wlk+kjdcYTlpavrzXKQZRprDxKIUkxVoqETp b5m+RqQ3IyTuJYcyEsJLiguxYA6N5C4T/4n5IsHk+pzK7IUspTYsJH9DKn+4A8WiFJpG r/Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=d2h3vevkYkVu6ki2VA7HPdPz/xuNcH/E20UC4Fi6w3o=; b=H9dHdy1OPoTNvnf4pCogZmX3TqPyyLDO1GkUHm96bYlYVWLj97sCD1CPdXVUozsyZc +UjHXsQmp0GviNnZhLc1Ov2jXB+UhOIefOB7oaKXF3/0FK/csy9+DhFJJDBfel7303iB zr6bfY88IQguPz7GODyQ2dSNlDmU/PR8wWZMHODpNgZhPlA94r80rlDm7HHcxKYOpS5r 2wGi4ZJxrQL9lTCqPor1a1YD02A1r5elNFhFalZYjfjWkX6IrjkUpgrqwb7Ry4pqYp1u b7/DMQw7ZW+Ya/5WE+9t4Ebnmk1coLwizhZ6kJqnIR+/I8yI1EkE8xxYD+woq5uw/IHn vtOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=ZZntHeSb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:00 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V5 08/21] RISC-V: ACPI: Cache and retrieve the RINTC structure Date: Mon, 8 May 2023 17:22:24 +0530 Message-Id: <20230508115237.216337-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328684012901269?= X-GMAIL-MSGID: =?utf-8?q?1765328684012901269?= RINTC structures in the MADT provide mapping between the hartid and the CPU. This is required many times even at run time like cpuinfo. So, instead of parsing the ACPI table every time, cache the RINTC structures and provide a function to get the correct RINTC structure for a given cpu. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- arch/riscv/include/asm/acpi.h | 10 ++++++++ arch/riscv/kernel/acpi.c | 45 +++++++++++++++++++++++++++++++++++ arch/riscv/kernel/setup.c | 4 ++++ 3 files changed, 59 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 9be52b6ffae1..6519529c8bdf 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -59,6 +59,16 @@ static inline bool acpi_has_cpu_in_madt(void) static inline void arch_fix_phys_package_id(int num, u32 slot) { } +void acpi_init_rintc_map(void); +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); +u32 get_acpi_id_for_cpu(int cpu); +#else +static inline void acpi_init_rintc_map(void) { } +static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) +{ + return NULL; +} + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 81d448c41714..89e142611c84 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -24,6 +24,51 @@ EXPORT_SYMBOL(acpi_disabled); int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ EXPORT_SYMBOL(acpi_pci_disabled); +static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS]; + +static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) +{ + struct acpi_madt_rintc *rintc = (struct acpi_madt_rintc *)header; + int cpuid; + + if (!(rintc->flags & ACPI_MADT_ENABLED)) + return 0; + + cpuid = riscv_hartid_to_cpuid(rintc->hart_id); + /* + * When CONFIG_SMP is disabled, mapping won't be created for + * all cpus. + * CPUs more than num_possible_cpus, will be ignored. + */ + if (cpuid >= 0 && cpuid < num_possible_cpus()) + cpu_madt_rintc[cpuid] = *rintc; + + return 0; +} + +/* + * Instead of parsing (and freeing) the ACPI table, cache + * the RINTC structures since they are frequently used + * like in cpuinfo. + */ +void __init acpi_init_rintc_map(void) +{ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_madt_rintc, 0) <= 0) { + pr_err("No valid RINTC entries exist\n"); + BUG(); + } +} + +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) +{ + return &cpu_madt_rintc[cpu]; +} + +u32 get_acpi_id_for_cpu(int cpu) +{ + return acpi_cpu_get_madt_rintc(cpu)->uid; +} + /* * __acpi_map_table() will be called before paging_init(), so early_ioremap() * or early_memremap() should be called here to for ACPI table mapping. diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 9fb839074e16..a44c7fcde12f 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -293,6 +294,9 @@ void __init setup_arch(char **cmdline_p) setup_smp(); #endif + if (!acpi_disabled) + acpi_init_rintc_map(); + riscv_init_cbo_blocksizes(); riscv_fill_hwcap(); apply_boot_alternatives(); From patchwork Mon May 8 11:52:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91087 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2104802vqo; Mon, 8 May 2023 05:10:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5nbO2FgABKPwXiyUh+ACoDePdqOEQ5dgn9KhUst4ZaNzf52LzMtwwAeIr24w+NxyMq4xjw X-Received: by 2002:a05:6a21:1012:b0:ec:8859:7aa7 with SMTP id nk18-20020a056a21101200b000ec88597aa7mr9322804pzb.62.1683547858241; Mon, 08 May 2023 05:10:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683547858; cv=none; d=google.com; s=arc-20160816; b=MLmwVaheKbG5ZirL0A253MwWPGx3emN750B+a55qBntOyOByLp8SxSm/8BwGi+Yovc gxxaaEMlNVwD6N85e1mR1/Ydk3pSDu+IZujHEqKDkTXr68wf05c1Pyzs+Xy3r3GLBv+4 8VkywlPilg0Zc4PtYT3ojkCSjy76tO37sso/GllsHdi1+GSybxNb6Ph8JzN9LtmWkPQi BtyyBUjqBv3LNvTNJa5pFTGQA9aAyBBTZwNWBxquV3E7sqMbsqXodnjryKJtosoq5NR4 PYEjxeTQGRi5NYS9GTpQuqLf6IthF1NyQIgGDKmkQd9mSyEy+bV1Jlfqy7zYC/wNCK64 PSLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0nwVNZh7ok4nFqCGOtk3GB5ee+yA98GCkbh3FEbeZck=; b=fXR5A4ycDYQgFI+KYCAq0wU8YHuwHM3cqWmSttWrxTh5r/4dbuAAU3GztKFPrg8xZu nvfT2y0+nSOu7wkMs0VUaCzzdIOcn3EOgzSplKD+TugH1KSM52AyfsWgjKvoL9KQfFF1 E3E5qS12TgnqKkIRk0OvPJr5bajmJw4reReo9vf7CRlSETxRzxlwPuAd+v9riLVy6x+0 RK+VFES+wcd0zGUCRNqDo2KVysnqwU9UV9VJAsLQqGcb/0fdOUz1E4q4Jca0uPXPN3PK 0s9e4dIvnQ7o59/DLvAtrWvKfytKy2t9s5p52UZdbyEA2HVsrKB3+vwlsxNYKWWB2AGT kfQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=piWIkweC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:09 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Palmer Dabbelt Subject: [PATCH V5 09/21] drivers/acpi: RISC-V: Add RHCT related code Date: Mon, 8 May 2023 17:22:25 +0530 Message-Id: <20230508115237.216337-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765327878861473747?= X-GMAIL-MSGID: =?utf-8?q?1765327878861473747?= RHCT is a new table defined for RISC-V to communicate the features of the CPU to the OS. Create a new architecture folder in drivers/acpi and add RHCT parsing code. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/acpi.h | 8 ++++ drivers/acpi/Makefile | 2 + drivers/acpi/riscv/Makefile | 2 + drivers/acpi/riscv/rhct.c | 83 +++++++++++++++++++++++++++++++++++ 4 files changed, 95 insertions(+) create mode 100644 drivers/acpi/riscv/Makefile create mode 100644 drivers/acpi/riscv/rhct.c diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6519529c8bdf..39471759bec1 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -62,6 +62,8 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { } void acpi_init_rintc_map(void); struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); u32 get_acpi_id_for_cpu(int cpu); +int acpi_get_riscv_isa(struct acpi_table_header *table, + unsigned int cpu, const char **isa); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -69,6 +71,12 @@ static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) return NULL; } +static inline int acpi_get_riscv_isa(struct acpi_table_header *table, + unsigned int cpu, const char **isa) +{ + return -EINVAL; +} + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index feb36c0b9446..3fc5a0d54f6e 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -131,3 +131,5 @@ obj-y += dptf/ obj-$(CONFIG_ARM64) += arm64/ obj-$(CONFIG_ACPI_VIOT) += viot.o + +obj-$(CONFIG_RISCV) += riscv/ diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile new file mode 100644 index 000000000000..8b3b126e0b94 --- /dev/null +++ b/drivers/acpi/riscv/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += rhct.o diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c new file mode 100644 index 000000000000..b280b3e9c7d9 --- /dev/null +++ b/drivers/acpi/riscv/rhct.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022-2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#define pr_fmt(fmt) "ACPI: RHCT: " fmt + +#include + +static struct acpi_table_header *acpi_get_rhct(void) +{ + static struct acpi_table_header *rhct; + acpi_status status; + + /* + * RHCT will be used at runtime on every CPU, so we + * don't need to call acpi_put_table() to release the table mapping. + */ + if (!rhct) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) { + pr_warn_once("No RHCT table found\n"); + return NULL; + } + } + + return rhct; +} + +/* + * During early boot, the caller should call acpi_get_table() and pass its pointer to + * these functions(and free up later). At run time, since this table can be used + * multiple times, NULL may be passed in order to use the cached table. + */ +int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa) +{ + struct acpi_rhct_node_header *node, *ref_node, *end; + u32 size_hdr = sizeof(struct acpi_rhct_node_header); + u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info); + struct acpi_rhct_hart_info *hart_info; + struct acpi_rhct_isa_string *isa_node; + struct acpi_table_rhct *rhct; + u32 *hart_info_node_offset; + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + + BUG_ON(acpi_disabled); + + if (!table) { + rhct = (struct acpi_table_rhct *)acpi_get_rhct(); + if (!rhct) + return -ENOENT; + } else { + rhct = (struct acpi_table_rhct *)table; + } + + end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length); + + for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset); + node < end; + node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) { + if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) { + hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr); + hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo); + if (acpi_cpu_id != hart_info->uid) + continue; + + for (int i = 0; i < hart_info->num_offsets; i++) { + ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header, + rhct, hart_info_node_offset[i]); + if (ref_node->type == ACPI_RHCT_NODE_TYPE_ISA_STRING) { + isa_node = ACPI_ADD_PTR(struct acpi_rhct_isa_string, + ref_node, size_hdr); + *isa = isa_node->isa; + return 0; + } + } + } + } + + return -1; +} From patchwork Mon May 8 11:52:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91102 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2115671vqo; Mon, 8 May 2023 05:28:08 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5jjbjxqx5ie82Oif0HeE6UfUQ8TFs6i8M1E3kIUDTKxrPoX/Vdkz7QdbFP49Rp57xrWlVw X-Received: by 2002:a05:6a20:7347:b0:d6:7264:f44e with SMTP id v7-20020a056a20734700b000d67264f44emr13507240pzc.3.1683548887693; Mon, 08 May 2023 05:28:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548887; cv=none; d=google.com; s=arc-20160816; b=M38bKs74HsNJi+qQcTiCkp0G6tLomVyO/jBOhIwvkuUJYRiEQ0lPzv7e8u/SG5GEyz T1BFs21iBh7lFkWCrmIvhOCWaqNaPaQxZJtszJY7C9c7/eVl5nVzWJA/vZPzV1fZ9PFq PNifYUH5mymB0EdkXIIrEfu8d9VlKrGjokE658X+4g/mvuPJiTV1bq/J6LY8iWqXppOB 0bTalWwe5ZgIDm6Ysr3M1spbfq7Xs/cOLxkkW9NB1IHFgrMWmS5HLpUm5eLcaKcKii8n Np01IBWT+K8sxO+9mGhKwg0iGtLquFrOeytdIJbtxFvFu/h4Fpq0MBfx84X6XYG6BXcP PcNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yNB5noEZPasx/OngqcP7wy15OXtx85aYSDWecQ1qX3I=; b=PKq4+UMZK4hsXNnUrJgPCu/cjhYqfq0iILizACnEzS2v0H0clIRpqY2H/nEJoRMKfu yuF+YZygkRyFUlDhrDySqe+1YhDSq+6l1j/flt4jiaRxY0n+SZmqBec6Z3W++beziIxV XtJCoyTYxGDE9/XrjuzdZb9oaVzP9N89FOPuIhqLDY2LnX63XWBgjlURoXKjiwDC6WjH Gn35/4T+TmRQc7NUTyXBxNoBMbWj5Lv+kJQ2TwcWlhoWjnXexMkP7Fm7T4WpUegG7swi sG6DR/8tKVTN/C9KZs0/fQy4qmYu39RNv2fRYOM56kVFmf9Wf++BwX1alO2jueQMEALr wSRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=bdUOpEXd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:18 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Conor Dooley , Andrew Jones , Palmer Dabbelt Subject: [PATCH V5 10/21] RISC-V: smpboot: Create wrapper setup_smp() Date: Mon, 8 May 2023 17:22:26 +0530 Message-Id: <20230508115237.216337-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328958424265395?= X-GMAIL-MSGID: =?utf-8?q?1765328958424265395?= setup_smp() currently assumes DT-based platforms. To enable ACPI, first make this a wrapper function and move existing code to a separate DT-specific function. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt --- arch/riscv/kernel/smpboot.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 445a4efee267..a2e66126b733 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -70,7 +70,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } -void __init setup_smp(void) +static void __init of_parse_and_init_cpus(void) { struct device_node *dn; unsigned long hart; @@ -116,6 +116,11 @@ void __init setup_smp(void) } } +void __init setup_smp(void) +{ + of_parse_and_init_cpus(); +} + static int start_secondary_cpu(int cpu, struct task_struct *tidle) { if (cpu_ops[cpu]->cpu_start) From patchwork Mon May 8 11:52:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91093 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2114034vqo; Mon, 8 May 2023 05:25:09 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7MY/t8KmyGBGbd4a7YeCpMk4e0WpyWCtfS/ygjC8//BBVL39WSvR2YbYKuWz+DQqVmxKPk X-Received: by 2002:a05:6a00:ac2:b0:63d:2f13:200 with SMTP id c2-20020a056a000ac200b0063d2f130200mr15542801pfl.16.1683548709115; Mon, 08 May 2023 05:25:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548709; cv=none; d=google.com; s=arc-20160816; b=mrr3VM2HIMg9E3JAG4y2COpR2+j+P5GurB2o/fwNWzxJfLrFqIDF7/vTdaGG7KkZQX nvtnVEmStKqMJ86Ez04OgjloAeJFNjmLE9hR1CugqvWTtPuacm+7AHp9V/EeutuaRO8+ U8n4S0Lf5FSrcORHFjeMKX/OZDjKXasSti6g9YUHq/U+4hz7Zr+055p9RZIS3xftExrQ DwuoXBfhvTWNKqnpJmeaaIDeyepLRgOix9JAVj+P7TA7kFKa5heEaf11bjtKUKj52o5U 06IFFPf5+oORFtqegyl91I8PHOSzSXfmKj2XpZu6n+Zu8faWzwtDVDcV/3PZF8DchNcK RAPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xPSUnhfUj53RcidJeP5kL6gGwZHEmDmCHUal6KZm638=; b=VMryh+3V5jXSMErt9/QfVyema4/G0jpbQ0ual1TaAUbzusBCSuQU3k3M+6LXW8A8mE 7vgQDtNspN0RRbaYAAjsgLRRfp1XUPoAF4mv3Q/6LLtAGds2/T7+DYVcVX/Gz9y5meDu prqUGD4ORqdK+xciMSCSY/wSOQtkr0QwcG11e6PK/nv02nqz8xVtRARpz0Esm5JqmbCI 9ji5JzB8godY8iS649sL1UN+CRXvrZkgX47S+hu2X9HpnsmFhiwQWALUR95gSX/p8QAg wsnyASWDU9DQXvGuHDPqYkqke60DwXy/4O/0DDATjpjdf4ZoHPCJQ9vnkfC1IAvNDlKX qo2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=B89bgCvR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:26 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Conor Dooley , Andrew Jones Subject: [PATCH V5 11/21] RISC-V: smpboot: Add ACPI support in setup_smp() Date: Mon, 8 May 2023 17:22:27 +0530 Message-Id: <20230508115237.216337-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328771039994425?= X-GMAIL-MSGID: =?utf-8?q?1765328771039994425?= Enable SMP boot on ACPI based platforms by using the RINTC structures in the MADT table. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 2 + arch/riscv/kernel/smpboot.c | 72 ++++++++++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 39471759bec1..f71ce21ff684 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -64,6 +64,8 @@ struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); u32 get_acpi_id_for_cpu(int cpu); int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); + +static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index a2e66126b733..67bc5ef3e8b2 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -8,6 +8,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -70,6 +71,72 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } +#ifdef CONFIG_ACPI +static unsigned int cpu_count = 1; + +static int __init acpi_parse_rintc(union acpi_subtable_headers *header, const unsigned long end) +{ + unsigned long hart; + static bool found_boot_cpu; + struct acpi_madt_rintc *processor = (struct acpi_madt_rintc *)header; + + /* + * Each RINTC structure in MADT will have a flag. If ACPI_MADT_ENABLED + * bit in the flag is not enabled, it means OS should not try to enable + * the cpu to which RINTC belongs. + */ + if (!(processor->flags & ACPI_MADT_ENABLED)) + return 0; + + if (BAD_MADT_ENTRY(processor, end)) + return -EINVAL; + + acpi_table_print_madt_entry(&header->common); + + hart = processor->hart_id; + if (hart == INVALID_HARTID) { + pr_warn("Invalid hartid\n"); + return 0; + } + + if (hart == cpuid_to_hartid_map(0)) { + BUG_ON(found_boot_cpu); + found_boot_cpu = true; + early_map_cpu_to_node(0, acpi_numa_get_nid(cpu_count)); + return 0; + } + + if (cpu_count >= NR_CPUS) { + pr_warn("NR_CPUS is too small for the number of ACPI tables.\n"); + return 0; + } + + cpuid_to_hartid_map(cpu_count) = hart; + early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count)); + cpu_count++; + + return 0; +} + +static void __init acpi_parse_and_init_cpus(void) +{ + int cpuid; + + cpu_set_ops(0); + + acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_rintc, 0); + + for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++) { + if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID) { + cpu_set_ops(cpuid); + set_cpu_possible(cpuid, true); + } + } +} +#else +#define acpi_parse_and_init_cpus(...) do { } while (0) +#endif + static void __init of_parse_and_init_cpus(void) { struct device_node *dn; @@ -118,7 +185,10 @@ static void __init of_parse_and_init_cpus(void) void __init setup_smp(void) { - of_parse_and_init_cpus(); + if (acpi_disabled) + of_parse_and_init_cpus(); + else + acpi_parse_and_init_cpus(); } static int start_secondary_cpu(int cpu, struct task_struct *tidle) From patchwork Mon May 8 11:52:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91089 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2112812vqo; Mon, 8 May 2023 05:23:04 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7iHWyOWrvWiu4og9AjOM6ArtGdLrqo/CzTVpqVXWi+8brtjueSe//VQbacMtI42RWkp9hF X-Received: by 2002:a05:6a00:2183:b0:63f:cfd:5d10 with SMTP id h3-20020a056a00218300b0063f0cfd5d10mr12732081pfi.8.1683548584059; Mon, 08 May 2023 05:23:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548584; cv=none; d=google.com; s=arc-20160816; b=hHu1y4AsTQxcmMQ6H7e3F3VygCie0Gm8Au2DIPZV9mt7csd724Ev4pYBEUxZGL92Bl WCJYgrjr+qVLm7iPbegLN8PZOXYlIQfZU8Zc8FY7eWHLOLdq44Nm/JG8n8NlAxbQ4NVE F4w9Z9cJmspSEWYNhs9c/Bx9c/Jb16M9zlogoNwmprRWaCgcM14isQyauWPfICh/xZqo VuQM74943MJIa2mlT/L1IGqAZy5IIgU0k7Yr8/Dq7S2eb3iVoARCfIIqZwAqHysLm09n U4KUn7frGfnB37+YAuZbx3wtCNeGR4d6CoWp8GEhYNId+NJBatSk3DfD+LV7H7IksFwj fsrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/XDEVfXqS4FP0KdGTx6jL5yfIe6/oO8gDCIQfJ1eWZE=; b=fGKI5tIWb5yhOhIfYhR1CxOhhqbJgpL0Xabu4l5DPL+5pIjDmliBciTBk7Zl3Si+/n 7ROL2WL5L3fV2vZHaJSJgJ4DfM8x23dQEwzyco9N0ROUf6IAauhPr+T5f4Y9eP07Z1tz 3ASMO+8ehkep/K3JHAmP6WGhA27XB/f02dle3LNmx9/sM16fdhQWvYBUVpOOscN5BQja p7qvQacAhzEIQtKEvilad09I7SvfQQb/k2gPWoMjZ980J/CIMFc6dCq7PidXYn41Zx0n RkR3MToKskkY7xITlxo7z+Nw+QtnmQLTP/eNm9OB2of6o5VhflWO0GxAt/ocSmTnVqp6 rvJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=NcufZwwv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:34 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , Conor Dooley , Andrew Jones Subject: [PATCH V5 12/21] RISC-V: only iterate over possible CPUs in ISA string parser Date: Mon, 8 May 2023 17:22:28 +0530 Message-Id: <20230508115237.216337-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328640263062343?= X-GMAIL-MSGID: =?utf-8?q?1765328640263062343?= During boot we call riscv_of_processor_hartid() for each hart that we add to the possible cpus list. Repeating the call again here is not required, if we iterate over the list of possible CPUs, rather than the list of all CPUs. The call to of_property_read_string() for "riscv,isa" cannot fail either, as it has previously succeeded in riscv_of_processor_hartid(), but leaving in the error checking makes the operation of the loop more obvious & provides leeway for future refactoring of riscv_of_processor_hartid(). Signed-off-by: Sunil V L Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b1d6b7e4b829..c607db2c842c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -99,7 +100,7 @@ void __init riscv_fill_hwcap(void) char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; - unsigned long hartid; + unsigned int cpu; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -112,16 +113,20 @@ void __init riscv_fill_hwcap(void) bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); - for_each_of_cpu_node(node) { + for_each_possible_cpu(cpu) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; - rc = riscv_of_processor_hartid(node, &hartid); - if (rc < 0) + node = of_cpu_device_node_get(cpu); + if (!node) { + pr_warn("Unable to find cpu node\n"); continue; + } - if (of_property_read_string(node, "riscv,isa", &isa)) { + rc = of_property_read_string(node, "riscv,isa", &isa); + of_node_put(node); + if (rc) { pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); continue; } From patchwork Mon May 8 11:52:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91121 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2134764vqo; Mon, 8 May 2023 06:00:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6ndWx4FIIJCLTd2ge48B4Fzckh+6wxaMo+fVnYrL353y/VuBYyogoAei3+7g3BcMhhjr6Z X-Received: by 2002:a05:6a20:7d83:b0:100:a6ba:ba1b with SMTP id v3-20020a056a207d8300b00100a6baba1bmr2918101pzj.51.1683550837553; Mon, 08 May 2023 06:00:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683550837; cv=none; d=google.com; s=arc-20160816; b=t6ggctbhhRljTQFHiL+DVdoVl8nBTjBYdt7GYbakbochYcoMVJ6+EA0BanMTNGYm0+ ZbSo1c3WMxPsbWyQi8KNLJAEfL3U4KQfJXIYNqf9a7+dZx7ChhZ+dfxqcEsB6Ox48hQW Ffgf+HINIFm4f9jyaRkkwYtlNcX79G2wVjlqk30EV63DJ6GY2rCNA96rVk3g4pWE04xc 6Lh+Isp4Pa2I3Fzkg1lymbAW1sENN0aW7T1azmPOYplU8GPl5JZdJrtlr7YtzJuiXkcI 9ckhSUHCi40ULbtkIjbsP+qz8L7t5qJTwEVDyw28fuMP6GDl1PaBiFS0b0MbslZTSYe7 TlIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fWBNL8Yoxn6F5OA39mGQO+nKX7WWRbncPVBB9F2/Cag=; b=O6zyOPNYqGWjTvQkax97cMDq+gJRIkAkLNcxOMvEeDjyo5wG8C4rrkIDQzlw/5RyJI 4oelhH8sySbrebapqV9wNh31horUtIH3ghTe31JaEVK16M/b9JbQg2VjITys2xeHDPZH jOI2+8lzitOUlaB2i0Y9/a3QzVHJMgbdilyKX2eDY4dhgYs7v3N5N3n1zwwiWFJ3HRW1 lwfZ+29JAPzxVYU7+pjfSOugZQqXCUObNuVNCjKF1obDOJ9Q88NnFo1HbboRsMDqaY2k zxnPFFFNsz0IbC1HKmJHUJfc6dnpq913exJJq97U8XQ/GdaxLn6HFb9tW/C/I+orAB3Z a6Lw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=UTsXWuWm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 13/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Date: Mon, 8 May 2023 17:22:29 +0530 Message-Id: <20230508115237.216337-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765331002778865236?= X-GMAIL-MSGID: =?utf-8?q?1765331002778865236?= On ACPI based systems, the information about the hart like ISA is provided by the RISC-V Hart Capabilities Table (RHCT). Enable filling up hwcap structure based on the information in RHCT. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c607db2c842c..6ba8e20c5346 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -6,6 +6,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -100,6 +102,8 @@ void __init riscv_fill_hwcap(void) char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; + struct acpi_table_header *rhct; + acpi_status status; unsigned int cpu; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; @@ -113,22 +117,36 @@ void __init riscv_fill_hwcap(void) bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); + if (!acpi_disabled) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) + return; + } + for_each_possible_cpu(cpu) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; - node = of_cpu_device_node_get(cpu); - if (!node) { - pr_warn("Unable to find cpu node\n"); - continue; - } + if (acpi_disabled) { + node = of_cpu_device_node_get(cpu); + if (!node) { + pr_warn("Unable to find cpu node\n"); + continue; + } - rc = of_property_read_string(node, "riscv,isa", &isa); - of_node_put(node); - if (rc) { - pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); - continue; + rc = of_property_read_string(node, "riscv,isa", &isa); + of_node_put(node); + if (rc) { + pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); + continue; + } + } else { + rc = acpi_get_riscv_isa(rhct, cpu, &isa); + if (rc < 0) { + pr_warn("Unable to get ISA for the hart - %d\n", cpu); + continue; + } } temp = isa; @@ -265,6 +283,9 @@ void __init riscv_fill_hwcap(void) bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); } + if (!acpi_disabled && rhct) + acpi_put_table((struct acpi_table_header *)rhct); + /* We don't support systems with F but without D, so mask those out * here. */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { From patchwork Mon May 8 11:52:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91106 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2117036vqo; Mon, 8 May 2023 05:30:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ58zFKklO2U+CdPWj6CwRBbYb0ejl/17m18kP0qJxjVtLs9oNm9goQGa5JPk4PtwRMTV7I5 X-Received: by 2002:a17:902:8c96:b0:1a9:631b:7d68 with SMTP id t22-20020a1709028c9600b001a9631b7d68mr9053563plo.8.1683549034444; Mon, 08 May 2023 05:30:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683549034; cv=none; d=google.com; s=arc-20160816; b=AVBUJ+NbJ7LUoyttkC+XgjsjgQfbinpMd0omd4+wnDh0/mOVd0FnWqJS91wnbMkhLA JUB50S+yQbly3L7bn/KM/VH7iSlTsX236KZin/7AcKP5qHZl/6QHUnTxGFu/CtNSp3Ez UVeqMdytKYruWkfK8Hi247ZbMwPI13PSbGgPRAUvRbqq8x5JMbC9asYtzrqLgoF7q4tm 7IoF/MxP15kLF0hdHmmhslxH7VI9sPH/268jdR/Gf+tZBLWZxBZy1GOmEZkmHJ8MdXGC 0JlSzblJpRX0RAbWCurrpL/QfFfcKelyX0YxAyx4u9wlDv0SzlGwYb3Hrl6/oH7Qj9LY xZDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VyhfCZ5csOlZFGV4bhDymGpgdY5PFJC+Se96opk/VAw=; b=QY57aYwd2NI2JaStMP/kwIxQTz0D2wZVLgOxBscILt+SVdQIcBY9u8EtmN9004xP1k 5DOBuAJOZD68jd3QNiEnwaC6AUsy94+bM0XQQh4Y9NHbsU2uw1kn5fwqggNtBwRm5hHr 9j73v/RIx6uOv5RQV/nZaFuvDfez+9g/0tGb2VdvRU+ujqMYvzuk3MPxhXCG0cUpji7q madWHeCG9CMCUXNLwRu0MbP/D4s+1ziFyeUhn7scebuyCOAJXSmM8HKKLfThcxTFbkD/ uCZzhZagFJw0P/hadTqzwlqhh3qYHWBcTm+cBznkHDGRXR0U9tzN65erH7+pK16BuuMQ 6bJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=mZVolCAz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:51 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 14/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Date: Mon, 8 May 2023 17:22:30 +0530 Message-Id: <20230508115237.216337-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765329112006876657?= X-GMAIL-MSGID: =?utf-8?q?1765329112006876657?= On ACPI based platforms, few details like ISA need to be read from the ACPI table. Enable cpuinfo on ACPI based systems. ACPI has nothing similar to DT compatible property for each CPU. Hence, cpuinfo will not print "uarch". Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index c96aa56cf1c7..5de6fb703cc2 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -3,10 +3,12 @@ * Copyright (C) 2012 Regents of the University of California */ +#include #include #include #include #include +#include #include #include #include @@ -283,23 +285,35 @@ static void c_stop(struct seq_file *m, void *v) static int c_show(struct seq_file *m, void *v) { unsigned long cpu_id = (unsigned long)v - 1; - struct device_node *node = of_get_cpu_node(cpu_id, NULL); struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); + struct device_node *node; const char *compat, *isa; seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); - print_mmu(m); - if (!of_property_read_string(node, "compatible", &compat) - && strcmp(compat, "riscv")) - seq_printf(m, "uarch\t\t: %s\n", compat); + + if (acpi_disabled) { + node = of_get_cpu_node(cpu_id, NULL); + if (!of_property_read_string(node, "riscv,isa", &isa)) + print_isa(m, isa); + + print_mmu(m); + if (!of_property_read_string(node, "compatible", &compat) && + strcmp(compat, "riscv")) + seq_printf(m, "uarch\t\t: %s\n", compat); + + of_node_put(node); + } else { + if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) + print_isa(m, isa); + + print_mmu(m); + } + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); seq_puts(m, "\n"); - of_node_put(node); return 0; } From patchwork Mon May 8 11:52:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91101 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2115526vqo; Mon, 8 May 2023 05:27:48 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4LWFO8e3l0HUNZ9TnE8iPPAO36p+d32SzQvq7eAZ5YntpovLSlCs2tsdHDTqO5xul5aBkJ X-Received: by 2002:a17:902:f7d6:b0:1a9:f425:5409 with SMTP id h22-20020a170902f7d600b001a9f4255409mr10523044plw.49.1683548868340; Mon, 08 May 2023 05:27:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548868; cv=none; d=google.com; s=arc-20160816; b=H0zNFEjDYULRXEt53qZYKsNc5Wd+1P+9TbEW7fnAd9+IlUQ9pR4AX3WQ8e1cwiw+Bl yKY4osFs/o/+DrfvtBeTsEhP/ZBKmy2k3vyPkfdjM/apMAcg03XNzjrnJJ57tAfws41f 6JV3r801lYnwdCrfIHeJzKKlU9pZIt/oamys9hi0+h2Eq8tBBtwC7I+y1VhpjUjTnxAk ngpMuMuuSUDFqYYtTVEOSvWB0GAzIUeX67fioEl331sKfKnXAfvG0fU8/nTy6/vsWxej ma3qgvzahZNRHKpkCV3NJqFqU2lARy3rUFx+4niE8BihSuqGm7mkb3Jjlz3QKrYRp+wf qdUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GSuTggFYj3JSbFizfFEsySbatkGCHwC0oNgPzvEucIg=; b=PF9nmy3dt+cZWfPj/OQTsYn9ZlTEukt/DDgHJZ6n4Lh36MZj3EYWXUILmVKMJXm9p6 RJMywrJTetRC5qfj5oMvsDdJWSOHATtpn0O+lPrR2/o41SbBDvCyzKnPtt+oFJ7tMZ0n a92TunPl3ee8bHenv8auZMDF4qsAUfVMQSMkq2O/hq+Ex5TYnJ0fYxWgPGtfVCkc5den S4QVaRXX+GzVkTmG4BgnUQ3EPC2JPnq2JdW7HGsekDCbmlcXBY/Tnb8LiMbMjN7QW4ND 9D8s320Gl4mOMj7D4Q+IkUQ7hizxD3Dk83LoNVCjES9Ob6aT2sNDB2l8ULLZtPp9FUYj uLug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=OwnBVNyw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:59 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 15/21] irqchip/riscv-intc: Add ACPI support Date: Mon, 8 May 2023 17:22:31 +0530 Message-Id: <20230508115237.216337-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328938142442043?= X-GMAIL-MSGID: =?utf-8?q?1765328938142442043?= Add support for initializing the RISC-V INTC driver on ACPI platforms. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/irqchip/irq-riscv-intc.c | 70 +++++++++++++++++++++++++------- 1 file changed, 55 insertions(+), 15 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index f229e3e66387..4adeee1bc391 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -6,6 +6,7 @@ */ #define pr_fmt(fmt) "riscv-intc: " fmt +#include #include #include #include @@ -112,6 +113,30 @@ static struct fwnode_handle *riscv_intc_hwnode(void) return intc_domain->fwnode; } +static int __init riscv_intc_init_common(struct fwnode_handle *fn) +{ + int rc; + + intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, + &riscv_intc_domain_ops, NULL); + if (!intc_domain) { + pr_err("unable to add IRQ domain\n"); + return -ENXIO; + } + + rc = set_handle_irq(&riscv_intc_irq); + if (rc) { + pr_err("failed to set irq handler\n"); + return rc; + } + + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + + pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + + return 0; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -133,24 +158,39 @@ static int __init riscv_intc_init(struct device_node *node, if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) return 0; - intc_domain = irq_domain_add_linear(node, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); - if (!intc_domain) { - pr_err("unable to add IRQ domain\n"); - return -ENXIO; - } + return riscv_intc_init_common(of_node_to_fwnode(node)); +} - rc = set_handle_irq(&riscv_intc_irq); - if (rc) { - pr_err("failed to set irq handler\n"); - return rc; - } +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); - riscv_set_intc_hwnode_fn(riscv_intc_hwnode); +#ifdef CONFIG_ACPI - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); +static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct fwnode_handle *fn; + struct acpi_madt_rintc *rintc; - return 0; + rintc = (struct acpi_madt_rintc *)header; + + /* + * The ACPI MADT will have one INTC for each CPU (or HART) + * so riscv_intc_acpi_init() function will be called once + * for each INTC. We only do INTC initialization + * for the INTC belonging to the boot CPU (or boot HART). + */ + if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id()) + return 0; + + fn = irq_domain_alloc_named_fwnode("RISCV-INTC"); + if (!fn) { + pr_err("unable to allocate INTC FW node\n"); + return -ENOMEM; + } + + return riscv_intc_init_common(fn); } -IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, + ACPI_MADT_RINTC_VERSION_V1, riscv_intc_acpi_init); +#endif From patchwork Mon May 8 11:52:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91092 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2113840vqo; Mon, 8 May 2023 05:24:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5hrmi5cveLopBCkNDw5CJOABq8Hh/CvJkQAHDS2v4eoNoAdxc4idtAYnrAdb4lq8wQlfmJ X-Received: by 2002:a17:903:48e:b0:1a2:a904:c438 with SMTP id jj14-20020a170903048e00b001a2a904c438mr10007490plb.58.1683548689647; Mon, 08 May 2023 05:24:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548689; cv=none; d=google.com; s=arc-20160816; b=i8nhCF7oejTb7gwK/guxo+SbPucyGYvCzpGSvb9wgAGVd3P5NdruLwSjy0dAx+swce cnE+8GIhKHuuKRMjm+vMRJLj048s/anhCkaRCHfh7xpkd4jJ3drRx2WfUCdryqb2U9iW SAIsYwcdcpyLRt3cnsO+Agoqnr+isdlvuu6BXbLiBY4DqR4tS7DmmGLfIZSlgguEhhtm NpVa1qcT5gb9shnUGUhxJR55GmahTPWhzlfPsM3KCFKdxR9Gi5kKlErgWkyJVTRcXPfa Et3BhggX9aSWmRc3EFgppkHSQt0YRfQdL/LcbzJ+ipFkImE1+mlQb4Pr/S/XvNhQWIK5 0iTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IS1GWILYl7Q6QsdApEh939z6h09NwhOHpvU6XTgdfRk=; b=utX8GMNwIQnyB4qhqXNLL4WDneII3Gm8ThUPjug49oGC2yxOJ4uGyzXAk+c85sMb/o TFMvVk1VY8zqbKYrswfDFux/F9ikaLGeXIxFuMgtq+J78Xnlm2H5/tD6gZAwJSFSwM6t Toe+mFlwQUWhzPyP+rZwduH0gYkQC6JGFdXZ4FwQFwM560KDI8fCsdPytJgaIaXLsyqJ HUtPYvhZ5InOptPfnCvHXw6Aug6BaOLmyeTPF2Wa6qntnzuHedOI+lDo9FgrH5iLJ6Mq KDziRRdo1xzDHpkTCHdQkzAL9Uc9exMTMwqpB3IwjvvBCnXb3N5Io4zLCnBgRfqbK1j8 GJPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=eJP89kRr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:07 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , Anup Patel , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 16/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Date: Mon, 8 May 2023 17:22:32 +0530 Message-Id: <20230508115237.216337-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328750998312101?= X-GMAIL-MSGID: =?utf-8?q?1765328750998312101?= Refactor the timer init function such that few things can be shared by both DT and ACPI based platforms. Co-developed-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/clocksource/timer-riscv.c | 81 +++++++++++++++---------------- 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5f0f10c7e222..cecc4662293b 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -124,61 +124,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init riscv_timer_init_dt(struct device_node *n) +static int __init riscv_timer_init_common(void) { - int cpuid, error; - unsigned long hartid; - struct device_node *child; + int error; struct irq_domain *domain; + struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode(); - error = riscv_of_processor_hartid(n, &hartid); - if (error < 0) { - pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", - n, hartid); - return error; - } - - cpuid = riscv_hartid_to_cpuid(hartid); - if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); - return cpuid; - } - - if (cpuid != smp_processor_id()) - return 0; - - child = of_find_compatible_node(NULL, NULL, "riscv,timer"); - if (child) { - riscv_timer_cannot_wake_cpu = of_property_read_bool(child, - "riscv,timer-cannot-wake-cpu"); - of_node_put(child); - } - - domain = NULL; - child = of_get_compatible_child(n, "riscv,cpu-intc"); - if (!child) { - pr_err("Failed to find INTC node [%pOF]\n", n); - return -ENODEV; - } - domain = irq_find_host(child); - of_node_put(child); + domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY); if (!domain) { - pr_err("Failed to find IRQ domain for node [%pOF]\n", n); + pr_err("Failed to find irq_domain for INTC node [%pfwP]\n", + intc_fwnode); return -ENODEV; } riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER); if (!riscv_clock_event_irq) { - pr_err("Failed to map timer interrupt for node [%pOF]\n", n); + pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode); return -ENODEV; } - pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", - __func__, cpuid, hartid); error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", - error, cpuid); + pr_err("RISCV timer registration failed [%d]\n", error); return error; } @@ -207,4 +174,36 @@ static int __init riscv_timer_init_dt(struct device_node *n) return error; } +static int __init riscv_timer_init_dt(struct device_node *n) +{ + int cpuid, error; + unsigned long hartid; + struct device_node *child; + + error = riscv_of_processor_hartid(n, &hartid); + if (error < 0) { + pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n", + n, hartid); + return error; + } + + cpuid = riscv_hartid_to_cpuid(hartid); + if (cpuid < 0) { + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); + return cpuid; + } + + if (cpuid != smp_processor_id()) + return 0; + + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cannot_wake_cpu = of_property_read_bool(child, + "riscv,timer-cannot-wake-cpu"); + of_node_put(child); + } + + return riscv_timer_init_common(); +} + TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); From patchwork Mon May 8 11:52:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91104 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2116284vqo; Mon, 8 May 2023 05:29:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5bG6x694cNh6sd5GH+K7LU39qy7NbZDb6q4zRtIyqCca+lyifWEFoCVv/RA7vhf0Qh5XIL X-Received: by 2002:a17:90a:a683:b0:23e:f855:79ed with SMTP id d3-20020a17090aa68300b0023ef85579edmr10588125pjq.28.1683548956797; Mon, 08 May 2023 05:29:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548956; cv=none; d=google.com; s=arc-20160816; b=X9Ut5I6l1IoDDv5Yg3UpgjzKQV4YwMtZx2KKguyczxkH9sS/SN/Uw3df14pbFsW1oM /DEOxQMw/vgjW2SEMtrwW2lPGxbMIjIfSfNZbfH0ekHjJi0iGnU0AVih9l0fUOAhTWUk tMb1JAQAhxsk2cm5wd3PPKsJdTAUPWnghA4Z1Rq5GGL1PZOu6hC8E0Pi79S+9mnH7K3D SSY/HJYZsb9Q+tUmLHIT2xbKVjIOyMkTxaGj6UYnQsIsGUaFeFFuWvCySYvoHPeUwLnC e2R2PWCosEpzQHJw7zp8mYu2HeyAhD+9fQkfRMi+LfW0Ee/BZXh3e/GCZDuSplpolXxb SjOA== ARC-Message-Signature: i=1; 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Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 17/21] clocksource/timer-riscv: Add ACPI support Date: Mon, 8 May 2023 17:22:33 +0530 Message-Id: <20230508115237.216337-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765329031045203183?= X-GMAIL-MSGID: =?utf-8?q?1765329031045203183?= Initialize the timer driver based on RHCT table on ACPI based platforms. Currently, ACPI doesn't support a flag to indicate that the timer interrupt can wake up the cpu irrespective of its power state. It will be added in future update. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/clocksource/timer-riscv.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index cecc4662293b..da3071b387eb 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) "riscv-timer: " fmt +#include #include #include #include @@ -207,3 +208,13 @@ static int __init riscv_timer_init_dt(struct device_node *n) } TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); + +#ifdef CONFIG_ACPI +static int __init riscv_timer_acpi_init(struct acpi_table_header *table) +{ + return riscv_timer_init_common(); +} + +TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init); + +#endif From patchwork Mon May 8 11:52:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91098 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2115072vqo; Mon, 8 May 2023 05:27:01 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7WrrtyRH0GJogNkVAekTHVBvhoVovYqbvC1Zw3QpB0TNzWp8EKrtyE0MQdp0MfuvIf3O7j X-Received: by 2002:a05:6a00:13a8:b0:63d:6744:8cae with SMTP id t40-20020a056a0013a800b0063d67448caemr12890728pfg.2.1683548821374; Mon, 08 May 2023 05:27:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548821; cv=none; d=google.com; s=arc-20160816; b=bxlYbPdTO7kOa38LYJUNjl75U+MuaNA9/DZeM/pLFPL/iNhpYeO0t/MlGniYZVDpcB qKLA0H+20eFJcJ4WG+4GIWv6GG75Wvl6kQOmRJZxh+Ll2kCBpwNpifGYHw8Ek1Q0b1iE CCzQD71d24pS/l2RxezC/uWHtlRrHCuTmOiAMdcSN4Q7V6RQQjGwQ4j7vDIhX8efuWV5 /K+S88xpfZGz4rrvB74WFm4PzeAAPv5OhL4lXq1yN+7Qy+Nvo6JZtd9y/WP1T3hjd1Le dMjzSSYRpbhvyx40TvUMuBC2xiONxJr0FpCVWHbocUmyaD7WCZpcNf1YGeNaBHKr2q3J G5gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yRIRI8aArNgE1fextAvbnFu2fBTu5X0gP4d56RcrLtU=; b=NiWakDDoAYtkpri/wlqw5mSrl39oz1AGu2hxJSYIVojwzyBeGU5alxBCx4gaZbj7/w 79sZ5izOwzo9TG6+vIIVdZEDZ/7yHTeaUosC0nU1o9tGYgKUlFwDtdI3+YwUzn4GTf51 rPGpMl4Bdj7h79K4AYxmSQsCA5b1WlXaxBbBLjrU6W+MM7z8uw7PqFhoKzjUd01xjSC5 GVLHXzQG4eEA8oDLVYiCs+2kzMaf3ReImImG+Y6HkPvfr1vxrq2aK/MGsGqGFvw/a5yL /gulKBLiw6zE8Q+hHc5nWFJdzL6601Y4gmKctZTjVMvpFD/N5/V8CH8EMCyVpE1XjsJO PREA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=dPMbOuJs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:23 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 18/21] RISC-V: time.c: Add ACPI support for time_init() Date: Mon, 8 May 2023 17:22:34 +0530 Message-Id: <20230508115237.216337-19-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328888662982043?= X-GMAIL-MSGID: =?utf-8?q?1765328888662982043?= On ACPI based platforms, timer related information is available in RHCT. Add ACPI based probe support to the timer initialization. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/time.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index babaf3b48ba8..23641e82a9df 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -4,6 +4,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -18,17 +19,29 @@ EXPORT_SYMBOL_GPL(riscv_timebase); void __init time_init(void) { struct device_node *cpu; + struct acpi_table_rhct *rhct; + acpi_status status; u32 prop; - cpu = of_find_node_by_path("/cpus"); - if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) - panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n"); - of_node_put(cpu); - riscv_timebase = prop; + if (acpi_disabled) { + cpu = of_find_node_by_path("/cpus"); + if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) + panic("RISC-V system with no 'timebase-frequency' in DTS\n"); + + of_node_put(cpu); + riscv_timebase = prop; + of_clk_init(NULL); + } else { + status = acpi_get_table(ACPI_SIG_RHCT, 0, (struct acpi_table_header **)&rhct); + if (ACPI_FAILURE(status)) + panic("RISC-V ACPI system with no RHCT table\n"); + + riscv_timebase = rhct->time_base_freq; + acpi_put_table((struct acpi_table_header *)rhct); + } lpj_fine = riscv_timebase / HZ; - of_clk_init(NULL); timer_probe(); tick_setup_hrtimer_broadcast(); From patchwork Mon May 8 11:52:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91094 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2114051vqo; Mon, 8 May 2023 05:25:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6TxdykGZwrfdRbxkDK50Ca/Vy1xuABAtrN+hd7htATN+yLZvHaWKjeM95Me5717YiJnyRa X-Received: by 2002:a05:6a21:3393:b0:ff:7e58:c232 with SMTP id yy19-20020a056a21339300b000ff7e58c232mr4555054pzb.39.1683548711240; Mon, 08 May 2023 05:25:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548711; cv=none; d=google.com; s=arc-20160816; b=fSWJwSuLX2rNTuSpDag4uuZ2+KFy7xxN3eSFJKrOPMcPY67WyE3zcBE0KN/F9q4LBu KCIO8dxQx5jYtNzkmTBwppptpmhr8Ydm96+aycpGCH+tqErI1N7XHkW4jItqVckcy64q yZAHPlkhQSXe2v+wn5Xro8bqg698WANm52dLGdwhx1jOqhV4UomBtS9ADRxhZGcnUFAv kYvqapW1sJAmQXzQbeBw3KtM5VvismUOBeveJFDfyzHqXvkF0wkjHrgG+fCBT9hIWAuw RSjC8J7NiyvtN3a28qcQ+jrpPGv+zsFtxtwbumjjLvZw7oYGYaDZor4lA8sA+oFEIVJ0 kZ+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AKIAPMXrXfzkk8IX1ewOX27TBpicUwrq64VdyI20DAw=; b=KXtgdNjhkYUnRB5mQhucH7aN7ASHwKdPcD/LbJb2U3+MNKxxM7tvl9oU3zjpHbIAxP QBK20JVpOJQ42p1lplYj0bOIlQIFYkJeXtl//26LMaWtDKsWBT5NZvCtyv7CzmMHIEKR qeWz9JOqnqqZad90YiiVIxnnTUJR4vUQ3vVrfXsPn2IHKiMEgGlgnEZBQC91eafbm1nl d2jyORyj3HKkLD7RjF1XC4upbLvtqLUv3L+yuXMHafodvPqeTEy+5XxI0VbdEfCYUqQb vw+PaMXcjHA0CRH9njpSI/w/2qMANVYSfjbnSuEwmV1JLXZn5aRDXeipReFhPjsKmgY1 OBUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=KpgNJW0k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:32 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 19/21] RISC-V: Add ACPI initialization in setup_arch() Date: Mon, 8 May 2023 17:22:35 +0530 Message-Id: <20230508115237.216337-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328773446776850?= X-GMAIL-MSGID: =?utf-8?q?1765328773446776850?= Initialize the ACPI core for RISC-V during boot. ACPI tables and interpreter are initialized based on the information passed from the firmware and the value of the kernel parameter 'acpi'. With ACPI support added for RISC-V, the kernel parameter 'acpi' is also supported on RISC-V. Hence, update the documentation. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Acked-by: Conor Dooley --- .../admin-guide/kernel-parameters.txt | 8 +- arch/riscv/kernel/acpi.c | 125 ++++++++++++++++++ arch/riscv/kernel/setup.c | 5 + 3 files changed, 134 insertions(+), 4 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 9e5bab29685f..d910fba25f2c 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1,17 +1,17 @@ - acpi= [HW,ACPI,X86,ARM64] + acpi= [HW,ACPI,X86,ARM64,RISCV64] Advanced Configuration and Power Interface Format: { force | on | off | strict | noirq | rsdt | copy_dsdt } force -- enable ACPI if default was off - on -- enable ACPI but allow fallback to DT [arm64] + on -- enable ACPI but allow fallback to DT [arm64,riscv64] off -- disable ACPI if default was on noirq -- do not use ACPI for IRQ routing strict -- Be less tolerant of platforms that are not strictly ACPI specification compliant. rsdt -- prefer RSDT over (default) XSDT copy_dsdt -- copy DSDT to memory - For ARM64, ONLY "acpi=off", "acpi=on" or "acpi=force" - are available + For ARM64 and RISCV64, ONLY "acpi=off", "acpi=on" or + "acpi=force" are available See also Documentation/power/runtime_pm.rst, pci=noacpi diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 89e142611c84..93f643f8d763 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -16,6 +16,7 @@ #include #include #include +#include int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -25,6 +26,130 @@ int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ EXPORT_SYMBOL(acpi_pci_disabled); static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS]; +static bool param_acpi_off __initdata; +static bool param_acpi_on __initdata; +static bool param_acpi_force __initdata; + +static int __init parse_acpi(char *arg) +{ + if (!arg) + return -EINVAL; + + /* "acpi=off" disables both ACPI table parsing and interpreter */ + if (strcmp(arg, "off") == 0) + param_acpi_off = true; + else if (strcmp(arg, "on") == 0) /* prefer ACPI over DT */ + param_acpi_on = true; + else if (strcmp(arg, "force") == 0) /* force ACPI to be enabled */ + param_acpi_force = true; + else + return -EINVAL; /* Core will print when we return error */ + + return 0; +} +early_param("acpi", parse_acpi); + +/* + * acpi_fadt_sanity_check() - Check FADT presence and carry out sanity + * checks on it + * + * Return 0 on success, <0 on failure + */ +static int __init acpi_fadt_sanity_check(void) +{ + struct acpi_table_header *table; + struct acpi_table_fadt *fadt; + acpi_status status; + int ret = 0; + + /* + * FADT is required on riscv; retrieve it to check its presence + * and carry out revision and ACPI HW reduced compliancy tests + */ + status = acpi_get_table(ACPI_SIG_FADT, 0, &table); + if (ACPI_FAILURE(status)) { + const char *msg = acpi_format_exception(status); + + pr_err("Failed to get FADT table, %s\n", msg); + return -ENODEV; + } + + fadt = (struct acpi_table_fadt *)table; + + /* + * The revision in the table header is the FADT's Major revision. The + * FADT also has a minor revision, which is stored in the FADT itself. + * + * TODO: Currently, we check for 6.5 as the minimum version to check + * for HW_REDUCED flag. However, once RISC-V updates are released in + * the ACPI spec, we need to update this check for exact minor revision + */ + if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 5)) + pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.5+\n", + table->revision, fadt->minor_revision); + + if (!(fadt->flags & ACPI_FADT_HW_REDUCED)) { + pr_err("FADT not ACPI hardware reduced compliant\n"); + ret = -EINVAL; + } + + /* + * acpi_get_table() creates FADT table mapping that + * should be released after parsing and before resuming boot + */ + acpi_put_table(table); + return ret; +} + +/* + * acpi_boot_table_init() called from setup_arch(), always. + * 1. find RSDP and get its address, and then find XSDT + * 2. extract all tables and checksums them all + * 3. check ACPI FADT HW reduced flag + * + * We can parse ACPI boot-time tables such as MADT after + * this function is called. + * + * On return ACPI is enabled if either: + * + * - ACPI tables are initialized and sanity checks passed + * - acpi=force was passed in the command line and ACPI was not disabled + * explicitly through acpi=off command line parameter + * + * ACPI is disabled on function return otherwise + */ +void __init acpi_boot_table_init(void) +{ + /* + * Enable ACPI instead of device tree unless + * - ACPI has been disabled explicitly (acpi=off), or + * - firmware has not populated ACPI ptr in EFI system table + * and ACPI has not been [force] enabled (acpi=on|force) + */ + if (param_acpi_off || + (!param_acpi_on && !param_acpi_force && + efi.acpi20 == EFI_INVALID_TABLE_ADDR)) + return; + + /* + * ACPI is disabled at this point. Enable it in order to parse + * the ACPI tables and carry out sanity checks + */ + enable_acpi(); + + /* + * If ACPI tables are initialized and FADT sanity checks passed, + * leave ACPI enabled and carry on booting; otherwise disable ACPI + * on initialization error. + * If acpi=force was passed on the command line it forces ACPI + * to be enabled even if its initialization failed. + */ + if (acpi_table_init() || acpi_fadt_sanity_check()) { + pr_err("Failed to init ACPI tables\n"); + if (!param_acpi_force) + disable_acpi(); + } +} static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) { diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index a44c7fcde12f..2ab4cdaa2e68 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -8,6 +8,7 @@ * Nick Kossifidis */ +#include #include #include #include @@ -277,6 +278,10 @@ void __init setup_arch(char **cmdline_p) efi_init(); paging_init(); + + /* Parse the ACPI tables for possible boot-time configuration */ + acpi_boot_table_init(); + #if IS_ENABLED(CONFIG_BUILTIN_DTB) unflatten_and_copy_device_tree(); #else From patchwork Mon May 8 11:52:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91116 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2128771vqo; Mon, 8 May 2023 05:49:19 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5hwfAmffOsScb4LwMGsjzpqEFApLtwtxX6xinwXbgd5rhvg+eWvk7HVaK6Yfd+eVVvUeVe X-Received: by 2002:a05:6a20:12c7:b0:ef:511:d6fe with SMTP id v7-20020a056a2012c700b000ef0511d6femr14159755pzg.9.1683550159273; Mon, 08 May 2023 05:49:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683550159; cv=none; d=google.com; s=arc-20160816; b=l0982PjIAAi5STZ7M6AvGt741PM2Xsg5mOKUTN0eM1FS8j88nLNZCRXI0Z2jYYL4Xp hzwSZ1Up0UPx/u0VRbb38IXX/fYbOQtYBj6Qb4cpiKFAdUD6xVYgGSl7503SuzJRiNXT JKksllEHNOfvbNolsVOQLQMeaLdLP/ljzXsaEs3GU+Q9jVNWnJZ/0uL4+sWFQf84QVHJ /hwOaT129wfFB+h9Kr8IdYDHgVTQjSp7mh3f1oEV1O8aDwBcps1UPeVKALXWEv4T60Cd gCWnDxrtgkzjPG/QWEeBavdIGZSNUgaRL3XC6qwwYcr8L/XQFs4MMOaCKJQxTVDxYBGO JbFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=38k1Pzb7K1cfn0j2an7l+ypiTAB8VfWPvQzIb1c40CU=; b=029HAu5w0mGfH6eWHx24JPsiHuz/q+qMnXQ6bnA59alSufeBjOPyCh7jwF12I5bzFT IXaXvp2tYcakq+TzpSVaZFFVYmFjsDAGEzG3W7PbHbzSa/6PDF5zK8FmVPKBHNZCSwye bGGmLlNjxiqBPcwwbA+gUGY8Y9dEnNSORpof2b/VV2wvZWjpW7vHCs9B6B11QPRuXBJ8 JjiZ8VA57ZuzrSlo8AGk2iayoCCCdq48JZoZWvoe3dWvNmXB95Fksdy2PbxqWPpk4Y3K f01XjgpVyoIYVoAuFxyKlskyxjCRillRpeQLiE7EaFP3CVpLeqMMfVQUFlTNusAT8wFW wSwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=PChmFsn3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 20/21] RISC-V: Enable ACPI in defconfig Date: Mon, 8 May 2023 17:22:36 +0530 Message-Id: <20230508115237.216337-21-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765330291842379397?= X-GMAIL-MSGID: =?utf-8?q?1765330291842379397?= Add support to build ACPI subsystem in defconfig. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..d3d1fbf2dd5f 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -37,6 +37,7 @@ CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=m +CONFIG_ACPI=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y From patchwork Mon May 8 11:52:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 91100 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2115460vqo; Mon, 8 May 2023 05:27:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4mV9THKlv3Ud9diiBXcDFXehpxkZDbYeBiPntXPsS0yi2E2Fa9T2CHhMP8NfC+EC38V4Py X-Received: by 2002:a05:6a00:a14:b0:639:a518:3842 with SMTP id p20-20020a056a000a1400b00639a5183842mr14029314pfh.7.1683548861753; Mon, 08 May 2023 05:27:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683548861; cv=none; d=google.com; s=arc-20160816; b=ltB0mi4MdTnrdzhUlmPswWZ1nnYGyb19BH3PDYVLJN35AFEErdw5nJVL6Mvl4F5m5+ W7fs7XDuuE1aS8oNL8huaDHR1PmWn3lyQ/NX6t24BWikGhI6Rx4S2pjUnK3MSCsbIxme sMw0T2lShcguYZMnfO591Q0sPLwUN5EEXvrXv8IXEgTBNg4th3YZH6DRNUOtoTtJOeuH iIfrYr2LUpEDyHn1Z43R0zirY8aaSaa/4sLPScbWKMzhWUMvHTyNT0tq2vCNFSGrYBwq GpZTDS9EXRnn2WucfwZbRLyn2ap8MQbIqkRbodv84kCXyVKwJs0QX9Ld4/ppv7OhSzOx iPvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OXbI3HNo2LwXyvQs8qly8d1W6GTwS2nLVT7+MHc+VBo=; b=X9Q1NWf3akdQxuNUEMHQ4SEZQAdXdjIfGHCU+tRJoRZTiPPyjmt/Qp8QvI43BMBwjL ucZb+TIf1L3UO+kvXdKzJL2Js9GFPKaed29XFkbF/Tjzyly1Pgc8RJIHqneCx348tuOO 37Kb1bWMQNDN4f9dJ9jTL/sm9I3M0aWn1X4RedvLbLnW907Hl6X1eV1dc23pXF/dU2mo glWLgsxp2Uxi5baQs/7D5FRqVdorNReiv8lYJAj474uFUISdNT7fHO4N9nl0wIB/XCPZ cO7mZydAwCvCOo2wXU/YAJp7QsrSyVea07y5aEkA7yF4iTUxMGoj/0/wanh7sEY0zrY6 Fqag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=VJ05ByxA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:48 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V5 21/21] MAINTAINERS: Add entry for drivers/acpi/riscv Date: Mon, 8 May 2023 17:22:37 +0530 Message-Id: <20230508115237.216337-22-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765328931045812655?= X-GMAIL-MSGID: =?utf-8?q?1765328931045812655?= ACPI defines few RISC-V specific tables which need parsing code added in drivers/acpi/riscv. Add maintainer entries for this newly created folder. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..083ba321fc7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -406,6 +406,14 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/acpi/arm64 +ACPI FOR RISC-V (ACPI/riscv) +M: Sunil V L +L: linux-acpi@vger.kernel.org +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/kernel/acpi.c +F: drivers/acpi/riscv + ACPI SERIAL MULTI INSTANTIATE DRIVER M: Hans de Goede L: platform-driver-x86@vger.kernel.org