From patchwork Sun May 7 18:23:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 90871 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1706180vqo; Sun, 7 May 2023 11:35:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4D09UTcKFI9st0342oFq1rQCKjHx5LRIgSRBSaguF3hA4ZmUTn+FS7mEMJCsQ7W6fbd4tk X-Received: by 2002:a17:902:ce8b:b0:1ab:d2c:a1a6 with SMTP id f11-20020a170902ce8b00b001ab0d2ca1a6mr9645329plg.69.1683484514592; Sun, 07 May 2023 11:35:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683484514; cv=none; d=google.com; s=arc-20160816; b=SXdE7XPqBoijwka9MzgW2PBSX4NgjU1SRpr7CF5/vk9SOlrhBKTL7sEr+e6xC6RKNG powvg32K4NIbf13nD3l0FV3+OX8CzuP4Au7htqzmo2HrttkKS74G2tIaK79eC4xRD0aA jIbeD66moFun7xnM5CmyQ6Wjj/mvH6P9WJbqJdR2FqbRxTrJjhVxTcv4t6E0oobYcOsh oNB9uVHlMfIl41nx8+QlotYxvyXYRFx1stP8Xt3x4jAJKYvtcgg8N0nygrgISNA8wNTw ir/SQthC1sBfF8bLCoJcXZPZnCXqiRXEVqLlA9dIXmxr1X7YSCZsLY/LddgYcy8A4MaP o7bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Nb1uOsqnQ16MTm53sM9SirAo8jpFwmDW6buaTOpfTOQ=; b=Z60f8+FpQzlAySwsAnitoFQoGNaKb/EFGFyFkRbcrhr1IeJN1BlxoFs9eCZ2iotuvS 6GppfmTdpfCJ17DtrtaOId11uxNbfmit8/CfXa5+nRhlWdx5j6u0azucVde+Zv3nJfLs 5L+60C8pos5vUTXnX//2ogPDcJrp4zeyMIkUqUzuRWzHtNqpAFfHbj1lIJpijGIyeelv jKzOCqq5HPBUT0nl95dbHU8c0ReCsu0tn0NUxAtHDzgc3bw5Rn3zyNc8cS09bzdU8Eze q0n0guKQCFc0Bg6ZBMHoqCsj7jqjA9jlAMO1dF+/JDFDmrhSizY+yJQJ97KqqSO1HPUL 31RA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=iI2gauWX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id jj3-20020a170903048300b001a66c437b2esi6210682plb.20.2023.05.07.11.35.02; Sun, 07 May 2023 11:35:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=iI2gauWX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231415AbjEGSeU (ORCPT + 99 others); Sun, 7 May 2023 14:34:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229460AbjEGSeR (ORCPT ); Sun, 7 May 2023 14:34:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 024D36E82; Sun, 7 May 2023 11:34:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8C0C460FB1; Sun, 7 May 2023 18:34:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F72FC433A1; Sun, 7 May 2023 18:34:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484456; bh=BANIf+ASt30mN5iS/NWLlkQ2ov0wGoxCBBMNfEgEvLk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iI2gauWXX+FpvZGeuZivJ5XIu/c/TN8lfj5WAK9mc72mvIoGhJH2S9uYQDOJymWlE LulXx6JEDOKWhOmWkm7ja3YdWQHbNavQi1lD0RN7dvxG8QSXcuyUX0ecMFHWUJ8HTO OoN3SPK/P+sGNQHeOzRFx4kXJmF/y3Gr2muWMdu2FKCJWiJSK0jsnib5zH5siuLnOO 7HITT5jeGH4riYtTIBC35hmL1GsO0GU0ZlnKYhCbOJcrp/xXMa7bgArhNC9LnfHqXh tNUJe8EbpWaj8kXhIthunrRBkly54fbXcirV3z//8Z9Ol1HTI4LTT7FyVxoiJxahnq iw3IQNL5k9ZwA== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Date: Mon, 8 May 2023 02:23:00 +0800 Message-Id: <20230507182304.2934-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765261458228691173?= X-GMAIL-MSGID: =?utf-8?q?1765261458228691173?= The T-HEAD's C910 PLIC still needs the delegation bit settingto allow access from S-mode, but it doesn't need the edge quirk. Signed-off-by: Jisheng Zhang --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ drivers/irqchip/irq-sifive-plic.c | 1 + 2 files changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index f75736a061af..64b43a3c3748 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -62,6 +62,10 @@ properties: - starfive,jh7110-plic - canaan,k210-plic - const: sifive,plic-1.0.0 + - items: + - enum: + - thead,light-plic + - const: thead,c910-plic - items: - enum: - allwinner,sun20i-d1-plic diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index e1484905b7bd..71afa2a584d9 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node, } IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ static int __init plic_edge_init(struct device_node *node, From patchwork Sun May 7 18:23:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 90872 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1706254vqo; Sun, 7 May 2023 11:35:27 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4BNqJ+7gpUMzgAAJc1Fz8B9oWpO0MOCdsi6Y7dNm01hGUKdK6FnwN4w1iZOGviC6dPjkqG X-Received: by 2002:a17:902:ba86:b0:1aa:86a4:37ed with SMTP id k6-20020a170902ba8600b001aa86a437edmr7062137pls.55.1683484526914; Sun, 07 May 2023 11:35:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683484526; cv=none; d=google.com; s=arc-20160816; b=pRdWc3EmTW5qgTRd8jJGmHcYMhZD5xaO8w38niPg43PrhkXxU00RSio9wEB28JwC3r MCzp9lnt/Ecg1tCm8IOH2k2WAocFxyLN6916mJSFZ4/J/N8IgCvYuqWB3Rwc9GBkC/76 wlPCKccZju9SRf6pbOYJXIjdQVYqYwB+Gdm6VJojZzO6asVBc3IsN43Pg1UDYGZwNjLt DibuoEXmpIAu6H6mCN+D6UWQGestesFqckclEGSZWvn93Zd6+1fshiK72FKz3UFY1meK Eslor01wBMbl6AvmbdwrS1+GbG95CpbOmQaLbaQ73oIRRCinmNYWioOwnn/nWx1Vse5f rMAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=h46a+QpLj5LYU5bOmoNmV5X6h4gVOo8EJ5U67Pyvwx8=; b=je6EhOcHH7QqzUW/uwQE3qqRqUSt57E2W89FyuokOSw2zNjsTK7ZLdlDEMSlM9QENY fTc1nez+bEEItbSJjC1YGDtdHodJQHCSpVwebTpPIUXgSwyTi+KKqqrnPVXiQGlrFxWo RWUKhzu2UWnoTkGh3gVBucDuwnrMnO8ekzipjH0Wi2jpYmkELGvEotBAWUpC2Fy6d5cL j+9YlVzq52gIvfX4Bfc1ChAmxwfcx+ZMd8AT7HMNocrVNmeA+Db7KnyE2J+iT+H+k6zJ FTDtTP1JHlnlKXN6B9bldAj9t/USngZ90pNj1wL8R3cs0MwP7/Y7qCziT/9YASyHP1cB J53w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=uNMPk3nt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT From patchwork Sun May 7 18:23:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 90874 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1708242vqo; Sun, 7 May 2023 11:41:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5lnv6olYji+9vMebXKhb/3enElNFhzH8Q2PpO/loWePOVIO3i9Y4HPosCrY+4pVQR9aVsp X-Received: by 2002:a17:903:483:b0:1aa:dba2:d155 with SMTP id jj3-20020a170903048300b001aadba2d155mr7644100plb.48.1683484899041; Sun, 07 May 2023 11:41:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683484899; cv=none; d=google.com; s=arc-20160816; b=YINYGjD7vgyim5cYWA/G1LSU/MtSZ0tHlg+JQCkpHj62FHd+gd0UQ6G9pexKTRn2DT 49Gfy5TRaNvT543p41R7erlP3JzdB5lFHye301cVnkyTaOR9qCJFk5QtC3ibAagvw2mu QNv2BcgW5GMfnd/FUNomwgb7XJQbSqJ7+xy2LulytAERBBrdF7g72USJKL78H+qfobYK R9+mpDrKt8FxrqmbTVxaA10yqnyJqqi9pHUXBBLyhcRxLJuApZP6U9W1aKoMLtNzNhTw CRcsSlcAFCvM+eTFKDhUO5WpK/it9mj0EPwA6AfB1yXPqWE/uk8irMsbObtn2CVym+Pu GKoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Nx8NqohhCMa0crgQ8s1AwCQJvvQMiulQLngIbGc8VZk=; b=FwP1DwlKYLKddN3nhcf9T47Bq0goBpgDMflO3gscmo1djWzBNYfRBORWt/S/H8zUNv syxmy4DQhApcbz2utTUTvCmrrnIfQVwH3Kld+3V+e30MOZBmxydweUIsvxxq35qNgKM9 7XVWolEnmAi2o+OT7dQ2XZCTErgwqzz53xy950tDrsr9JC096ZIr8KFQ8le/mUoK0VL3 r4OgAj0uOJ+qX2GPIb0MIaK0EB1In6dP7E+k0lHHKiVApV0ncLx967UXZNGVDYmU3Nrk OvN5HsdSwQyTSHtvNdTuHGOLTFNNn+rwL3myhaGG4yTExYYlB95EeYdmqEFioKbyxD3/ KHRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ovLIV0PT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i6-20020a170902c94600b001a6db2bef14si6685189pla.157.2023.05.07.11.41.25; Sun, 07 May 2023 11:41:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ovLIV0PT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231543AbjEGSee (ORCPT + 99 others); Sun, 7 May 2023 14:34:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231589AbjEGSe2 (ORCPT ); Sun, 7 May 2023 14:34:28 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 104D912EAC; Sun, 7 May 2023 11:34:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 96DF261C83; Sun, 7 May 2023 18:34:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71598C433A4; Sun, 7 May 2023 18:34:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484462; bh=hMtC0Fu67Ii4QODNt4TY01t+H41Ind3v5j5PxzFdpSo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ovLIV0PTmRvfxI7HsIK6QLdI/x4ljE/SK0Jg2V0ARdAGfrlS3CZilmQM/32IFMq+A WlVlZuEoJVqZXmqU32H/VXoJ7IgSCGhYaSPmBQ4G6to7lu1jUbM48S5Jq94ZUnHdYN Aom5m73N8SoJsLXA/Oacb9/iFWLLbrk1xoraF54lwTpU1Slo4FzdZF26p/Uc5TciBW YTVil1CUM66u7JlO854mFzcvOPMr7hJ63kK50wdlaP4HsDu0zXZeBFp8YV/CPaWAeB afmtA297pcCMApjOu2XVYeuJ9e0ILPeS8I+kpIM2V2DKlaTjJb3uFBHawQEdHztZ+O X2txNSRdBNT7A== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree Date: Mon, 8 May 2023 02:23:02 +0800 Message-Id: <20230507182304.2934-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765261861454390104?= X-GMAIL-MSGID: =?utf-8?q?1765261861454390104?= Add initial device tree for the light(a.k.a TH1520) RISC-V SoC by T-HEAD. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/thead/light.dtsi | 454 +++++++++++++++++++++++++++ 1 file changed, 454 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/light.dtsi diff --git a/arch/riscv/boot/dts/thead/light.dtsi b/arch/riscv/boot/dts/thead/light.dtsi new file mode 100644 index 000000000000..cdf6d8b04d22 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light.dtsi @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + */ + +/ { + compatible = "thead,light"; + #address-cells = <2>; + #size-cells = <2>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <3000000>; + + c910_0: cpu@0 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_1: cpu@1 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_2: cpu@2 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_3: cpu@3 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&c910_0>; + }; + + core1 { + cpu = <&c910_1>; + }; + + core2 { + cpu = <&c910_2>; + }; + + core3 { + cpu = <&c910_3>; + }; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_24m"; + #clock-cells = <0>; + }; + + osc_32k: 32k-oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; + + apb_clk: apb-clk-clock { + compatible = "fixed-clock"; + clock-output-names = "apb_clk"; + #clock-cells = <0>; + }; + + uart_sclk: uart-sclk-clock { + compatible = "fixed-clock"; + clock-output-names = "uart_sclk"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reset: reset-sample { + compatible = "thead,reset-sample"; + entry-reg = <0xff 0xff019050>; + entry-cnt = <4>; + control-reg = <0xff 0xff015004>; + control-val = <0x1c>; + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; + }; + + plic: interrupt-controller@ffd8000000 { + compatible = "thead,c910-plic"; + reg = <0xff 0xd8000000 0x0 0x01000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + riscv,ndev = <240>; + }; + + clint: timer@ffdc000000 { + compatible = "thead,c900-clint"; + reg = <0xff 0xdc000000 0x0 0x00010000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + uart0: serial@ffe7014000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7014000 0x0 0x4000>; + interrupts = <36>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@ffe7f00000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f00000 0x0 0x4000>; + interrupts = <37>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ffe7f04000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f04000 0x0 0x4000>; + interrupts = <39>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + gpio2: gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <58>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f38000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <59>; + }; + }; + + gpio0: gpio@ffec005000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec005000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <56>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec006000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <57>; + }; + }; + + uart2: serial@ffec010000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; + interrupts = <38>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + dmac0: dmac@ffefc00000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xefc00000 0x0 0x1000>; + interrupts = <27>; + clocks = <&apb_clk>, <&apb_clk>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <4>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <16>; + status = "disabled"; + }; + + timer0: timer@ffefc32000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <16>; + status = "disabled"; + }; + + timer1: timer@ffefc32014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <17>; + status = "disabled"; + }; + + timer2: timer@ffefc32028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <18>; + status = "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc3203c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <19>; + status = "disabled"; + }; + + uart4: serial@fff7f08000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f08000 0x0 0x4000>; + interrupts = <40>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@fff7f0c000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f0c000 0x0 0x4000>; + interrupts = <41>; + clocks = <&uart_sclk>; + clock-names = "baudclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <20>; + status = "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <21>; + status = "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <22>; + status = "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc3303c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <23>; + status = "disabled"; + }; + + ao_gpio0: gpio@fffff41000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff41000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <76>; + }; + }; + + ao_gpio1: gpio@fffff52000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff52000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <55>; + }; + }; + }; +}; From patchwork Sun May 7 18:23:03 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m25-20020a637d59000000b005217446e9e9si6810673pgn.294.2023.05.07.11.35.40; Sun, 07 May 2023 11:35:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=EaLyerAZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231814AbjEGSeh (ORCPT + 99 others); Sun, 7 May 2023 14:34:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231686AbjEGSed (ORCPT ); Sun, 7 May 2023 14:34:33 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 326527A82; Sun, 7 May 2023 11:34:26 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8FBD460FB1; Sun, 7 May 2023 18:34:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 763F4C4339C; Sun, 7 May 2023 18:34:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484465; bh=2RFGJcRC8JFrMMqTRjHn7GAHKS+k26LwNQvh7lnf8Oo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EaLyerAZnN7eLruXlnT2hQfLIKGVwmdNkkKVAuDGkjPSWrzxycJZVouATTBG8A06h IXzKSkNlQaualCy4W0yX1WkhhPH7BJ0nejUz+wkKrSv89OLb4AxcuJ7l/mUeiP/sBQ De1b18YxQMbnoLvBjJuq5GbjH8Whca2XNuA3XRk57I4ZmWGEseVkt1AmmQ0yYERPM2 1yqt/moQtM8VkLFpvAt1MABtkqACsxpNvAnOAYp14l7VqbjIzNZW8bacdY8G42tLsb lIw9CtZdfdJwwskl7BHrFHHHlXgLNklDiX1BaWB3yJFfHy27LdXf3YuVVNjBrTdOPU V8YkFhtw+7WUg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 4/5] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Date: Mon, 8 May 2023 02:23:03 +0800 Message-Id: <20230507182304.2934-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765261498676042933?= X-GMAIL-MSGID: =?utf-8?q?1765261498676042933?= Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's light(a.k.a TH1520) SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/light-lichee-module-4a.dtsi | 38 +++++++++++++++++++ .../boot/dts/thead/light-lichee-pi-4a.dts | 32 ++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f8..1e884868ccba 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -2,6 +2,7 @@ subdir-y += allwinner subdir-y += sifive subdir-y += starfive +subdir-y += thead subdir-y += canaan subdir-y += microchip subdir-y += renesas diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile new file mode 100644 index 000000000000..9e00acc714cc --- /dev/null +++ b/arch/riscv/boot/dts/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_THEAD) += light-lichee-pi-4a.dtb diff --git a/arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi new file mode 100644 index 000000000000..24c9971e0fb5 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +/dts-v1/; + +#include "light.dtsi" + +/ { + model = "Sipeed Lichee Module 4A"; + compatible = "sipeed,lichee-module-4a", "thead,light"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&osc_32k { + clock-frequency = <32768>; +}; + +&apb_clk { + clock-frequency = <62500000>; +}; + +&uart_sclk { + clock-frequency = <100000000>; +}; + +&dmac0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts new file mode 100644 index 000000000000..4f0ba2149d2d --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include "light-lichee-module-4a.dtsi" + +/ { + model = "Sipeed Lichee Pi 4A"; + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,light"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; From patchwork Sun May 7 18:23:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 90875 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1710045vqo; Sun, 7 May 2023 11:47:31 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5lkIlM1Pw09pwNOx+JHGr60EzmwzLpPnU+4TLNDITn8i6fBj3+gS9WfFJ2bKq3jY5HRVdJ X-Received: by 2002:a17:90b:3910:b0:250:2ad4:b459 with SMTP id ob16-20020a17090b391000b002502ad4b459mr7875158pjb.39.1683485251272; Sun, 07 May 2023 11:47:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683485251; cv=none; d=google.com; s=arc-20160816; b=S3q1UW7MjbCqDSW97ET7Wufcsl/IFlvhEtscPnnhkA5BiqKCXYu3eMHqZr7FBPNP2O ExkIW3l1xtgJWDimm0YwXsmVhySiFoEykXG3tAmqVqRTHHGVOQ1aHbyKrlvoI/4T+2Th sy+/Dvit7NfYarGtw7iXhnID4y9axyCjoZfbtsycwu3zIqT6ix3hVRV6oU2QFny97rRd Hfl9tiNOh953F9iFNBAHREZkekypzRKdNFWrIyJ/2jrFCXbNlnKFeyOIjLOOgD4yqCwR 8SMxLQKftcw7zGmhqy51oGjjqNYqFnyffIAk7fhM5XYp/Ch4mZvpyo1FkSx8+MD+gEMH bM8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wFqp1Oa2uEnPAOc7kjw/iUoAlNTCC/UamFCUGIM1CtI=; b=aFE7ucnJmaa7SRn5E/Fo38/MQCWYWvXi8WVf2F/iIu4aVNZkKvRlvTqEexk5XWpVpZ Phv/h4ln0wQZZJXRVFpW1S83R9H7oS2FKmmtjYjd9JjyQovHaRlMD+aDMViEA2mrvcDV iOFp4+pdgwePQGsDZfEfRrLvwsC6rNNHYVzHRVl2MOEoD0Z7vwsFXVv5Hl0piz05sPvB DDjO34P5U/K7iKcEHiQrl6AOxcFPjmem+J/g3zoQVbgJi3zTxhstDOhv3A2ed/K1bCEc go7a6jtQE75PSpQjmoNGLGMqfWfvIIwujR1OV7uKUee4y0vtbnaXoeCOOeryb2Vm6e3l NoXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=GehbaZei; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k5-20020a17090a3cc500b00247425ceb4csi10742670pjd.165.2023.05.07.11.47.13; Sun, 07 May 2023 11:47:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=GehbaZei; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231754AbjEGSes (ORCPT + 99 others); Sun, 7 May 2023 14:34:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231738AbjEGSel (ORCPT ); Sun, 7 May 2023 14:34:41 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F2216E93; Sun, 7 May 2023 11:34:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9497B61C67; Sun, 7 May 2023 18:34:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 752CDC433EF; Sun, 7 May 2023 18:34:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484468; bh=5Ctl8xQn5Up2BfcQEPensi3ZFyebX1h9yHH8JgAlfCU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GehbaZeik0nSLoZNom/ZTCM0VHsqmpTwh5xbhVcQl8OSoZhhfGUog1cH08s3zpl9V AYYIaMPmJcU0f9YlzCeDy43U1obqTFYZuMNO6BLy7OLdemKuctVdAhuXzNl91nIk62 f0/LCnyxwniZuHwxfdasaHd1uO8ajjSp7ZlqAocn/0g8dYAIOj/KdknmHwjXJv4cMe mGhaaMYZZRYLfOLwvXe8Yq7Bb8pbFmVo0SKNXgUgYcKoTVshRXYHWsumOOXy2437oz NrBtzurbpkuyUC1FAY2ko5fqepWgZO7UtRtMfNu4/bLTB3EVX5zoMdIDZlWHBHyPth Hp7vTxangetyg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Date: Mon, 8 May 2023 02:23:04 +0800 Message-Id: <20230507182304.2934-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765262230765053336?= X-GMAIL-MSGID: =?utf-8?q?1765262230765053336?= I would like to temporarily maintain the T-HEAD RISC-V SoC support. Signed-off-by: Jisheng Zhang --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..e1e51accec4f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18155,6 +18155,12 @@ T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: Documentation/devicetree/bindings/riscv/ F: arch/riscv/boot/dts/ +RISC-V THEAD SoC SUPPORT +M: Jisheng Zhang +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/thead/ + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang