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Add both the ISI and CSI nodes, and pointing them to each other. Since the CSI capture is dependent on an attached camera, mark both ISI and CSI as disabled by default. Signed-off-by: Adam Ford --- V2: Change from a singular 'port' to 'ports' per feedback from Laurent Pinchart "When a single port is present using a "port" node directly is fine from an OF graph point of view, but to avoid too much complexity in the ISI binding the consensus was to always require a "ports" node for the ISI." This is also consistent with the binding YAML file. Change the size allocated to the ISI to 32k. The datasheet indicates it should be 64K, but the disp_blk_ctrl sits at 32e28000. Change the subject from 'Enable' to 'Add' since the ISI and CSI nodes are both technically disabled. diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 8be8f090e8b8..9869fe7652fc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1104,6 +1104,30 @@ dsim_from_lcdif: endpoint { }; }; + isi: isi@32e20000 { + compatible = "fsl,imx8mn-isi"; + reg = <0x32e20000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&disp_blk_ctrl>; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + isi_in: endpoint { + remote-endpoint = <&mipi_csi_out>; + }; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1147,6 +1171,42 @@ disp_blk_ctrl: blk-ctrl@32e28000 { #power-domain-cells = <1>; }; + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = ; + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL2_1000M>; + assigned-clock-rates = <333000000>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_CAMERA_PIXEL>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_out: endpoint { + remote-endpoint = <&isi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; From patchwork Sun May 7 15:15:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 90855 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1637529vqo; Sun, 7 May 2023 08:46:50 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5GTJ0l5LsfQ0LaEk3RJYjxb0CZ6/VbFz8qba7/bYWHMal1uma93jwYM7193HVp3l2hMBoP X-Received: by 2002:a17:902:d50c:b0:1ab:f74:a118 with SMTP id b12-20020a170902d50c00b001ab0f74a118mr9545844plg.19.1683474409876; Sun, 07 May 2023 08:46:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683474409; cv=none; d=google.com; s=arc-20160816; b=YO2Ruubr5KUwrLPaiGG5viwAD8SGqzcGeJ3lfXzdUBeJzYj9tU2iQ/0hwqEnlV19/V PBsNgbY0O2EF2dkBT4kzySPI6hLfc0b1enaCBABOHwaaRRPgV6hoLFDtM5dWckvZ7vgc ygzwRglWDSWkvlmkVksEi/+YDIQ+HSCAdV3xK8Li95/qbNy5Iq0kTIlLyHD1vre5aPt0 7kEMaBUISjfCfUt2M63haFGo0CH3Vmgiq7PEEGJAdnpjQ4aLCszQ4S80E9KIjLDdjSpC i99ewuGjJS/2/+rxdS/mnaTWggXCU+WsP7Xa+XlRCAvPR6bnHoJiaUPO+CqPBIeHgpPD rnGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=u0FAgyG30bpRJlMKwIJbN0GIC3aFiZtnxD9A8v5yUOA=; b=j4ZYqcZpEamMxfwJMJYo9NsSgoL/rcj134xR1Zjs6hqx9cy98/u7zXFU5lBJx4OU6j WyVQHXZFI/W+mZ0O4cMepxzCNISTvEQqUJM6if9HlRcrwDWk85YVVwk6+lSuyUKrysLO h+gEgzRANBmoYHjrcvwHYDpYmVp4iF70C215Naf1MV42LMieEB8I+k2qEnrs6/gfSo1M xZeGKS7K0gzCJnn1m9ulL9/xO3CrCHPrQLs0uyhbXCqncH58XbupFq2C16rhuMYFVwhe Bgwzaw4IHC+375cJGXGHj2hUKDJcOaNgjXNUaJOx29vjeR5myLTLvdfDC5cM4Wf0MZSZ luNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=NzbuuiAD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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The Mini routes the CSIS output to the imx7-CSI driver, and the Nano routes the CSIS through the imx8-isi driver like the one used on the imx8mp. Enable the drivers necessary to facilitate capture on both of these two platforms. Signed-off-by: Adam Ford Reviewed-by: Laurent Pinchart --- V2: No Change diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a24609e14d50..7005640fbb8e 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -743,6 +743,10 @@ CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_MEDIATEK_JPEG=m CONFIG_VIDEO_MEDIATEK_VCODEC=m +CONFIG_VIDEO_IMX7_CSI=m +CONFIG_VIDEO_IMX_MIPI_CSIS=m +CONFIG_VIDEO_IMX8_ISI=m +CONFIG_VIDEO_IMX8_ISI_M2M=y CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m CONFIG_VIDEO_RCAR_ISP=m From patchwork Sun May 7 15:15:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 90853 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1629771vqo; Sun, 7 May 2023 08:28:59 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5VXF2VKtH2YEFcQ+mxkuCmsjJomyeWr8BjaMZ2dWc60E8EFxg8+YQGRl+flHKyn60BKO1k X-Received: by 2002:a05:6a00:1742:b0:637:c959:8ea1 with SMTP id j2-20020a056a00174200b00637c9598ea1mr9926446pfc.22.1683473339178; Sun, 07 May 2023 08:28:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683473339; cv=none; d=google.com; s=arc-20160816; b=Pq8jWZyAiF0ZFXwQ46xnCNTUg6dWbjBahbullPfqLzSyYMf11VMeQ2Lg9CZ/aChfg9 peUVb28a2NVIZ6Cxj4drXoY3OgS8uU8Npy62HkMiBGMG1UjwIlhGAcGtrKPqWavhz5xS aJLo6tNKoSkIrXvCECYvP42xDbRkn9xsX7RBfquoVquTa/UxEBTiksgA+weV/6eL5B4y ct87HprgWIvg6OwvNredt89UPKaKCN1NpjE3gQUxPOtacCHULfocAO2DN5fsVaf7Sv1w KsffiOVVwi1b+Irzx22wZc2PMqt+iU1BBZ2rkwsfhj0JH6bmk80wrTUToH5j8SnZdPA6 6Prw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Myks9ibscFfLfkvDsV+jBK2okCgS5xjyuH4qT5dxmZ0=; b=Tdym01j7DBoqeHNDnTBSqXmZeRr0O5zUwXvXKiSrrefxsBRfeme0ghgzl/cYfN9x54 sfO/gOWoV6BuWiKj65iUgME0eJ0mWRevVbkLAcv5VcXHlkV2fXVqWp6bZMyEXs2iFkL5 B9MD5Ux+Bk/w5PppUZNSgscoagKtLbvGJrNyclhCat/VhG1DjhD50OXJf63rYPa6SKpZ i8bYT4qQnGYFPWknYQBU4UA8dj4kDaLHFLbveUlkGQniRhurVLxnbsZZ8WP9wOs4Z1O+ RAVkJHnDwjFJys9mNFhagdLJnXYH6CeJiDwQxrsrvECtF0563VqDlsOBRy0EIxgvM8x8 3mEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=onyWJMmF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Enable it as part of the deveopment kit baseboard instead of an overlay. Enable the camera with the following media-ctl -l "'ov5640 1-0010':0 -> 'csis-32e30000.mipi-csi':0 [1]" media-ctl -v -V "'ov5640 1-0010':0 [fmt:UYVY8_1X16/640x480 field:none]" media-ctl -v -V "'crossbar':0 [fmt:UYVY8_1X16/640x480 field:none]" media-ctl -v -V "'mxc_isi.0':0 [fmt:UYVY8_1X16/640x480 field:none]" Signed-off-by: Adam Ford --- V2: New to series, since Laurent asked me to add a board which supports the previous two commits. diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 9e82069c941f..6dce77a6114c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -43,6 +43,17 @@ reg_audio: regulator-audio { enable-active-high; }; + reg_camera: regulator-camera { + compatible = "regulator-fixed"; + regulator-name = "mipi_pwr"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "vsd_3v3"; @@ -96,6 +107,36 @@ eeprom@0 { }; }; +&i2c2 { + clock-frequency = <384000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + camera@10 { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x10>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + AVDD-supply = <®_camera>; /* 2.8v */ + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + + port { + /* MIPI CSI-2 bus endpoint */ + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; &i2c4 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -145,11 +186,28 @@ wm8962: audio-codec@1a { }; }; +&isi { + status = "okay"; +}; + &easrc { fsl,asrc-rate = <48000>; status = "okay"; }; +&mipi_csi { + status = "okay"; + + ports { + port@0 { + mipi_csi_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -226,6 +284,14 @@ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 >; }; + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19