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(riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (vlmul_field_enum): Ditto. * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Remove static scope. * config/riscv/riscv-opts.h (riscv_vector_lmul_enum): New enum. --- gcc/config/riscv/riscv-opts.h | 10 ++++++++++ gcc/config/riscv/riscv-protos.h | 9 +++++++++ 2 files changed, 19 insertions(+) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 4207db240ea..00c4ab222ae 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,7 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; + /* RISC-V auto-vectorization preference. */ enum riscv_autovec_preference_enum { NO_AUTOVEC, @@ -82,6 +83,15 @@ enum riscv_autovec_lmul_enum { RVV_M8 = 8 }; +/* vectorization factor. */ +enum riscv_vector_lmul_enum +{ + RVV_LMUL1 = 1, + RVV_LMUL2 = 2, + RVV_LMUL4 = 4, + RVV_LMUL8 = 8 +}; + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 33eb574aadc..fb39b856735 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -243,4 +243,13 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); #endif extern bool riscv_use_divmod_expander (void); +/* Routines implemented in riscv-v.cc. */ + +namespace riscv_vector { +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode); +extern bool riscv_vector_mask_mode_p (machine_mode); +extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode); +extern rtx get_mask_policy_no_pred (); +extern rtx get_tail_policy_no_pred (); +} #endif /* ! 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(get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred): New external declaration. (get_mask_policy_for_pred): Ditto. --- gcc/config/riscv/riscv-vector-builtins.cc | 4 ++-- gcc/config/riscv/riscv-vector-builtins.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 434bd8e157b..f0ebc095fa7 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -2496,7 +2496,7 @@ use_real_merge_p (enum predication_type_index pred) /* Get TAIL policy for predication. If predication indicates TU, return the TU. Otherwise, return the prefer default configuration. */ -static rtx +rtx get_tail_policy_for_pred (enum predication_type_index pred) { if (pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == PRED_TYPE_tumu) @@ -2506,7 +2506,7 @@ get_tail_policy_for_pred (enum predication_type_index pred) /* Get MASK policy for predication. If predication indicates MU, return the MU. Otherwise, return the prefer default configuration. */ -static rtx +rtx get_mask_policy_for_pred (enum predication_type_index pred) { if (pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu) diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 8ffb9d33e33..de3fd6ca290 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -483,6 +483,9 @@ extern rvv_builtin_types_t builtin_types[NUM_VECTOR_TYPES + 1]; extern function_instance get_read_vl_instance (void); extern tree get_read_vl_decl (void); +extern rtx get_tail_policy_for_pred (enum predication_type_index pred); +extern rtx get_mask_policy_for_pred (enum predication_type_index pred); + inline tree rvv_arg_type_info::get_scalar_type (vector_type_index type_idx) const { From patchwork Fri May 5 15:46:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 90490 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp507183vqo; Fri, 5 May 2023 08:49:59 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7z4MAQXvb7rIM8bwXjbGdGD/9FXi8NM/V1h+zyifQ9X2Qn1UBhmMcXlN4fBpuMkTzPK3N+ X-Received: by 2002:a17:907:783:b0:862:c1d5:ea1b with SMTP id xd3-20020a170907078300b00862c1d5ea1bmr1792098ejb.8.1683301799068; Fri, 05 May 2023 08:49:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683301799; cv=none; d=google.com; s=arc-20160816; b=0ZUPJhXM5XgRYNjpGUeBmXk1eLfpeM/BRdjag5VOjt5NNl0ScqqlHgJYLAD1PVSjS2 d06oXJH5rQcY3Hk9QxrXgCdsZdBhhveohaxu4VBv4EIFxSZ4Myz/+af3kTCu9IPkGdAn qJtC9KP8MiY7Rl+tR2aZI4VXAOZccmy8oxL1pk50cwhiYIEJCLK9c1xHVosM2KF0gxfa moNc73neYetwQOtIZnUccYLwgmOnedULpE5WMcVqAdnbEtjR8Egw0XxF/v2cw411Wv5E 7TWYmASLLqiaF7rf6ht8kCAnsbQPN5F7CnZf4r2pU/8bdC4RKY6b4W3jAzCfOg3M2BUQ AYkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=B/QZa46aLJ+xJ4j67Wj6BwpRIqfZUegdMXm/cGlvQW0=; b=XjFyxSZ0AhP4/rSt1S9XAlMowd+n+rWTj0pjhr9iAbcm8It+z5JEFRHEtu8/TfCjBM 90WGR9XS9puqLAxirbfru34f5zaRFOqj/08B+Lln5NCjlbiJMyDQX2GNP5CZyjHtvs3F 6JJ/JY1BXYcQGubUX7a6FSrB2BM3uURaDxmgajjilRm3nGwGogoLdC+w2z51V9O6datg Jh0L9GnjDE7r9sBKgHTfnSGtBpClx40hmc4oLvszX4xicOxkBtreWVBuVD9zRvTwQYKR mupSD1gdHaflkaKBnmnvyLUqEiEMpszks+cZDLhfFgD8/y4GSNGdEfojnbJAXJZHyNw5 lr6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=gHqtNgSM; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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(get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. --- gcc/config/riscv/riscv-v.cc | 91 +++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 99c414cc910..7faffb55046 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -39,9 +39,11 @@ #include "emit-rtl.h" #include "tm_p.h" #include "target.h" +#include "targhooks.h" #include "expr.h" #include "optabs.h" #include "tm-constrs.h" +#include "riscv-vector-builtins.h" #include "rtx-vector-builder.h" using namespace riscv_vector; @@ -176,6 +178,56 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) return ratio; } +/* SCALABLE means that the vector-length is agnostic (run-time invariant and + compile-time unknown). FIXED meands that the vector-length is specific + (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing + auto-vectorization using VLMAX vsetvl configuration. */ +static bool +autovec_use_vlmax_p (void) +{ + return riscv_autovec_preference == RVV_SCALABLE + || riscv_autovec_preference == RVV_FIXED_VLMAX; +} + +/* Return the vectorization machine mode for RVV according to LMUL. */ +machine_mode +riscv_vector_preferred_simd_mode (scalar_mode mode) +{ + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 && + riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE + when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. + in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have + VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are + enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to + use them. Currently, we can support auto-vectorization in + -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or + -march=rv32_zve32x_zvl64b are disabled. + */ + if (autovec_use_vlmax_p ()) + { + /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2 + auto-vectorization since Loop Vectorizer may use VNx1SImode or + VNx1DImode to vectorize which will create ICE in the + 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. */ + if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2) + return word_mode; + /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and + riscv_autovec_lmul as multiply factor to calculate the the NUNITS to + get the auto-vectorization mode. */ + poly_uint64 nunits; + poly_uint64 vector_size + = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); + poly_uint64 scalar_size = GET_MODE_SIZE (mode); + gcc_assert (multiple_p (vector_size, scalar_size, &nunits)); + machine_mode rvv_mode; + if (get_vector_mode (mode, nunits).exists (&rvv_mode)) + return rvv_mode; + } + /* TODO: We will support minimum length VLS auto-vectorization in the future. + */ + return word_mode; +} + /* Emit an RVV unmask && vl mov from SRC to DEST. */ static void emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len, @@ -430,6 +482,45 @@ get_avl_type_rtx (enum avl_type type) return gen_int_mode (type, Pmode); } +/* Return the mask policy for no predication. */ +rtx +get_mask_policy_no_pred () +{ + return get_mask_policy_for_pred (PRED_TYPE_none); +} + +/* Return the tail policy for no predication. */ +rtx +get_tail_policy_no_pred () +{ + return get_tail_policy_for_pred (PRED_TYPE_none); +} + +/* Return true if it is a RVV mask mode. */ +bool +riscv_vector_mask_mode_p (machine_mode mode) +{ + return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode + || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode + || mode == VNx64BImode); +} + +/* Return the appropriate mask mode for MODE. */ + +opt_machine_mode +riscv_vector_get_mask_mode (machine_mode mode) +{ + machine_mode mask_mode; + int nf = 1; + + FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL) + if (GET_MODE_INNER (mask_mode) == BImode + && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode)) + && riscv_vector_mask_mode_p (mask_mode)) + return mask_mode; + return default_get_mask_mode (mode); +} + /* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE. This function is not only used by builtins, but also will be used by auto-vectorization in the future. */ From patchwork Fri May 5 15:46:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 90489 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp507174vqo; Fri, 5 May 2023 08:49:57 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ53vIVMcCthP7XlfuJpWuGDVSPRmJijAGl9VLxrBaxCU0KRZFi+xSihxo0sQ+dK3l6uTNaa X-Received: by 2002:aa7:d609:0:b0:50d:8894:8c11 with SMTP id c9-20020aa7d609000000b0050d88948c11mr222756edr.11.1683301797735; Fri, 05 May 2023 08:49:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683301797; cv=none; d=google.com; s=arc-20160816; b=YSezizJ1OmSBcH5ClXw8cRWzjzMIGQ/KpOl2cehz3Krbdwn0ePjx3kneZdgp/o+xnV wX6/5E+YEM2wmkm/8iiIpBb+QHO3KqvYbQjHlzvB6O6jVwLSJlXlNqBV1SglDCSCcDgS FIQM32pWnVTn/zSUEipaM0Mdjjs+A2Fc9HDEJtVNlysPDfBESwipyJYuNtgBsqi/JvtP rADBmvvTEZIJrIrCgHmZlknt05gY6HepU1glXtkHvqgApryYKfYEQE5gow7PcUxji1J6 KETQtlAfa9zsO2LUqH6PcapZmXHxLS022aCjIlI/ximUoVRl8Tt3b+v2o3xf1VUZhLtS KHQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=C0xsoxzdldoxCrktDwsghPeS6+ZN820DraYxZxc3i50=; b=XGoTp11Ih7rQmhmw8uQEvK4rEFsN5yUVW2y8kkx1T47vPYXL2sLIkeOobC94ICU3Gf Ox3931o/K4I/Ksp3dW2gz4FMBlUoVSTmid/vcOZFiGEvDai1aNzP0ecTv5CVPTryRJrp sJl5j5ADvnG/OvYzYnYEo0LfQDmOs96Sfb3+3D3knEQpwwz4Iuqx4tE4QLWh71dnAyje PH3+6FHNlbbM6tcnXP1DY1c7gMhre6e8XAhWwuOULrPZTamIADaVicRhpuxRp0sFGrJ5 iiYrcbu4ss8sF/qzvuvkk5TPMUNZIBEU4d37mN5Wd/8qcUXSBNGSyIINWYckaN7oRoJw i7oA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=3TH55hnh; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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(riscv_preferred_simd_mode): Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. (riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE. (riscv_empty_mask_is_expensive): Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. (riscv_vectorize_create_costs): Implement TARGET_VECTORIZE_CREATE_COSTS. (riscv_support_vector_misalignment): Implement TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT. (TARGET_ESTIMATED_POLY_VALUE): Register target macro. (TARGET_VECTORIZE_GET_MASK_MODE): Ditto. (TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto. (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Ditto. --- gcc/config/riscv/riscv.cc | 130 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1e328f6a801..1425f50d80a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -60,6 +60,15 @@ along with GCC; see the file COPYING3. If not see #include "opts.h" #include "tm-constrs.h" #include "rtl-iter.h" +#include "gimple.h" +#include "cfghooks.h" +#include "cfgloop.h" +#include "cfgrtl.h" +#include "sel-sched.h" +#include "fold-const.h" +#include "gimple-iterator.h" +#include "gimple-expr.h" +#include "tree-vectorizer.h" /* This file should be included last. */ #include "target-def.h" @@ -7138,6 +7147,112 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor, return RISCV_DWARF_VLENB; } +/* Implement TARGET_ESTIMATED_POLY_VALUE. + Look into the tuning structure for an estimate. + KIND specifies the type of requested estimate: min, max or likely. + For cores with a known RVV width all three estimates are the same. + For generic RVV tuning we want to distinguish the maximum estimate from + the minimum and likely ones. + The likely estimate is the same as the minimum in that case to give a + conservative behavior of auto-vectorizing with RVV when it is a win + even for 128-bit RVV. + When RVV width information is available VAL.coeffs[1] is multiplied by + the number of VQ chunks over the initial Advanced SIMD 128 bits. */ + +static HOST_WIDE_INT +riscv_estimated_poly_value (poly_int64 val, + poly_value_estimate_kind kind = POLY_VALUE_LIKELY) +{ + unsigned int width_source = BITS_PER_RISCV_VECTOR.is_constant () + ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant () + : (unsigned int) RVV_SCALABLE; + + /* If there is no core-specific information then the minimum and likely + values are based on 128-bit vectors and the maximum is based on + the architectural maximum of 65536 bits. */ + if (width_source == RVV_SCALABLE) + switch (kind) + { + case POLY_VALUE_MIN: + case POLY_VALUE_LIKELY: + return val.coeffs[0]; + + case POLY_VALUE_MAX: + return val.coeffs[0] + val.coeffs[1] * 15; + } + + /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the + lowest as likely. This could be made more general if future -mtune + options need it to be. */ + if (kind == POLY_VALUE_MAX) + width_source = 1 << floor_log2 (width_source); + else + width_source = least_bit_hwi (width_source); + + /* If the core provides width information, use that. */ + HOST_WIDE_INT over_128 = width_source - 128; + return val.coeffs[0] + val.coeffs[1] * over_128 / 128; +} + +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */ + +static machine_mode +riscv_preferred_simd_mode (scalar_mode mode) +{ + if (TARGET_VECTOR) + return riscv_vector::riscv_vector_preferred_simd_mode (mode); + + return word_mode; +} + +bool +riscv_support_vector_misalignment (machine_mode mode, + const_tree type ATTRIBUTE_UNUSED, + int misalignment, + bool is_packed ATTRIBUTE_UNUSED) +{ + if (TARGET_VECTOR) + { + if (STRICT_ALIGNMENT) + { + /* Return if movmisalign pattern is not supported for this mode. */ + if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing) + return false; + + /* Misalignment factor is unknown at compile time. */ + if (misalignment == -1) + return false; + } + return true; + } + + return default_builtin_support_vector_misalignment (mode, type, misalignment, + is_packed); +} + +/* Implement TARGET_VECTORIZE_GET_MASK_MODE. */ + +static opt_machine_mode +riscv_get_mask_mode (machine_mode mode) +{ + machine_mode mask_mode = VOIDmode; + if (TARGET_VECTOR + && riscv_vector::riscv_vector_get_mask_mode (mode).exists (&mask_mode)) + return mask_mode; + + return default_get_mask_mode (mode); +} + +/* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that + it isn't worth branching around empty masked ops (including masked + stores). */ + +static bool +riscv_empty_mask_is_expensive (unsigned) +{ + return false; +} + /* Return true if a shift-amount matches the trailing cleared bits on a bitmask. */ @@ -7522,9 +7637,24 @@ riscv_use_divmod_expander (void) #undef TARGET_VERIFY_TYPE_CONTEXT #define TARGET_VERIFY_TYPE_CONTEXT riscv_verify_type_context +#undef TARGET_ESTIMATED_POLY_VALUE +#define TARGET_ESTIMATED_POLY_VALUE riscv_estimated_poly_value + +#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE +#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode + +#undef TARGET_VECTORIZE_GET_MASK_MODE +#define TARGET_VECTORIZE_GET_MASK_MODE riscv_get_mask_mode + +#undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE +#define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE riscv_empty_mask_is_expensive + #undef TARGET_VECTOR_ALIGNMENT #define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment +#undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT +#define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT riscv_support_vector_misalignment + #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value From patchwork Fri May 5 15:46:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 90484 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp506114vqo; Fri, 5 May 2023 08:48:10 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4W7mAH0tQbqa3NLo06vd80yC1ccROhMhMD2NgHvlrZlAGIJosGvXy3hgkR8kDiGySG0XZ+ X-Received: by 2002:a17:907:720c:b0:95e:ce4b:b333 with SMTP id dr12-20020a170907720c00b0095ece4bb333mr1556119ejc.53.1683301690427; Fri, 05 May 2023 08:48:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683301690; cv=none; d=google.com; s=arc-20160816; b=g2M4nuoXC+Nph+qOCo/UMhdWN2j9+HbliTbzcRPBNukliODXwtwSiFRuXwUh/XOgU2 mLENGygUzwCLPka6tikI7lZopyIE3nhV140eyZd9vNykus3b9gvkqm1rlO6ytwUEwf6R qZBnzJ4z3742WQP5G2H2uy2u9eK1rKfMWD/4DkSH5kBzK1xB0orL76e1mGz80IWM11VB Dpg1c5YaKE3DIxbdFTGSwAm7ZnDjdW/bZ7fRaNNJTa48T3rTMxLib5rZhz4Tz1DGZ7Ag 63WS5krKu/+ClIiVfcZhbJHTCseG0PwJQmb/dJ1jRGeocyY9lFPsFg6vW2tXPR86tb9Q gjbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=xWKdAUiACWg6Q1/rWmeh3GKhsdh1Weq67zXUUokOQN4=; b=BAC0wmXP68ba+mhZArtXk/2O3vJ346H3AaJizEKG++4XGHtzNH59iWsoA8XBx+MWVL yBvnx9cqk/Z1adxYxGQcyIkKQWrCSLgsVL89IitRGOGEtY6d5k2DiiXE/K6xhDzaUwcX shSBi/LuDtQ9uOo0CW0wV+BRpf40JudtqupRBhnGsH0/wKO0F0bWECZHpJ8WjHj5E0vC Hyo+2nR+/45NhuSCcet7Caannh7jvDDVv167g2o0a69MvAVZJ3c7Q6MrdyMEZXaIWgS2 7xcDrxKp6GR4XppEomS2QGW0q/pqFdi78PRfBM/EYEBdshzJ5LLe0b8zFoIotaaG5cmI XUGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=XypmcJGf; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Fri, 05 May 2023 08:46:11 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v6 5/9] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store Date: Fri, 5 May 2023 11:46:03 -0400 Message-Id: <20230505154607.1155567-6-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505154607.1155567-1-collison@rivosinc.com> References: <20230505154607.1155567-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765069753784719232?= X-GMAIL-MSGID: =?utf-8?q?1765069753784719232?= 2023-04-25 Michael Collison Juzhe Zhong * config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include vector-iterators.md. * config/riscv/vector-auto.md: New file containing autovectorization patterns. * config/riscv/vector.md: Remove include of vector-iterators.md and include vector-auto.md. --- gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/vector-auto.md | 74 +++++++++++++++++++++++++++++++++ gcc/config/riscv/vector.md | 4 +- 3 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 gcc/config/riscv/vector-auto.md diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c508ee3ad89..e9b49eda617 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -140,6 +140,7 @@ (include "predicates.md") (include "constraints.md") (include "iterators.md") +(include "vector-iterators.md") ;; .................... ;; diff --git a/gcc/config/riscv/vector-auto.md b/gcc/config/riscv/vector-auto.md new file mode 100644 index 00000000000..83d2ab6957a --- /dev/null +++ b/gcc/config/riscv/vector-auto.md @@ -0,0 +1,74 @@ +;; Machine description for RISC-V 'V' Extension for GNU compiler. +;; Copyright (C) 2022-2023 Free Software Foundation, Inc. +;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. +;; Contributed by Michael Collison (collison@rivosinc.com, Rivos Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; len_load/len_store is a sub-optimal pattern for RVV auto-vectorization support. +;; We will replace them when len_maskload/len_maskstore is supported in loop vectorizer. +(define_expand "len_load_" + [(match_operand:V 0 "register_operand") + (match_operand:V 1 "memory_operand") + (match_operand 2 "vector_length_operand") + (match_operand 3 "const_0_operand")] + "TARGET_VECTOR" +{ + riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0], + operands[1], operands[2], mode); + DONE; +}) + +(define_expand "len_store_" + [(match_operand:V 0 "memory_operand") + (match_operand:V 1 "register_operand") + (match_operand 2 "vector_length_operand") + (match_operand 3 "const_0_operand")] + "TARGET_VECTOR" +{ + riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0], + operands[1], operands[2], mode); + DONE; +}) + +;; ------------------------------------------------------------------------- +;; ---- [INT] Vector binary patterns +;; ------------------------------------------------------------------------- + +(define_expand "3" + [(set (match_operand:VI 0 "register_operand") + (any_int_binop:VI (match_operand:VI 1 "") + (match_operand:VI 2 "")))] + "TARGET_VECTOR" +{ + using namespace riscv_vector; + + rtx merge = RVV_VUNDEF (mode); + rtx vl = gen_reg_rtx (Pmode); + emit_vlmax_vsetvl (mode, vl); + rtx mask_policy = get_mask_policy_no_pred (); + rtx tail_policy = get_tail_policy_no_pred (); + rtx mask = CONSTM1_RTX(mode); + rtx vlmax_avl_p = get_avl_type_rtx (NONVLMAX); + + emit_insn (gen_pred_ (operands[0], mask, merge, operands[1], operands[2], + vl, tail_policy, mask_policy, vlmax_avl_p)); + + DONE; +}) + + diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1642822d098..5c9252c281b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -26,8 +26,6 @@ ;; - Auto-vectorization (TBD) ;; - Combine optimization (TBD) -(include "vector-iterators.md") - (define_constants [ (INVALID_ATTRIBUTE 255) (X0_REGNUM 0) @@ -368,6 +366,8 @@ (symbol_ref "INTVAL (operands[4])")] (const_int INVALID_ATTRIBUTE))) +(include "vector-auto.md") + ;; ----------------------------------------------------------------- ;; ---- Miscellaneous Operations ;; ----------------------------------------------------------------- From patchwork Fri May 5 15:46:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 90495 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp508567vqo; Fri, 5 May 2023 08:52:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6wM2wLh7Br6DB6jN4SeS5eTL5OXpod1CGd+lXzPt7s16gJfhPofLrG93+ojJU3QKyPdLEq X-Received: by 2002:aa7:cb11:0:b0:504:a3ec:eacc with SMTP id s17-20020aa7cb11000000b00504a3eceaccmr1925377edt.4.1683301943658; Fri, 05 May 2023 08:52:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683301943; cv=none; d=google.com; s=arc-20160816; b=boTh3ZWCT+8SwYdTP6bFOPaZgw0mnG37y/CP4QB6tvOZwC1Ye+W+hBbaFXIEnWl8wp 7Mxva2SwyykzfNRhIR6bHCUnENycv6Zs0k7LFvl2MwzC64I9IX3WkKzd8wkMzCeZk1iU jSaSLfBpbOhaoO/aORiVz+IWaFcmp8BEeEemlI76aqw6i2enF41wOokhTlXOw4VUjyRJ XvsX9faWOlWdimCTT5XNOgUO6ldNeSkU/3Odh2CED0OdMYz1beKzCmN+vEFgvlOoX3C4 ob/SHnoq7AFkXc/d69t/L/WEfHSeDlRDLi6OXWhhBv0y8fSqEarSARsaieUgBaHVnW5b O2ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=nfeKVTPOx4lLGqWjSYL0cYLaY1Ole3hW51CK3s0URU8=; b=w+b9fujcE5ngF8fPJTyEQNjp9Hpu8IccCzmurlVFq9ASjqJ47gU3GTUIpPUDL4dvDc 6Uf0xrfR4p8ATW+5f89QFW02ej3nZWUdsxtUC2pGOCTBXYTo97f6hU7AuHWgb85hm8KZ T4nB9uSdggoaVoef7KAvDM4zxcou6c3/kw5cVeXPf/bQqKmXKe4M05AqqhiO0VRwIFei 5H/CUM3QiGK/GE1RH0/HIp9YzaZvMa7mG0S1O5N4+6gy+0dcO34whgxyVT/UVnfNDNgI 41GL7VtL8dB8i7criHO1AXNtGN02kM/KsQUH+/Exoutx60SscgPZ9/SQpL0I5KG7jN17 Jy7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=aiEcXQPm; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Fri, 05 May 2023 08:46:11 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v6 6/9] RISC-V:autovec: Add autovectorization tests for add & sub Date: Fri, 5 May 2023 11:46:04 -0400 Message-Id: <20230505154607.1155567-7-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505154607.1155567-1-collison@rivosinc.com> References: <20230505154607.1155567-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765070018815568427?= X-GMAIL-MSGID: =?utf-8?q?1765070018815568427?= 2023-03-02 Michael Collison Vineet Gupta * gcc.target/riscv/rvv/autovec: New directory for autovectorization tests. * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New test to verify code generation of vector add on rv32. * gcc.target/riscv/rvv/autovec/loop-add.c: New test to verify code generation of vector add on rv64. * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: New test to verify code generation of vector subtract on rv32. * gcc.target/riscv/rvv/autovec/loop-sub.c: New test to verify code generation of vector subtract on rv64. --- .../riscv/rvv/autovec/loop-add-rv32.c | 24 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-add.c | 24 +++++++++++++++++++ .../riscv/rvv/autovec/loop-sub-rv32.c | 24 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-sub.c | 24 +++++++++++++++++++ 4 files changed, 96 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c new file mode 100644 index 00000000000..bdc3b6892e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] + b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c new file mode 100644 index 00000000000..d7f992c7d27 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] + b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c new file mode 100644 index 00000000000..7d0a40ec539 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] - b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c new file mode 100644 index 00000000000..c8900884f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] - b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ From patchwork Fri May 5 15:46:05 2023 Content-Type: text/plain; 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Date: Fri, 5 May 2023 11:46:05 -0400 Message-Id: <20230505154607.1155567-8-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505154607.1155567-1-collison@rivosinc.com> References: <20230505154607.1155567-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765069955712383914?= X-GMAIL-MSGID: =?utf-8?q?1765069955712383914?= While working on autovectorizing for the RISCV port I encountered an issue where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode), where GET_MODE_NUNITS is equal to one. Tested on RISCV and x86_64-linux-gnu. Okay? 2023-03-09 Michael Collison * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a multiple of 2. --- gcc/tree-vect-slp.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc index b299e209b5b..3b7a21724ec 100644 --- a/gcc/tree-vect-slp.cc +++ b/gcc/tree-vect-slp.cc @@ -423,10 +423,13 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count, (GET_MODE_BITSIZE (int_mode), 1); tree vector_type = get_vectype_for_scalar_type (vinfo, int_type, count); + poly_int64 half_nelts; if (vector_type && VECTOR_MODE_P (TYPE_MODE (vector_type)) && known_eq (GET_MODE_SIZE (TYPE_MODE (vector_type)), - GET_MODE_SIZE (base_vector_mode))) + GET_MODE_SIZE (base_vector_mode)) + && multiple_p (GET_MODE_NUNITS (TYPE_MODE (vector_type)), + 2, &half_nelts)) { /* Try fusing consecutive sequences of COUNT / NVECTORS elements together into elements of type INT_TYPE and using the result @@ -434,7 +437,7 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count, poly_uint64 nelts = GET_MODE_NUNITS (TYPE_MODE (vector_type)); vec_perm_builder sel1 (nelts, 2, 3); vec_perm_builder sel2 (nelts, 2, 3); - poly_int64 half_nelts = exact_div (nelts, 2); + for (unsigned int i = 0; i < 3; ++i) { sel1.quick_push (i); From patchwork Fri May 5 15:46:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 90491 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp507288vqo; Fri, 5 May 2023 08:50:08 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5BulnPR7UqvD2aqOtVTf1Xg8V2H3F/AQYED/YF8dDKkvxTbiruYyx72lvliR1iZCQsGxtb X-Received: by 2002:a17:907:608c:b0:962:582d:89c3 with SMTP id ht12-20020a170907608c00b00962582d89c3mr2069647ejc.22.1683301808052; Fri, 05 May 2023 08:50:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683301808; cv=none; d=google.com; s=arc-20160816; b=bVyinCZBRi8VPEHlVfyNaLB9AnjF289XAPs+tqExzoySkis1xHPWUQEwihPKlP1xTy gcPOrTvekyU023ub0QzNrBPJiQMfH2f147KxHzNjV/sXXLoaq01ecLE7xJNAdi60juLU Hl8Q/R+PDUUOnLMtRv8fEV7km8EMr2WaPrnJABeKI6pCWMJOXdLUQHBIJeHUWgewtDQB oCgEld38GnaRQD6LR64tyAkOxFeTe375a9FIBCZL/zgwKgUQk2oEN+sk5gmzN1omCxWW qhvvPVpHHcJ6P6hQ51RnCLRW8Bp395IAJEPQiXSspb2aHb/dhL/xsm4l+Ec2ZRpoRa1y IccA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:dmarc-filter:delivered-to; bh=WNV6xNtsAvEO3u/hQCvJL6iRLcjTfQe1JwnMUHwzqZ8=; b=zacWnF+a2bJsetpzgDCX2lxit7/9i2gu48nvGHzlB+zonE9p/52Ixe208QDFjvjRZL 8dWT8H2WGkB8B+dEMSWukmvvLxTCTaRahd3zdUij4ZY621qKtIm/b71Hwc5OynnGgz+1 pFsnaBd7L8lb5+UBtmcL5CFC8UsckfUJx15qFYd3mMohVzmoYDm02L/VNV4B55QNiwV7 U19QNdNc59YUulNiSuIqBw/NHvC25kwfVZN904eEy01KzcHuzGj3+14ZV/H912haNGvc o2PcCcJwRERvrcuT71K0/0FARtt+rRDzgky2wmhK5TlP1IeA4nR9hSD/vvs20kbwjoLf sxuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=Dl2nuHIZ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765069876377577182?= X-GMAIL-MSGID: =?utf-8?q?1765069876377577182?= 2023-04-05 Michael Collison * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New test to verify code generation of vector "and" on rv32. * gcc.target/riscv/rvv/autovec/loop-and.c: New test to verify code generation of vector "and" on rv64. * gcc.target/riscv/rvv/autovec/loop-div-rv32.c: New test to verify code generation of vector divide on rv32. * gcc.target/riscv/rvv/autovec/loop-div.c: New test to verify code generation of vector divide on rv64. * gcc.target/riscv/rvv/autovec/loop-max-rv32.c: New test to verify code generation of vector maximum on rv32. * gcc.target/riscv/rvv/autovec/loop-max.c: New test to verify code generation of vector maximum on rv64. * gcc.target/riscv/rvv/autovec/loop-min-rv32.c: New test to verify code generation of vector minimum on rv32. * gcc.target/riscv/rvv/autovec/loop-min.c: New test to verify code generation of vector minimum on rv64. * gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: New test to verify code generation of vector modulus on rv32. * gcc.target/riscv/rvv/autovec/loop-mod.c: New test to verify code generation of vector modulus on rv64. * gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: New test to verify code generation of vector multiply on rv32. * gcc.target/riscv/rvv/autovec/loop-mul.c: New test to verify code generation of vector multiply on rv64. * gcc.target/riscv/rvv/autovec/loop-or-rv32.c: New test to verify code generation of vector "or" on rv32. * gcc.target/riscv/rvv/autovec/loop-or.c: New test to verify code generation of vector "or" on rv64. * gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: New test to verify code generation of vector xor on rv32. * gcc.target/riscv/rvv/autovec/loop-xor.c: New test to verify code generation of vector xor on rv64. --- .../riscv/rvv/autovec/loop-and-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-and.c | 24 ++++++++++++++++++ .../riscv/rvv/autovec/loop-div-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-div.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-max-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-max.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-min-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-min.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-mod-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-mod.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-mul-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-mul.c | 24 ++++++++++++++++++ .../riscv/rvv/autovec/loop-or-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-or.c | 24 ++++++++++++++++++ .../riscv/rvv/autovec/loop-xor-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-xor.c | 24 ++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 +++ 17 files changed, 396 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c new file mode 100644 index 00000000000..eb1ac5b44fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c new file mode 100644 index 00000000000..ff0cc2a5df7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c new file mode 100644 index 00000000000..21960f265b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] / b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c new file mode 100644 index 00000000000..bd675b4f6f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] / b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c new file mode 100644 index 00000000000..751ee9ecaa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c new file mode 100644 index 00000000000..f4dbf3f04fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c new file mode 100644 index 00000000000..e51cf590577 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c new file mode 100644 index 00000000000..304f939f6f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c new file mode 100644 index 00000000000..7c497f6e4cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] % b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c new file mode 100644 index 00000000000..7508f4a50d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] % b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c new file mode 100644 index 00000000000..fd6dcbf9c53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] * b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c new file mode 100644 index 00000000000..9fce40890ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] * b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c new file mode 100644 index 00000000000..305d106abd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] | b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c new file mode 100644 index 00000000000..501017bc790 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] | b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c new file mode 100644 index 00000000000..6a9ffdb11d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] ^ b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c new file mode 100644 index 00000000000..c9d7d7f8a75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] ^ b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 4b5509db385..60b620b0875 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -42,10 +42,14 @@ dg-init # Main loop. set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3" +set AUTOVECFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O2 -fno-vect-cost-model -std=c99" + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ "" $CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ + "" $AUTOVECFLAGS # All done. dg-finish From patchwork Fri May 5 15:46:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Collison X-Patchwork-Id: 90494 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp508109vqo; Fri, 5 May 2023 08:51:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6AxWyJIdYDDZOELoVnsXyB/zRg7QxZJFUUSEpDzgViDJziRfMa7XIBBX29MtZ/8D49sgcz X-Received: by 2002:a17:907:934a:b0:958:772e:e926 with SMTP id bv10-20020a170907934a00b00958772ee926mr1578297ejc.24.1683301895659; Fri, 05 May 2023 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Date: Fri, 5 May 2023 11:46:07 -0400 Message-Id: <20230505154607.1155567-10-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505154607.1155567-1-collison@rivosinc.com> References: <20230505154607.1155567-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765069968269640690?= X-GMAIL-MSGID: =?utf-8?q?1765069968269640690?= From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor.c: Ditto --- .../gcc.target/riscv/rvv/autovec/loop-add-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-and-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-div-rv32.c | 10 ++++++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c | 10 ++++++---- .../gcc.target/riscv/rvv/autovec/loop-max-rv32.c | 9 +++++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c | 9 +++++---- .../gcc.target/riscv/rvv/autovec/loop-min-rv32.c | 9 +++++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c | 9 +++++---- .../gcc.target/riscv/rvv/autovec/loop-mod-rv32.c | 10 ++++++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c | 10 ++++++---- .../gcc.target/riscv/rvv/autovec/loop-mul-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-or-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-sub-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-xor-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c | 7 ++++--- 20 files changed, 92 insertions(+), 68 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c index bdc3b6892e9..d2765e67d0d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c index d7f992c7d27..c43f6d3e8cb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c index eb1ac5b44fd..703f4843c2b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c index ff0cc2a5df7..ae74e4c6cc5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c index 21960f265b7..59d379d8647 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c index bd675b4f6f0..aa8ca21bac9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c index 751ee9ecaa3..5e44b3f1a5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c index f4dbf3f04fc..4e4cc3ea97d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c index e51cf590577..128bbed8d79 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c index 304f939f6f9..74e75dd5adc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c index 7c497f6e4cc..23bc5d04bd3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c index 7508f4a50d1..2b1d57a0cb2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c index fd6dcbf9c53..6561633536a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c index 9fce40890ef..08b207f0701 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c index 305d106abd9..58f7b06b5be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c index 501017bc790..7e6b0bed282 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c index 7d0a40ec539..48ae9411872 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c index c8900884f83..23a91e38931 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c index 6a9ffdb11d5..0a65b6261b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c index c9d7d7f8a75..9bfff8e6701 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */