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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z8-20020a170902708800b001a6e719421asi1566992plk.366.2023.05.05.06.29.10; Fri, 05 May 2023 06:29:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=jdElmPln; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232236AbjEENNb (ORCPT + 99 others); Fri, 5 May 2023 09:13:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232265AbjEENNZ (ORCPT ); Fri, 5 May 2023 09:13:25 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 184C71E988; Fri, 5 May 2023 06:13:23 -0700 (PDT) X-UUID: 98783304eb4611ed9cb5633481061a41-20230505 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=fR5zPRr6mGaPjBEV+8bAJ+j1tXb4IEd8qsOXLOLPyjY=; b=jdElmPlncml4I6S6PLDEL5UbBaabr2T7NeeYFOQTdPGy6rSURDRLdX9uHAH14s+Fy+h1ltsUwVeHoWjbm/aggDY92nmjswucfzZMQYQa23IDmjnTXz7DmNK5s1D0lhnegBOt61CC3SMh5vB4wZnrfBLS+oaGa2JgAaNf/8hymBo=; X-CID-UNFAMILIAR: 1 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.23,REQID:8fcf0bc4-0387-49cb-baa3-b57acc2cf018,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:100 X-CID-INFO: VERSION:1.1.23,REQID:8fcf0bc4-0387-49cb-baa3-b57acc2cf018,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:100 X-CID-META: VersionHash:697ab71,CLOUDID:35c5de30-6935-4eab-a959-f84f8da15543,B ulkID:230505211317ZLQ6Q49H,BulkQuantity:0,Recheck:0,SF:29|28|16|19|48|38,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-UUID: 98783304eb4611ed9cb5633481061a41-20230505 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1448119291; Fri, 05 May 2023 21:13:15 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 5 May 2023 21:13:14 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 5 May 2023 21:13:13 +0800 From: Runyang Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski CC: , , , , , Runyang Chen Subject: [PATCH v2 1/2] dt-bindings: reset: mt8188: add thermal reset control bit Date: Fri, 5 May 2023 21:13:07 +0800 Message-ID: <20230505131308.27190-2-runyang.chen@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20230505131308.27190-1-runyang.chen@mediatek.com> References: <20230505131308.27190-1-runyang.chen@mediatek.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765061022112176402?= X-GMAIL-MSGID: =?utf-8?q?1765061022112176402?= To support reset of infra_ao, add the index of infra_ao reset of thermal for MT8188. Signed-off-by: Runyang Chen Acked-by: Krzysztof Kozlowski --- include/dt-bindings/reset/mt8188-resets.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h index 377cdfda82a9..ba9a5e9b8899 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -33,4 +33,9 @@ #define MT8188_TOPRGU_SW_RST_NUM 24 +/* INFRA resets */ +#define MT8188_INFRA_RST1_THERMAL_MCU_RST 0 +#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 +#define MT8188_INFRA_RST3_PTP_CTRL_RST 2 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ From patchwork Fri May 5 13:13:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Runyang Chen X-Patchwork-Id: 90439 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp398180vqo; Fri, 5 May 2023 06:19:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5i452XVs07133kIJln9scARfD4/MChoWMn1CwzTLGbPIX853ERimrBs0PCgQFy/MdUAUxb X-Received: by 2002:a17:90a:ea83:b0:24e:f33:8a1 with SMTP id h3-20020a17090aea8300b0024e0f3308a1mr6899784pjz.1.1683292792534; Fri, 05 May 2023 06:19:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683292792; cv=none; d=google.com; s=arc-20160816; b=PeI0naClHOg0ZOr+QkYqN5eyid+FgY0oh832HvajrJgD9q3gJYEKeADLle/PlDW5T4 OPUmxDwjys81aO7PMfWeSMX/0ocdmP6lC9YBugUPUVjDYhmfQQOJza518pmQGKNSEmHM Yk5c8blZi7b/cwoNm5shTclg00BS/SSzAVJQUmD9bAKepDRMUKrLzXTK72hOt9WZNBu4 D0q+tX3nkDSRcjyQHd71zUy9mbuvs+t4A4Ig7OEupBVKj9iYaB26fjuqbQcpLlUJlZyp yZpM/7NFW10ZoUGqbWQMdn9wH4PQCWlPAsh6BWXhPu/TgfnteDTmUF/l/ZjHK4rAIfG6 FpVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=5N66xXPaesJHbEN2e+y1DB+ADmXl9MaI6t+9Chgeapo=; b=XT6NH+wEFNMNxbaYIkGFjWCsw+fuxIY9v6iC5CNiG41eEz3L0igsJp+Q75O6ewD7ps cF4lNCmQq2mezklOv8loZ0hLSeX7wc4HwSLeTWHO5lrRxfH5GI3UKerAMjq2+9vmAU9C OxJrpOMFC1jB5qAkcDqzqpJ4EZ4gEJXwmngfiqxSvv2aZQp8SrMmDY83LEBzuoJEaZsg QncKXXMqVlma/5Guqsso3hQEpUSo/L4riRx2bFCW3X071li0tZnhk6H2SW0yNsmQqPPR J6M/n3sd7ttuDtkJw5zUStygH92bem/vw8GZAswfiiULLqzGeIAVa7FD+BgG8ALKK71Y Y5/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=OQkRgqbd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Runyang Chen --- drivers/clk/mediatek/clk-mt8188-infra_ao.c | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8188-infra_ao.c b/drivers/clk/mediatek/clk-mt8188-infra_ao.c index 91c35db40b4e..1d4b27ba06be 100644 --- a/drivers/clk/mediatek/clk-mt8188-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8188-infra_ao.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -176,9 +177,32 @@ static const struct mtk_gate infra_ao_clks[] = { "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), }; +static u16 infra_ao_rst_ofs[] = { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static u16 infra_ao_idx_map[] = { + [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2, + [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4, + [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5, +}; + +static struct mtk_clk_rst_desc infra_ao_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infra_ao_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), + .rst_idx_map = infra_ao_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), +}; + static const struct mtk_clk_desc infra_ao_desc = { .clks = infra_ao_clks, .num_clks = ARRAY_SIZE(infra_ao_clks), + .rst_desc = &infra_ao_rst_desc, }; static const struct of_device_id of_match_clk_mt8188_infra_ao[] = {