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[2620:137:e000::1:20]) by mx.google.com with ESMTP id lx13-20020a17090b4b0d00b0023d02932015si6416062pjb.40.2023.05.04.23.54.19; Thu, 04 May 2023 23:54:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q6yy787y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230462AbjEEGlF (ORCPT + 99 others); Fri, 5 May 2023 02:41:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230487AbjEEGlC (ORCPT ); Fri, 5 May 2023 02:41:02 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68ABB15EF5 for ; Thu, 4 May 2023 23:40:52 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-51b0f9d7d70so1257467a12.1 for ; Thu, 04 May 2023 23:40:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683268852; x=1685860852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fcm7rdxyr0xQGgW24k3dhsiALIquYRobfBwbbRtNKtU=; b=Q6yy787yvN0xQS4jJfeyx9C2FRtdQmyTxVJ8w7F4NVmq1evCftj87C9EkmVGTnPf8l A6qvGHwGmgAfiPENVMgd/ZcdntZIopxTdu5XhdtgvN62Eti98pUKbmkWr6FLnMHbGct4 nLi38fMcJKxCPAE064e0H5pgW8KVO87k2jTYE3LDmdqWMbrBkiOQlB5SkCWCkd2621zc T3R4gvJtKzMEpDVja25xIv43yV9q+J69LiHjqEzokeMrljiYvEY08sBPobOkVifdUAxR /xuMi/zd/Y0arjAqhiCUaOBCllhlR6RU7WOyhe+/hIJtL+G4iUyuqiLzNwoBpSeU8OxT QmcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683268852; x=1685860852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fcm7rdxyr0xQGgW24k3dhsiALIquYRobfBwbbRtNKtU=; b=cnAW+aX4fNQRRbOP4Jgy9eaISlaGiaOqFgyusefizW4cG//iR/GfaI1OwxhrDmYnzG +ao14eDw/0MpsjF4F9h/YsN+/6bFbXBlDXrht3EN7h+7Ly9izvYyrOJuMVd+DLYGVswS YGG+yyI8P2KiNlosm/0uxzUZscSPpROW3rL52aAcYuWIxsP5Uip6Cb6hizfeFIVDozqp up4AITNZRNWlqUQSy2x1sQlhD9BjucH94267gANulrfjXIu5McCgGhcjQ8Ck3ilWiqGx C61rfXU8OvewghGwD7vsaGh3Rx9jckgvPGLGZoTuTXO1h2sUlq7O5u70HyaJ3+uNGTiH fwpg== X-Gm-Message-State: AC+VfDwQzYQetnVq7gMlskWs1pf2ErpJ4gpWTDe/sLJR1dNKLamYbq5p rlJZ3bOKfMBfIKlyB31s0SNNeQ== X-Received: by 2002:a17:902:8691:b0:1a5:150f:8558 with SMTP id g17-20020a170902869100b001a5150f8558mr397342plo.17.1683268851927; Thu, 04 May 2023 23:40:51 -0700 (PDT) Received: from localhost.localdomain ([223.233.65.180]) by smtp.gmail.com with ESMTPSA id c4-20020a170902848400b001ab0b2dad2fsm816251plo.211.2023.05.04.23.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 23:40:51 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org Subject: [PATCH v4 1/5] usb: misc: eud: Fix eud sysfs path (use 'qcom_eud') Date: Fri, 5 May 2023 12:10:35 +0530 Message-Id: <20230505064039.1630025-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230505064039.1630025-1-bhupesh.sharma@linaro.org> References: <20230505064039.1630025-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765036184700597738?= X-GMAIL-MSGID: =?utf-8?q?1765036184700597738?= The eud sysfs enablement path is currently mentioned in the Documentation as: /sys/bus/platform/drivers/eud/.../enable Instead it should be: /sys/bus/platform/drivers/qcom_eud/.../enable Fix the same. Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma --- Documentation/ABI/testing/sysfs-driver-eud | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-driver-eud b/Documentation/ABI/testing/sysfs-driver-eud index 83f3872182a4..2bab0db2d2f0 100644 --- a/Documentation/ABI/testing/sysfs-driver-eud +++ b/Documentation/ABI/testing/sysfs-driver-eud @@ -1,4 +1,4 @@ -What: /sys/bus/platform/drivers/eud/.../enable +What: /sys/bus/platform/drivers/qcom_eud/.../enable Date: February 2022 Contact: Souradeep Chowdhury Description: From patchwork Fri May 5 06:40:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 90316 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp198496vqo; Fri, 5 May 2023 00:00:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7xEJpLODL0jGhqJrTESgkSgIsBwQexrCn70T87BjOlrigFLYhoHtbr8b/k8zMTrKjcvFSD X-Received: by 2002:a05:6a20:a10c:b0:ec:a118:6471 with SMTP id q12-20020a056a20a10c00b000eca1186471mr415175pzk.50.1683270036702; Fri, 05 May 2023 00:00:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683270036; cv=none; d=google.com; s=arc-20160816; b=iL1MRhwg+uSYJDq8gMrxt29VbajwgdwZu3bmqNWJB9YSec7vPJy83zPcC+xau39jVt OZESEPae3I6tcXD1Qauq0uiexnuXUCIWn45re9w33r955gLUOJ5edTpFj2FljBGYnu5a UPiSFLN5trsZM7Ba8xi0YbsUAlCbK1wim+60lUIbnnPpANUcuZEFD7rsA/JAWp+5nX1Q /TF630E7LKTQxCu5VztRb7td7bIzz+CXuwOdYl+jVY7yAtu1YTJrQCxRiDANAN1TrCtA qgoHQOeYAWTRCEb5A9v4rLs9+wpM7AUIlcZvnDqXEUz+q5lKEYPf6GoUyvupuKLYUA1Q JncQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tpKnP1YDIVbRZiADGr23D8oPufyg/cq5r9T3i6z6bvI=; b=Asl7O50bksVMK7O5EfUyaU5wLG/8f6ERnnoygck2pPZYilQTjt8xMKp7iT4p1T53Es +FnEbk57CfRPH9mzhxf79y4Ty8BcTmrk0SVORHnosVXy2jMJDXF3uawjMtnVGdvPkKlC 8rN9BSwUy1By3KYcDAQVjsoojmEzl6EZU2sZfNTv5GoOYvYDAwBDf9d5kw/MWgHr8tHj Dd3h6p+8wlbigNV8TI7RM1+vVFVekmsI+8jnVGfE1SV5P+KgGD2T/5OqjfYJ4kzfugKs ChXIwLDtNzwKZpR3Yj7DTchJO1lKkmySlGwvnaQcAX7u0SIzhRfzOCFm0GCkzF1ZhJYX T9Cg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WDGKOcE/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' the eud module. So, update the dt-bindings to accommodate the third register property (TCSR Base) required by the driver on these SoCs. Also for these SoCs, introduce a new bool property 'qcom,secure-mode-enable', which indicates that the mode manager needs to be accessed only via the secure world. Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437..3b92cdf4e306 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,17 +18,33 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud reg: + minItems: 2 items: - description: EUD Base Register Region - description: EUD Mode Manager Register + - description: TCSR Base Register Region + + reg-names: + minItems: 2 + items: + - const: eud-base + - const: eud-mode-mgr + - const: tcsr-base interrupts: description: EUD interrupt maxItems: 1 + qcom,secure-mode-enable: + type: boolean + description: + Indicates that the mode manager needs to be accessed only via the secure + world (through 'scm' calls). + ports: $ref: /schemas/graph.yaml#/properties/ports description: From patchwork Fri May 5 06:40:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 90315 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp197784vqo; Thu, 4 May 2023 23:59:07 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5T4Q+kQA2BwCnsHLcbkZb0nGUM8oPYFDFSJa0sK+KBK5QgFx2EgAz2mYcBT8vnoJ9LsbLa X-Received: by 2002:a17:902:ea0f:b0:1a6:fe25:412b with SMTP id s15-20020a170902ea0f00b001a6fe25412bmr476411plg.26.1683269947478; Thu, 04 May 2023 23:59:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683269947; cv=none; d=google.com; s=arc-20160816; b=TzCAkFstjWeHylmWU68JWHux3ZoDu/eWwe2KNLwVoGcyMRdO0WgNAk2CmkELYpVUIZ mTkgkqndgG4nD+96am+BzNyIxuE8/GXLnOGXPvQIgZW/+seIFoGktfF44SttCYsZ1iP1 qm6L9r3yBTYuf+fJLSa9DMozpNSOq1UG/qAilB5NB76b4cG6E6oPrUMJ1R9ZoqrOX9qC QfyXkQQDIL6lJlzEnW76uVP4j/pZ8G8yPrFDjS0crPtPZvPV3sGL74p0GmL1lQFfS6Uw az4JiNg3AyvM0wLKAYxLrn1iVhn5uSBqz27w/u+aOEZzCLVCLenHe9lCH7qelJb4wO67 52mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DxVNud7lt4L0J09lKeSHXN8bCCY+H6qtBEVB86DAgHc=; b=sGFulXpH0LH9z9cvjPzNkGhZyc7ENZ1n07Juru9cHFc+KqzEA2Rt2aUhw/QZkp9Zuz hVJIC7kLAJQD4DydjdaVTCcx0cX7eWkV8WsATSnskAgr9DEOZwVLLaFLmjpOEqExL5et 0BrqOSan1VIEDjkY9qonYumI/touYtAmrmuop2HW+WOhNJj6as8hHVt/+kSQLzc2m+Xj 7yNzT34OZCZmoXFG5uZD14X1xyOv6wbrVHbJeGdzR1ot2nJpgEg4vJD66JGKSeN+5E8P f4HC8AZMlqYsHLVJAu3SKYkNjEZoLU1eGynxlPMpflwZUXheDk/ozvKuJo48dY1p6Mt2 HyGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pG6cxxOn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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On some SoCs (like the SM6115 / SM4250 SoC), the mode manager needs to be accessed only via the secure world (through 'scm' calls). Also, the enable bit inside 'tcsr_check_reg' needs to be set first to set the eud in 'enable' mode on these SoCs. Since this difference comes from how the firmware is configured, so the driver now relies on the presence of an extra boolean DT property to identify if secure access is needed. Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/Kconfig | 1 + drivers/usb/misc/qcom_eud.c | 74 +++++++++++++++++++++++++++++++++---- 2 files changed, 68 insertions(+), 7 deletions(-) diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index 99b15b77dfd5..fe1b5fec1dfc 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -147,6 +147,7 @@ config USB_APPLEDISPLAY config USB_QCOM_EUD tristate "QCOM Embedded USB Debugger(EUD) Driver" depends on ARCH_QCOM || COMPILE_TEST + select QCOM_SCM select USB_ROLE_SWITCH help This module enables support for Qualcomm Technologies, Inc. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index b7f13df00764..18a2dee3b4b9 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -5,12 +5,14 @@ #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -22,23 +24,35 @@ #define EUD_REG_VBUS_INT_CLR 0x0080 #define EUD_REG_CSR_EUD_EN 0x1014 #define EUD_REG_SW_ATTACH_DET 0x1018 -#define EUD_REG_EUD_EN2 0x0000 +#define EUD_REG_EUD_EN2 0x0000 #define EUD_ENABLE BIT(0) -#define EUD_INT_PET_EUD BIT(0) +#define EUD_INT_PET_EUD BIT(0) #define EUD_INT_VBUS BIT(2) #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) +#define EUD_EN2_SECURE_EN BIT(0) +#define EUD_EN2_NONSECURE_EN (1) +#define EUD_EN2_DISABLE (0) +#define TCSR_CHECK_EN BIT(0) + +struct eud_soc_cfg { + u32 tcsr_check_offset; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; + const struct eud_soc_cfg *eud_cfg; void __iomem *base; void __iomem *mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + bool secure_mode_enable; + phys_addr_t secure_mode_mgr; }; static int enable_eud(struct eud_chip *priv) @@ -46,7 +60,11 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_SECURE_EN); + else + writel(EUD_EN2_NONSECURE_EN, priv->mode_mgr + EUD_REG_EUD_EN2); return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +72,11 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_DISABLE); + else + writel(EUD_EN2_DISABLE, priv->mode_mgr + EUD_REG_EUD_EN2); } static ssize_t enable_show(struct device *dev, @@ -178,6 +200,8 @@ static void eud_role_switch_release(void *data) static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; + phys_addr_t tcsr_base, tcsr_check; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); @@ -200,9 +224,40 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(chip->mode_mgr)) - return PTR_ERR(chip->mode_mgr); + chip->secure_mode_enable = of_property_read_bool(chip->dev->of_node, + "qcom,secure-mode-enable"); + /* + * EUD block on a few Qualcomm SoCs need secure register access. + * Check for the same. + */ + if (chip->secure_mode_enable) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get secure_mode_mgr reg base\n"); + + chip->secure_mode_mgr = res->start; + } else { + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->mode_mgr)) + return PTR_ERR(chip->mode_mgr); + } + + /* Check for any SoC specific config data */ + chip->eud_cfg = of_device_get_match_data(&pdev->dev); + if (chip->eud_cfg) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr-base"); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get tcsr reg base\n"); + + tcsr_base = res->start; + tcsr_check = tcsr_base + chip->eud_cfg->tcsr_check_offset; + + ret = qcom_scm_io_writel(tcsr_check, TCSR_CHECK_EN); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n"); + } chip->irq = platform_get_irq(pdev, 0); ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, @@ -230,8 +285,13 @@ static int eud_remove(struct platform_device *pdev) return 0; } +static const struct eud_soc_cfg sm6115_eud_cfg = { + .tcsr_check_offset = 0x25018, +}; + static const struct of_device_id eud_dt_match[] = { { .compatible = "qcom,sc7280-eud" }, + { .compatible = "qcom,sm6115-eud", .data = &sm6115_eud_cfg }, { } }; MODULE_DEVICE_TABLE(of, eud_dt_match); From patchwork Fri May 5 06:40:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 90310 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp192721vqo; Thu, 4 May 2023 23:45:33 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6Ep1m0OZJWMhXEn5VkHnGAHdOA+LGwvDK3e4m2kMhhZrwricTv6DVJkQ/auFKnP7tQ3RdZ X-Received: by 2002:a05:6a20:6a04:b0:f0:cef6:9d2e with SMTP id p4-20020a056a206a0400b000f0cef69d2emr581641pzk.28.1683269133055; Thu, 04 May 2023 23:45:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683269133; cv=none; d=google.com; s=arc-20160816; b=GQryONgyige5psyQb7ScFVkdfYMWyXB8fun3XCnzglnpMcSsySZA51yvFFyawoCrpX uMtaLAoqISDlE9Hn2eoSoYdnkS7959BnXjfgIgd/ydID3GiVkKIScW5N0VvvTURpu4vL 1jSO047D60MjpmPDyIJUN8WWsVN9n/BFVgmixjbIFn+Lp7ohcrEmstYcPE6EM1eHlKWO SzpILYZ/oDSDJ8H5n/ztflIebV58IjKCucPv68NuUeCgGhjMuI7CcLduyabIfVhAZ/Fo 0FTZvErCTxj/TM8DnfYI8xRCj1OE6gpwFjxkosRpNm0hz/RwIE3eMUg9YIhMH71em1Pp covA== ARC-Message-Signature: i=1; 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The node contains EUD base register region, EUD mode manager register region and TCSR Base register region along with the interrupt entry. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. To enable the role switch, we need to set dr_mode = "otg" property for 'usb_dwc3' sub-node in the board dts file. Also the EUD device can be enabled on a board once linux is boot'ed by setting: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/../enable Signed-off-by: Bhupesh Sharma Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index f67863561f3f..61a0af33ca43 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -180,6 +180,18 @@ core3 { }; }; + eud_typec: connector { + compatible = "usb-c-connector"; + + ports { + port@0 { + con_eud: endpoint { + remote-endpoint = <&eud_con>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-sm6115", "qcom,scm"; @@ -647,6 +659,38 @@ gcc: clock-controller@1400000 { #power-domain-cells = <1>; }; + eud: eud@1610000 { + compatible = "qcom,sm6115-eud", "qcom,eud"; + reg = <0x0 0x01610000 0x0 0x2000>, + <0x0 0x01612000 0x0 0x1000>, + <0x0 0x003c0000 0x0 0x40000>; + reg-names = "eud-base", "eud-mode-mgr", "tcsr-base"; + interrupts = ; + qcom,secure-mode-enable; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; + }; + }; + }; + usb_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; reg = <0x0 0x01613000 0x0 0x180>; @@ -1144,6 +1188,13 @@ usb_dwc3: usb@4e00000 { snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + usb-role-switch; + + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; + }; + }; }; }; From patchwork Fri May 5 06:40:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 90321 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp209886vqo; Fri, 5 May 2023 00:25:26 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7z4PGJlXjE9sBmrpHiBVTTFINarvVKAQS+4cwFRxd+DPGlx7IGuvTGLY0UO7fw59kHhsbm X-Received: by 2002:a05:6a20:54a1:b0:f2:6d58:ae8e with SMTP id i33-20020a056a2054a100b000f26d58ae8emr799114pzk.5.1683271526093; Fri, 05 May 2023 00:25:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683271526; cv=none; d=google.com; s=arc-20160816; b=rjEw572TiZGHG4S4KIyDO+IWdB36M9o5RdnJi7SppNOUBGGcldxVwjUB8+VZsOHOLY ejcXSISkXI+PZWQtDtkxYEOoZr66OwHq2U7Wz5p15PUzghvz7dVYolpzFJB4QzwiIStZ WGdo/M2Pr7Hio6Zer1bvTst1Ykg8JzuzgKNOCvHystI69iKp5OzH9STZDr56eXQGZ8eb sqPgD0yVWfvE1non+nh0TKjFSqfWC4KNQwnMQxu+eSFzbopSKQaSEmOgbq1EuZgTMBkc 6bGQ7s7qxQg+Pd9BBYsoj0xA7pWsjbNiVxadBKRC3hit2JCN7j/wAVB7cdQPQt4gd1KJ c25A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fz6g2/625qlFmhiR93VnIJ+EVOsf12tbuuuDirZwZ9U=; b=ySuLpDnXoIke9dQavkl7uzgU6kItgYZQb8xw6Ef8Qu7q7lcIOPFEiSGa9rv+zhDT83 2G368rpCjtbCJJ65pDaIYmw50vRuTit6d/e8HqhZwrQXomFEmTgqj+p9fwPIzY60xDBJ 9qb57icOzTzyq4PieNkqV1rLOttccsrnrFHZ9xKXwDgz7hj3tgbGPOwpeE37o6rFwXx0 UPXpr2NBhzL5oTnlyne1sS6dvOp1FD4KlZaqe3NlA6bwbQvWYLKFPVOsbMrlyrFBWK0e nTYbthwtUtUq21AEsgBbrpEtcLZWOtpbHaMwz0cmKe/OMk/76HVc0B7E9X4/nQ8WkEYX YEog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MmA7Y+uU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Now, the EUD debug peripheral can be enabled by executing: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/1610000.eud/enable Signed-off-by: Bhupesh Sharma Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 27 +++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 1a0776a0cfd0..0ce72f1ebc10 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -30,6 +30,10 @@ vph_pwr: vph-pwr-regulator { }; }; +&eud { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -253,7 +257,28 @@ &usb { &usb_dwc3 { maximum-speed = "super-speed"; - dr_mode = "peripheral"; + + /* + * There is only one USB DWC3 controller on QRB4210 board and it is connected + * via a DIP Switch: + * - to either an USB - C type connector or an USB - A type connector + * (via a GL3590-S hub), and + * - to either an USB - A type connector (via a GL3590-S hub) or a connector + * for further connection with a mezzanine board. + * + * All of the above hardware muxes would allow us to hook things up in + * different ways to some potential benefit for static configurations (for e.g. + * on one hand we can have two USB - A type connectors and a USB - Ethernet + * connection available and on the other we can use the USB - C type in + * peripheral mode). + * + * Note that since the USB - C type can be used only in peripehral mode, + * so hardcoding the mode to 'peripheral' here makes sense. + * + * However since we want to use the EUD debug device, we set the mode as + * 'otg' here. + */ + dr_mode = "otg"; }; &usb_hsphy {