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[8.43.85.97]) by mx.google.com with ESMTPS id f13-20020a50ee8d000000b0050c064800a9si2023681edr.100.2023.05.04.22.21.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 22:21:58 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5803C3856DE7 for ; Fri, 5 May 2023 05:21:53 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id 80E143858D20 for ; Fri, 5 May 2023 05:21:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 80E143858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp79t1683264082twka7ex3 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 05 May 2023 13:21:21 +0800 (CST) X-QQ-SSF: 01400000000000F0Q000000A0000000 X-QQ-FEAT: dE9SBKWxUELwc0N1Gde4HsCqxSU2tw0k+BC0z0jo2ESJcXQrrOA4QVdNp1Gob WvLRnYZ+6yu16hkH7H5+jW9RynysKrd5jSfv85MAuvNC0K4CSob/+nBXExgYVoTVfyVolYL IevdW6Fi5M/P4KvvrS9whX1LM25MdF+mph1eHiZxRjSyswcWdTYlWfI6jAYeXV5C7GmcuvY DW1lS+nMhI9zhb7vHcU/eLQX19zzO4SOJ059sy/PhzI+BxC6i6nmSdN8vIBkpoJcGa6medh g4QKAQYHJxbcP4AP+F31oaf115hDGs0ckGmfVaMJQZJjPqO/DioUvoCMp2++dppVrGpM88t joS9hevLskHU1am8NqfRdiUm0CuvAxrSLImvO/zsqNlzTO6PJNjV/PVzlkUlA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6253410804783694842 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix PR109615 Date: Fri, 5 May 2023 13:21:20 +0800 Message-Id: <20230505052120.1074528-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765030356358987934?= X-GMAIL-MSGID: =?utf-8?q?1765030356358987934?= From: Juzhe-Zhong Before this patch: ... .L2: addi a4,a1,100 add t1,a0,a2 mv t0,a0 beq a2,zero,.L1 vsetvli zero,a3,e8,mf8,tu,mu .L4: addi a6,t0,100 addi a7,a4,-100 vle8.v v1,0(t0) addi t0,t0,1 vse8.v v1,0(a7) vlm.v v0,0(a6) vle8.v v1,0(a6),v0.t vse8.v v1,0(a4) addi a4,a4,1 bne t0,t1,.L4 addi a0,a0,300 addi a1,a1,300 add a2,a0,a2 vsetvli zero,a3,e8,mf8,ta,ma .L5: vle8.v v2,0(a0) addi a0,a0,1 vse8.v v2,0(a1) addi a1,a1,1 bne a2,a0,.L5 .L1: ret After this patch: ... .L2: addi a4,a1,100 add t1,a0,a2 mv t0,a0 beq a2,zero,.L1 vsetvli zero,a3,e8,mf8,tu,mu .L4: addi a6,t0,100 addi a7,a4,-100 vle8.v v1,0(t0) addi t0,t0,1 vse8.v v1,0(a7) vlm.v v0,0(a6) vle8.v v1,0(a6),v0.t vse8.v v1,0(a4) addi a4,a4,1 bne t0,t1,.L4 addi a0,a0,300 addi a1,a1,300 add a2,a0,a2 .L5: vle8.v v2,0(a0) addi a0,a0,1 vse8.v v2,0(a1) addi a1,a1,1 bne a2,a0,.L5 .L1: ret PR target/109615 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (avl_info::multiple_source_equal_p): Add denegrate PHI optmization. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Adapt testcase. * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Ditto. * gcc.target/riscv/rvv/vsetvl/pr109615.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 81 +++++-------------- .../riscv/rvv/vsetvl/avl_single-74.c | 4 +- .../gcc.target/riscv/rvv/vsetvl/pr109615.c | 33 ++++++++ .../gcc.target/riscv/rvv/vsetvl/vsetvl-11.c | 2 +- 4 files changed, 54 insertions(+), 66 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 609f86d8704..39b4d21210b 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1676,72 +1676,27 @@ avl_info::single_source_equal_p (const avl_info &other) const bool avl_info::multiple_source_equal_p (const avl_info &other) const { - /* TODO: We don't do too much optimization here since it's - too complicated in case of analyzing the PHI node. + /* When the def info is same in RTL_SSA namespace, it's safe + to consider they are avl compatible. */ + if (m_source == other.get_source ()) + return true; - For example: - void f (void * restrict in, void * restrict out, int n, int m, int cond) - { - size_t vl; - switch (cond) - { - case 1: - vl = 100; - break; - case 2: - vl = *(size_t*)(in + 100); - break; - case 3: - { - size_t new_vl = *(size_t*)(in + 500); - size_t new_vl2 = *(size_t*)(in + 600); - vl = new_vl + new_vl2 + 777; - break; - } - default: - vl = 4000; - break; - } - for (size_t i = 0; i < n; i++) - { - vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); - __riscv_vse8_v_i8mf8 (out + i, v, vl); + /* We only consider handle PHI node. */ + if (!m_source->insn ()->is_phi () || !other.get_source ()->insn ()->is_phi ()) + return false; - vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl); - __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl); - } + phi_info *phi1 = as_a (m_source); + phi_info *phi2 = as_a (other.get_source ()); - size_t vl2; - switch (cond) - { - case 1: - vl2 = 100; - break; - case 2: - vl2 = *(size_t*)(in + 100); - break; - case 3: - { - size_t new_vl = *(size_t*)(in + 500); - size_t new_vl2 = *(size_t*)(in + 600); - vl2 = new_vl + new_vl2 + 777; - break; - } - default: - vl2 = 4000; - break; - } - for (size_t i = 0; i < m; i++) - { - vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl2); - __riscv_vse8_v_i8mf8 (out + i + 300, v, vl2); - vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 200, vl2); - __riscv_vse8_v_i8mf8 (out + i + 200, v2, vl2); - } - } - Such case may not be necessary to optimize since the codes of defining - vl and vl2 are redundant. */ - return m_source == other.get_source (); + if (phi1->is_degenerate () && phi2->is_degenerate ()) + { + /* Case 1: If both PHI nodes have the same single input in use list. + We consider they are AVL compatible. */ + if (phi1->input_value (0) == phi2->input_value (0)) + return true; + } + /* TODO: We can support more optimization cases in the future. */ + return false; } avl_info & diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c index ff540ec792d..cc4f88be888 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c @@ -23,5 +23,5 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int cond, size_t vl, } } -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c new file mode 100644 index 00000000000..90b0bb79937 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond) +{ + size_t vl = 101; + if (cond) + vl = m * 2; + else + vl = m * 2 * vl; + + for (size_t i = 0; i < n; i++) + { + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl); + __riscv_vse8_v_i8mf8 (out + i, v, vl); + + vbool64_t mask = __riscv_vlm_v_b64 (in + i + 100, vl); + + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in + i + 100, vl); + __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl); + } + + for (size_t i = 0; i < n; i++) + { + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl); + __riscv_vse8_v_i8mf8 (out + i + 300, v, vl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c index fa825f031f9..3ef0fdcb66d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c @@ -18,4 +18,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int c } } -/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */