From patchwork Thu May 4 17:14:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Moreira Zinsly X-Patchwork-Id: 90154 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp482564vqo; Thu, 4 May 2023 10:15:07 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5aRZfA4UVh0ZxeSeB28hb4lepZQhwfyifYYpxTwQYwazs/Gqhq6qq7KNO3lKrzSK2tqnXi X-Received: by 2002:a17:907:3e02:b0:965:d17b:26d with SMTP id hp2-20020a1709073e0200b00965d17b026dmr188903ejc.35.1683220506800; Thu, 04 May 2023 10:15:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683220506; cv=none; d=google.com; s=arc-20160816; b=OO/FTVpIIwA184liMtdUlVlEBej3uwcI3echpIlf+XiMjmCXXBn75AmjZkqJepKHPk ZgpQQLtNgFzOwngn4cJrtwVDzIcAevRWMTZg8Xw+w23ngj/K2E6i8vxA5I560uRO76J+ i5RqA4RB63DJ4tx7apvOGTX/+YcOOheo2eW+fodloA4HnCgqpUDrYvATq6vmAyb4Matw gag+k9ZM3Ara2ydSdFGrBKMWlYCXaDHf8ZblIkV2HR+NT1aFpA2ow5TYBL5Sf9JcpTmK Td5Z2av6evDshbWOLsX4JBKgsL4WRm9sRbWrwmet3MvqyHUCM1SrLlHxFaluJPaP61wN bVcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature :dmarc-filter:delivered-to; bh=Ya62mUwOby3GKTXeO88kyI+FKL9nhyzxzr2ODgcM/mU=; b=XqQnZn/taBII9AgNgQs3ZQVmAfqSkCKwfKpMvIL0IXwFAvG7hqvrnqw4cPai+DC+sT o57Z20U7RbF1fYa8AxF1tXe4Us2FuUIX4l5Z9FaH18GfCQ8blyMbg9wOxf+CKPq4bIx8 y6kfFjT+Sbr0fqL2piP4xiaTQbQfZX7Scsj/6hEFsjUBJKCMMUy+baTFaLMrQB9XNI29 4Sdm/K4lJcgBnk/w+rvkAZ3ao9PS2K/zHvPWkF5g8EYRx81C3ImGjVCgMQj07m75Zif7 0MEFRCiU1xnJhOqQ/+bSdjdbAjFkYvT4wnbid6PUnFOq9ii9xqQg5s9oFoNz6GKfOwEb DUJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=h0qMzyfN; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id os18-20020a170906af7200b0095389804380si26030494ejb.220.2023.05.04.10.15.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 10:15:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=h0qMzyfN; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 988B13856DD2 for ; Thu, 4 May 2023 17:14:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oi1-x22b.google.com (mail-oi1-x22b.google.com [IPv6:2607:f8b0:4864:20::22b]) by sourceware.org (Postfix) with ESMTPS id 6445A3858D33 for ; Thu, 4 May 2023 17:14:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6445A3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-38dfdc1daa9so435214b6e.1 for ; Thu, 04 May 2023 10:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683220472; x=1685812472; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Ya62mUwOby3GKTXeO88kyI+FKL9nhyzxzr2ODgcM/mU=; b=h0qMzyfNIqWsncm6dNf8IGfAo7f2JY2yQS6nxsBmYfBmdJVPEeAwXPnCVjSxi1YHiT kF3wk3s3guvR7F/mWJeuhrSU8Su2dCwdI/K1XWK7kywNxziBnrEXKAo+ImSP+SfUZCW2 tlKBPS6VF72yhZC2FgxdaUwEv1/UzMLFy2bj2D3KbYgV7y4sTHfucmlS50oVQpLEtaI2 +pnePSF+5s7MrO9Cu4hcQBF9d5xfwNFdEh5GOJKlncjRC1Eb7T0EDBzsjfocfMuPK7u0 0ywplAZ39si0bX5C8MCeO5yzDLYcfcpGbhLt9HdKje/Oa6IXr6uLvuIv4F5Rx7ol5IMY 7q7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683220472; x=1685812472; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Ya62mUwOby3GKTXeO88kyI+FKL9nhyzxzr2ODgcM/mU=; b=b4n2u49VHfF+CXd5hqrT4TAqjzpfurJ0xGVB4775GMsH5qFMFdiW92xv7+9ongaSNT Dt8cZaVrXqk5c/z3UEgMOaKJq5gH45Oh1qV3zV/c9aMSFNV9Xs5Q+m7pJsq9gwwoo9Y2 b4U3rMKFFLqi12+pkNNGtD7xLzymjWO1nT6oPE+p5vPXb/M0V3ob4n84nqSZpmLtvBR1 2+2G9vrplaPdJHLehlP4WqXdtwXBSsUAzSpxv93wW1+qmmT6+IOXaKhPl1X0sCygEiSL S6kuVu3PIphB4uQpNgoBvD1TegynqByBmOpzAOnr/X86W42IpY5AeltMOVsk4HV3pQdr 2Ugg== X-Gm-Message-State: AC+VfDxDSgHY+ugmg0IA5ey2rKpwpqwsDpWRIM5QmxCBXDYgoF89VURt UxcDNZJN6JtcjIsPmMwk4ReECg4RKCh0s2FNtO2JYw== X-Received: by 2002:a05:6808:309b:b0:38d:ef18:53b9 with SMTP id bl27-20020a056808309b00b0038def1853b9mr2361328oib.10.1683220472376; Thu, 04 May 2023 10:14:32 -0700 (PDT) Received: from marvin.. ([2804:14d:bac2:9b0b::1000]) by smtp.gmail.com with ESMTPSA id t11-20020a0568080b2b00b0038eeba6fce1sm1791455oij.55.2023.05.04.10.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 10:14:32 -0700 (PDT) From: Raphael Moreira Zinsly To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, vineetg@rivosinc.com, shihua@iscas.ac.cn, Raphael Moreira Zinsly Subject: [PATCH] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] Date: Thu, 4 May 2023 14:14:21 -0300 Message-Id: <20230504171421.1829763-1-rzinsly@ventanamicro.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764984626184605238?= X-GMAIL-MSGID: =?utf-8?q?1764984626184605238?= We were not able to match the CTZ sign extend pattern on RISC-V because it get optimized to zero extend and/or to ANDI patterns. For the ANDI case, combine scrambles the RTL and generates the extension by using subregs. gcc/ChangeLog: PR target/106888 * config/riscv/bitmanip.md (disi2): Match with any_extend. (disi2_sext): New pattern to match with sign extend using an ANDI instruction. gcc/testsuite/ChangeLog: PR target/106888 * gcc.target/riscv/pr106888.c: New test. * gcc.target/riscv/zbbw.c: Check for ANDI. --- gcc/config/riscv/bitmanip.md | 14 +++++++++++++- gcc/testsuite/gcc.target/riscv/pr106888.c | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/zbbw.c | 1 + 3 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr106888.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index a27fc3e34a1..8dc3e85a338 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -246,13 +246,25 @@ (define_insn "*disi2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI + (any_extend:DI (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))] "TARGET_64BIT && TARGET_ZBB" "w\t%0,%1" [(set_attr "type" "") (set_attr "mode" "SI")]) +;; A SImode clz_ctz_pcnt may be extended to DImode via subreg. +(define_insn "*disi2_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (subreg:DI + (clz_ctz_pcnt:SI (subreg:SI + (match_operand:DI 1 "register_operand" "r") 0)) 0) + (match_operand:DI 2 "const_int_operand")))] + "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)" + "w\t%0,%1" + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) + (define_insn "*di2" [(set (match_operand:DI 0 "register_operand" "=r") (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/riscv/pr106888.c b/gcc/testsuite/gcc.target/riscv/pr106888.c new file mode 100644 index 00000000000..77fb8e5b79c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106888.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ + +int +ctz (int i) +{ + int res = __builtin_ctz (i); + return res&0xffff; +} + +/* { dg-final { scan-assembler-times "ctzw" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c index 709743c3b68..f7b2b63853f 100644 --- a/gcc/testsuite/gcc.target/riscv/zbbw.c +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c @@ -23,3 +23,4 @@ popcount (int i) /* { dg-final { scan-assembler-times "clzw" 1 } } */ /* { dg-final { scan-assembler-times "ctzw" 1 } } */ /* { dg-final { scan-assembler-times "cpopw" 1 } } */ +/* { dg-final { scan-assembler-not "andi\t" } } */