From patchwork Thu May 4 08:56:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: HAO CHEN GUI X-Patchwork-Id: 90000 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp156228vqo; Thu, 4 May 2023 01:57:20 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4oHhBKakme7LznDoEvZx0oREB9tzSciefSCy5T+T4iXwZqh7YX1Rvd9mx/qTCTOUKj4ELz X-Received: by 2002:a17:906:fe05:b0:94f:5e17:e80d with SMTP id wy5-20020a170906fe0500b0094f5e17e80dmr6844718ejb.45.1683190640579; Thu, 04 May 2023 01:57:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683190640; cv=none; d=google.com; s=arc-20160816; b=KRyDeYd8d4Cot13a9foYvyLewQ8Cegfbv3A8d78Xe4+/mU/48x51S5Ymh1e/BlqEvI MvSTZQscDIzVYQMVh4VObnW+2iHw3KgFDkbIsMMKMjHohzdlg8AQFGw6cjMlfCb+B7d2 Z66ZSjqJCk9LpYclCW5PkLO2OdrFZM9FuvQbhWj5dAWXlbdjEcX+TE5iZ7c3XuXgWPJl FrtFbLrtfMn9DXVdlUznvV+RdzKh9t6EPfpxVLpA/baBBEDZxWXXfXDaqA9CTWWaI485 Oa5d3YULJO4Jyqf5DPWnrzAsY0Yxwj+5uaPuwADCqd+U9l49hlWJSewjSbMeV7x9E5pz uzYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:subject:cc:to:content-language:user-agent :mime-version:date:message-id:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=NTGb7daIMiQVLeopTDx5PAKKeiPwmVquHLJdDqMWEe8=; b=wf5Fxse2fgOWvrIo56PgImbWrgReyOb8YiqBu2J8GQc6VjpYpfapR5onUogVLjZK+i hMov+a/EdCzBQIQTkhILfDMwTlTN0BDoq2RK3bkzbKImSarWRpPnMoqnX7drrR3UIjC6 K4HARIjvs3ouHphGcQ8WAPGdj1Kg60i4T3XmSkfZ5Ap9Yt0EMH8g84bbxIcLA68zVuSg llsfqOp3HLRwcwk8jIbRNMYqrS9srfZMOx6BjNVzPWRJXcgegPjN7SyC2HanfjMR/z6A c80v+sml/BF9JXxX2+CD0rHO7mAHLBB7w1JDg71U3kPvuyzp7tVAcn8pLREdtNAdyF/z n4/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=KUDnCI7l; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id os18-20020a170906af7200b0095389804380si25388929ejb.220.2023.05.04.01.57.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 01:57:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=KUDnCI7l; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6CDE5385734D for ; Thu, 4 May 2023 08:57:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6CDE5385734D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683190639; bh=NTGb7daIMiQVLeopTDx5PAKKeiPwmVquHLJdDqMWEe8=; h=Date:To:Cc:Subject:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=KUDnCI7ljWUhtMvQSHHG8QPapYrWQHhWNycy9uZWBAo85lkH+0TOPzrRsdX9v4vf4 gXg2Z7Xga0h/GGZbJZ/8cWwfVVpaZS0EuERAGFnwtYbgOBou5QuOz8OEWQzBerSPlg Ny23K3Y/tCDiZZaxxEUHHFcKSq3dzraTuFEIve7s= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id B5A573858D28 for ; Thu, 4 May 2023 08:56:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B5A573858D28 Received: from pps.filterd (m0353722.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3448igAv017400; Thu, 4 May 2023 08:56:31 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qc9f5rhd4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 May 2023 08:56:30 +0000 Received: from m0353722.ppops.net (m0353722.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3448k3qE025288; Thu, 4 May 2023 08:56:30 GMT Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qc9f5rhch-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 May 2023 08:56:30 +0000 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3442pTqf003240; Thu, 4 May 2023 08:56:28 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma04ams.nl.ibm.com (PPS) with ESMTPS id 3q8tv6tr70-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 May 2023 08:56:28 +0000 Received: from smtpav06.fra02v.mail.ibm.com (smtpav06.fra02v.mail.ibm.com [10.20.54.105]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3448uO1n13828470 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 4 May 2023 08:56:24 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8C71D20049; Thu, 4 May 2023 08:56:24 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A2D0B20040; Thu, 4 May 2023 08:56:22 +0000 (GMT) Received: from [9.197.235.133] (unknown [9.197.235.133]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 4 May 2023 08:56:22 +0000 (GMT) Message-ID: <47adfd48-c6b6-c1d9-02c4-398d300ec5ba@linux.ibm.com> Date: Thu, 4 May 2023 16:56:22 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner Subject: [PATCHv2, rs6000] Splat vector small V2DI constants with ISA 2.07 instructions [PR104124] X-TM-AS-GCONF: 00 X-Proofpoint-GUID: hUsCWeg3sP17YqGgX2W6qGKA_j9h4mXG X-Proofpoint-ORIG-GUID: g4VYiw4OxVZ3lk4cQfhs3081Gttk5p6X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-04_04,2023-05-03_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 impostorscore=0 bulkscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305040069 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: HAO CHEN GUI via Gcc-patches From: HAO CHEN GUI Reply-To: HAO CHEN GUI Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764953309153539879?= X-GMAIL-MSGID: =?utf-8?q?1764953309153539879?= Hi, This patch adds a new insn for vector splat with small V2DI constants on P8. If the value of constant is in RANGE (-16, 15) and not 0 or -1, it can be loaded with vspltisw and vupkhsw on P8. It should be efficient than loading vector from TOC. Compared to last version, the main change is to move the constant check from easy_altivec_constant to easy_altivec_constant and remove some unnecessary mode checks. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Thanks Gui Haochen ChangeLog 2023-05-04 Haochen Gui gcc/ PR target/104124 * config/rs6000/altivec.md (*altivec_vupkhs_direct): Rename to... (altivec_vupkhs_direct): ...this. * config/rs6000/constraints.md (wT constraint): New constant for a vector constraint that can be loaded with vspltisw and vupkhsw. * config/rs6000/predicates.md (vspltisw_vupkhsw_constant_split): New predicate for wT constraint. (easy_vector_constant): Call vspltisw_vupkhsw_constant_p to Check if a vector constant can be synthesized with a vspltisw and a vupkhsw. * config/rs6000/rs6000-protos.h (vspltisw_vupkhsw_constant_p): Declare. * config/rs6000/rs6000.cc (vspltisw_vupkhsw_constant_p): Call * (vspltisw_vupkhsw_constant_p): New function to return true if OP mode is V2DI and can be synthesized with vupkhsw and vspltisw. * config/rs6000/vsx.md (*vspltisw_v2di_split): New insn to load up constants with vspltisw and vupkhsw. gcc/testsuite/ PR target/104124 * gcc.target/powerpc/pr104124.c: New. patch.diff diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 49b0c964f4d..2c932854c33 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2542,7 +2542,7 @@ (define_insn "altivec_vupkhs" } [(set_attr "type" "vecperm")]) -(define_insn "*altivec_vupkhs_direct" +(define_insn "altivec_vupkhs_direct" [(set (match_operand:VP 0 "register_operand" "=v") (unspec:VP [(match_operand: 1 "register_operand" "v")] UNSPEC_VUNPACK_HI_SIGN_DIRECT))] diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index c4a6ccf4efb..e7f185660c0 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -144,6 +144,10 @@ (define_constraint "wS" "@internal Vector constant that can be loaded with XXSPLTIB & sign extension." (match_test "xxspltib_constant_split (op, mode)")) +(define_constraint "wT" + "@internal Vector constant that can be loaded with vspltisw & vupkhsw." + (match_test "vspltisw_vupkhsw_constant_split (op, mode)")) + ;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form. ;; Used by LXSD/STXSD/LXSSP/STXSSP. In contrast to "Y", the multiple-of-four ;; offset is enforced for 32-bit too. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 52c65534e51..ff0f625d508 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -694,6 +694,16 @@ (define_predicate "xxspltib_constant_split" return num_insns > 1; }) +;; Return true if the operand is a constant that can be loaded with a vspltisw +;; instruction and then a vupkhsw instruction. + +(define_predicate "vspltisw_vupkhsw_constant_split" + (match_code "const_vector") +{ + int value; + + return vspltisw_vupkhsw_constant_p (op, mode, &value); +}) ;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB ;; instruction. @@ -742,6 +752,11 @@ (define_predicate "easy_vector_constant" && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; + /* V2DI constant within RANGE (-16, 15) can be synthesized with a + vspltisw and a vupkhsw. */ + if (vspltisw_vupkhsw_constant_p (op, mode, &value)) + return true; + return easy_altivec_constant (op, mode); } diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 1a4fc1df668..ba39a73abf8 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -32,6 +32,7 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, extern int easy_altivec_constant (rtx, machine_mode); extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); +extern bool vspltisw_vupkhsw_constant_p (rtx, machine_mode, int *); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); extern bool macho_lo_sum_memory_operand (rtx, machine_mode); diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 3be5860dd9b..697b18e14f1 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -6638,6 +6638,36 @@ xxspltib_constant_p (rtx op, return true; } +/* Return true if OP mode is V2DI and can be synthesized with ISA 2.07 + instructions vupkhsw and vspltisw. + + Return the constant that is being split via CONSTANT_PTR. */ + +bool +vspltisw_vupkhsw_constant_p (rtx op, machine_mode mode, + int *constant_ptr = nullptr) +{ + HOST_WIDE_INT value; + rtx elt; + + if (!TARGET_P8_VECTOR) + return false; + + if (mode != V2DImode) + return false; + + if (!const_vec_duplicate_p (op, &elt)) + return false; + + value = INTVAL (elt); + if (value == 0 || value == 1 + || !EASY_VECTOR_15 (value)) + return false; + + *constant_ptr = (int) value; + return true; +} + const char * output_vec_const_move (rtx *operands) { diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7d845df5c2d..ba9b3037644 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1174,6 +1174,30 @@ (define_insn_and_split "*xxspltib__split" [(set_attr "type" "vecperm") (set_attr "length" "8")]) +(define_insn_and_split "*vspltisw_v2di_split" + [(set (match_operand:V2DI 0 "altivec_register_operand" "=v") + (match_operand:V2DI 1 "vspltisw_vupkhsw_constant_split" "wT"))] + "TARGET_P8_VECTOR" + "#" + "&& 1" + [(const_int 0)] +{ + int value; + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx tmp = can_create_pseudo_p () + ? gen_reg_rtx (V4SImode) + : gen_lowpart (V4SImode, op0); + + vspltisw_vupkhsw_constant_p (op1, V2DImode, &value); + emit_insn (gen_altivec_vspltisw (tmp, GEN_INT (value))); + emit_insn (gen_altivec_vupkhsw_direct (op0, tmp)); + + DONE; +} + [(set_attr "type" "vecperm") + (set_attr "length" "8")]) + ;; Prefer using vector registers over GPRs. Prefer using ISA 3.0's XXSPLTISB ;; or Altivec VSPLITW 0/-1 over XXLXOR/XXLORC to set a register to all 0's or diff --git a/gcc/testsuite/gcc.target/powerpc/pr104124.c b/gcc/testsuite/gcc.target/powerpc/pr104124.c new file mode 100644 index 00000000000..aec0f20edb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr104124.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-final { scan-assembler "vspltisw" } } */ +/* { dg-final { scan-assembler "vupkhsw" } } */ +/* { dg-final { scan-assembler-not "lvx" } } */ + +#include + +vector unsigned long long +foo () +{ + return vec_splats ((unsigned long long) 12); +}