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Signed-off-by: Bhupesh Sharma Reviewed-by: Konrad Dybcio --- Documentation/ABI/testing/sysfs-driver-eud | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-driver-eud b/Documentation/ABI/testing/sysfs-driver-eud index 83f3872182a4..2bab0db2d2f0 100644 --- a/Documentation/ABI/testing/sysfs-driver-eud +++ b/Documentation/ABI/testing/sysfs-driver-eud @@ -1,4 +1,4 @@ -What: /sys/bus/platform/drivers/eud/.../enable +What: /sys/bus/platform/drivers/qcom_eud/.../enable Date: February 2022 Contact: Souradeep Chowdhury Description: From patchwork Thu May 4 08:26:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 89993 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp145530vqo; Thu, 4 May 2023 01:31:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5gGtm8AErM5DeV2o0f6exfawu80TVPba6jslnjzpUOB5V0k/kq3kYaGSoFl6Ifu6W8w+ph X-Received: by 2002:a05:6a20:438a:b0:ef:95de:b877 with SMTP id i10-20020a056a20438a00b000ef95deb877mr1551196pzl.10.1683189096757; Thu, 04 May 2023 01:31:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683189096; cv=none; d=google.com; s=arc-20160816; b=UNoVP8h0j4Ob6cyDe4l2cJ1YYRZGxd99XLJPBFE6s+JNIzOZ/n1ujDmoFcIBV/9bvo TqT5tDMghUK9Zt/xmvS9adPoWD7XsEGHsoFPSQiPNa9EeBSlXAv3uAiUypJg7zRRkLuY ACFfhZFbRapO1Wa4Y3dulZ8xDkVW6VvYvWKjxiowIutlNMuulczq7URlmQsIuwlsZ75K 7WPNxa4OQhqyLxITxxJ6UibV4GRjQ15okJjVy2ksQH1AdJVzqGduEthg0PrLtZhBIfz5 pRT2s0EL9zQHt17wTLCF0OQCXWM6Z8ViP9MQ6gUDuc/RdBuiAAnHzGiIQYKzSiwGz8m0 gPMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tpKnP1YDIVbRZiADGr23D8oPufyg/cq5r9T3i6z6bvI=; b=COojgORsxOJJYvcd2R7AiqMWcVkS9Rh4JrJhfQPWLAiozk1SDCKfnwAsl7vza4cALi HC6gBJRzunxqCVLOhoogUiHMxKodNtlsJip5wDvOyIXNW1BEQp6IdFuRI82FlvGLw7KT 2KWVFqs9+NsQTNAWkSCUOGdiqJysN6AI4NidBY1sk1xHLsXZWMoBIZMg60Tq5HwtWW3P 2eFVDRFrPPTsFDrQDw08jZCW5UWCjvQvKS9v/1MUaFbP+/S97xN3vyslKAccVJr6QpT5 qMfodK8zPwY6cnAnu6zgQlUQg3u5hDu1NECbCcjqKG+56EtqsGBVjG7msE6gFGgsJeiv vW+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SqxCUtKD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' the eud module. So, update the dt-bindings to accommodate the third register property (TCSR Base) required by the driver on these SoCs. Also for these SoCs, introduce a new bool property 'qcom,secure-mode-enable', which indicates that the mode manager needs to be accessed only via the secure world. Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437..3b92cdf4e306 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,17 +18,33 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud reg: + minItems: 2 items: - description: EUD Base Register Region - description: EUD Mode Manager Register + - description: TCSR Base Register Region + + reg-names: + minItems: 2 + items: + - const: eud-base + - const: eud-mode-mgr + - const: tcsr-base interrupts: description: EUD interrupt maxItems: 1 + qcom,secure-mode-enable: + type: boolean + description: + Indicates that the mode manager needs to be accessed only via the secure + world (through 'scm' calls). + ports: $ref: /schemas/graph.yaml#/properties/ports description: From patchwork Thu May 4 08:26:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 89997 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp147933vqo; Thu, 4 May 2023 01:37:06 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5w4dsMD06tWAHOy4dU5ImbaNOPFEHY/mequFOPeCdDQZBP4bX7vOu78MIsR8uP+hwxZ4vU X-Received: by 2002:a05:6a20:a11c:b0:d9:dbb6:2e7a with SMTP id q28-20020a056a20a11c00b000d9dbb62e7amr1654604pzk.27.1683189426143; Thu, 04 May 2023 01:37:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683189426; cv=none; d=google.com; s=arc-20160816; b=mWnQc0g2d4Vxbm5HoX4CTHjmH2WTynXKoGUqUvXCamGxKmtRuu1UnsSyz4jngbbyJj 7TlhzjZvpUz0GwH6N27JwnlynaavwfZqxxjtYDML5V31SPxqkUO9AbeQog0Cmx1vfLvO SsH0g3mglEr9gH4SLrz3lTLSpLjuxBdjxEuX2bzWhpbF4IiHXeWRWnYgE3r5XQXnE7DQ nCOAM1JeY2psoRzXecEiy9JBgXlJsuiIVaVLg18/8MeHBKTv7eoohnk0BzsFHSIY3Hu0 uJ2XwZfgJ3192r5ppwK8mp+CZFCCKCe8rEJyETfis3h+yTtzjJ6QkfPs6o3PrBMidjZE 8QUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rC05tB6gG1w1yHT13tBk32ihblOOEZ5SfiKYI/IbjjQ=; b=Tf+IW02JGP/c4e0sMHiLRCOV6rruFfehyvbu+ATHELxJNxeTp6a+I3wZe+5Na4XXgs jnGy+ll6MMFaJsrDXNH3s9FnKViaQjOlVAF4bVgtcXQaALOxh7wo/vuStoZJj5ovjqyU 9e4I5ZfAVMPERBfQo8lP+L+ilvthCdKuscKWr3sQkI3BvRpoaZYmnu99gP7Rw8CgBuWs Ct7BmMNEzOLSwWZ3rGTvjsKEpoecE40tylC0Y94fpCqXL8HI61xV5FxYBgaNFfKzl9ca Z4NqTE4CTZplGFljpWxmp2ZJ1QOcGmiIKdIux0ww+dEEwT8NE4VYGUeLeNWiXxMbQezV ICyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IMfqygJF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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On some SoCs (like the SM6115 / SM4250 SoC), the mode manager needs to be accessed only via the secure world (through 'scm' calls). Also, the enable bit inside 'tcsr_check_reg' needs to be set first to set the eud in 'enable' mode on these SoCs. Since this difference comes from how the firmware is configured, so the driver now relies on the presence of an extra boolean DT property to identify if secure access is needed. Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/Kconfig | 1 + drivers/usb/misc/qcom_eud.c | 66 ++++++++++++++++++++++++++++++++++--- 2 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index 99b15b77dfd5..fe1b5fec1dfc 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -147,6 +147,7 @@ config USB_APPLEDISPLAY config USB_QCOM_EUD tristate "QCOM Embedded USB Debugger(EUD) Driver" depends on ARCH_QCOM || COMPILE_TEST + select QCOM_SCM select USB_ROLE_SWITCH help This module enables support for Qualcomm Technologies, Inc. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index b7f13df00764..b4736edcc64c 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -5,12 +5,14 @@ #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -30,15 +32,22 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) +struct eud_soc_cfg { + u32 tcsr_check_offset; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; + const struct eud_soc_cfg *eud_cfg; void __iomem *base; void __iomem *mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + bool secure_mode_enable; + phys_addr_t secure_mode_mgr; }; static int enable_eud(struct eud_chip *priv) @@ -46,7 +55,11 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, BIT(0)); + else + writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +67,11 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, 0); + else + writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); } static ssize_t enable_show(struct device *dev, @@ -178,12 +195,15 @@ static void eud_role_switch_release(void *data) static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; + phys_addr_t tcsr_base, tcsr_check; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; + chip->dev = &pdev->dev; chip->role_sw = usb_role_switch_get(&pdev->dev); @@ -200,9 +220,40 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(chip->mode_mgr)) - return PTR_ERR(chip->mode_mgr); + chip->secure_mode_enable = of_property_read_bool(chip->dev->of_node, + "qcom,secure-mode-enable"); + /* + * EUD block on a few Qualcomm SoCs need secure register access. + * Check for the same. + */ + if (chip->secure_mode_enable) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get secure_mode_mgr reg base\n"); + + chip->secure_mode_mgr = res->start; + } else { + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->mode_mgr)) + return PTR_ERR(chip->mode_mgr); + } + + /* Check for any SoC specific config data */ + chip->eud_cfg = of_device_get_match_data(&pdev->dev); + if (chip->eud_cfg) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get tcsr reg base\n"); + + tcsr_base = res->start; + tcsr_check = tcsr_base + chip->eud_cfg->tcsr_check_offset; + + ret = qcom_scm_io_writel(tcsr_check, BIT(0)); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n"); + } chip->irq = platform_get_irq(pdev, 0); ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, @@ -230,8 +281,13 @@ static int eud_remove(struct platform_device *pdev) return 0; } +static const struct eud_soc_cfg sm6115_eud_cfg = { + .tcsr_check_offset = 0x25018, +}; + static const struct of_device_id eud_dt_match[] = { { .compatible = "qcom,sc7280-eud" }, + { .compatible = "qcom,sm6115-eud", .data = &sm6115_eud_cfg }, { } }; MODULE_DEVICE_TABLE(of, eud_dt_match); From patchwork Thu May 4 08:26:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 89999 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp154538vqo; Thu, 4 May 2023 01:53:06 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6143xXmXRf+cEyQYEINv+0Q0THp2OyLNBZATOfhIqMszlB/v6BLkAMsBgUfvRPaaDeqK8X X-Received: by 2002:a17:90a:d202:b0:24d:fb8c:5ab3 with SMTP id o2-20020a17090ad20200b0024dfb8c5ab3mr1385890pju.24.1683190385777; Thu, 04 May 2023 01:53:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683190385; cv=none; d=google.com; s=arc-20160816; b=FxJgc8oHIX6qRK3VOG5V1NNLrttWYy60pWl1FEDgCI3qhvwW5x6EXAJPod51nKeHLC 9Y5iLztbrnKf8KgatwrCAWPHHxdL11t80aHSuki5mlcvv0HaExi6x+0Pu0KOqgDeW7rS 3rtyaC4nlJfAgF9k3ICsrVSD47sZOGpHzYqgA5iySKtRrC9BGLMnvKbQBYOmEXUBv4id lHsR9kljWD1VjHkLANIQSMXX+k/gJS2FdT3L+PSXciaUtL5Sj56qv0hfqzFhRve7m/X/ hamjiFyRA56vUdgNRyQXCYe9EKcHHdo55wHIZc9KHG9z0Qt8kEPytLFfe99GY6iqBWlB mXZg== ARC-Message-Signature: i=1; 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The node contains EUD base register region, EUD mode manager register region and TCSR Base register region along with the interrupt entry. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. To enable the role switch, we need to set dr_mode = "otg" property for 'usb_dwc3' sub-node in the board dts file. Also the EUD device can be enabled on a board once linux is boot'ed by setting: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/../enable Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 48 ++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index f67863561f3f..6865342fc42f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -180,6 +180,18 @@ core3 { }; }; + eud_typec: connector { + compatible = "usb-c-connector"; + + ports { + port@0 { + con_eud: endpoint { + remote-endpoint = <&eud_con>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-sm6115", "qcom,scm"; @@ -647,6 +659,35 @@ gcc: clock-controller@1400000 { #power-domain-cells = <1>; }; + eud: eud@1610000 { + compatible = "qcom,sm6115-eud", "qcom,eud"; + reg = <0x0 0x01610000 0x0 0x2000>, + <0x0 0x01612000 0x0 0x1000>, + <0x0 0x003c0000 0x0 0x40000>; + interrupts = ; + qcom,secure-mode-enable; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; + }; + + port@1 { + reg = <1>; + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; + }; + }; + }; + usb_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; reg = <0x0 0x01613000 0x0 0x180>; @@ -1144,6 +1185,13 @@ usb_dwc3: usb@4e00000 { snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + usb-role-switch; + + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; + }; + }; }; }; From patchwork Thu May 4 08:26:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 89998 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp151008vqo; Thu, 4 May 2023 01:44:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4Qo9jwjXRVtRk9PjTx0Vqe3vtui0Ncgu/jwOTaIpaMlqqvRTmtLmwNqT/TvIvgFibaY/uH X-Received: by 2002:a17:903:41c6:b0:1aa:e739:4097 with SMTP id u6-20020a17090341c600b001aae7394097mr3420900ple.5.1683189851843; Thu, 04 May 2023 01:44:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683189851; cv=none; d=google.com; s=arc-20160816; b=dWrGF1LULErPOX8QJFTqrzvMUz/H2PrmdvzQLZqHKG15ZppC0M8mpeJDapNcbTCLLq mPC/a8POydcpqDq4eNQZjd6B3az0whHdgPJqMbRb8MZHANFjcZs83WCbbyrBB2k7xrG1 9pFdqgG5cOJwOz8IsiMDuMN5V+ZV1W4N4/0FPhpwMnWMalfD6MfvGkY47COPqd/uaqGJ j1zziP4j2xjOMaUAfNQ3g3GcEiakvx0lwG4YR73IVu5/a5AbIosnPDwdxfZk0o4N5DL1 3XFT2qrb2yIpMPIlFQJZ0QO6LG5AMR+fCdOHuxO/aMWkH+NP6hkpI+dSmopN7APkq4OB QfJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fz6g2/625qlFmhiR93VnIJ+EVOsf12tbuuuDirZwZ9U=; b=bBC0j1F6rheR2+x3jdDyaMPBHNjN0dJsmrbHiyopzcnwlxIoQR2QcZ7eynptXdofLy UERQby3BxMN6Rvp/xmR504NB+yricL7ReG0EA0uzvOZjSdiK0Ekb3Ju9ArXUiDo4852x V5CoBklulmR2wKqLDZ0CqIuHrERVB1ROP3U8ct5ws2ih+lPt30DHQLL81R+p6j0Vn/VL WGXIlKhsSYKVryWK117TY9HDRxOZ703B4ev4ogRPXiBA4GHp/y4j+kRnCg86dUsneZWp Jt16Gsylc5tFadGbC6CffwONzlZIgmDIYcXJ8YcW8Fe1OJpIomYI6iuDkg2yaSpBVeg1 whgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="uh/cVkAv"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Now, the EUD debug peripheral can be enabled by executing: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/1610000.eud/enable Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 27 +++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 1a0776a0cfd0..0ce72f1ebc10 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -30,6 +30,10 @@ vph_pwr: vph-pwr-regulator { }; }; +&eud { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -253,7 +257,28 @@ &usb { &usb_dwc3 { maximum-speed = "super-speed"; - dr_mode = "peripheral"; + + /* + * There is only one USB DWC3 controller on QRB4210 board and it is connected + * via a DIP Switch: + * - to either an USB - C type connector or an USB - A type connector + * (via a GL3590-S hub), and + * - to either an USB - A type connector (via a GL3590-S hub) or a connector + * for further connection with a mezzanine board. + * + * All of the above hardware muxes would allow us to hook things up in + * different ways to some potential benefit for static configurations (for e.g. + * on one hand we can have two USB - A type connectors and a USB - Ethernet + * connection available and on the other we can use the USB - C type in + * peripheral mode). + * + * Note that since the USB - C type can be used only in peripehral mode, + * so hardcoding the mode to 'peripheral' here makes sense. + * + * However since we want to use the EUD debug device, we set the mode as + * 'otg' here. + */ + dr_mode = "otg"; }; &usb_hsphy {