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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id sz11-20020a1709078b0b00b009604c1d64c1si12471977ejc.163.2023.05.03.17.08.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 17:08:11 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=x7H+pjiV; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 19D223857006 for ; Thu, 4 May 2023 00:08:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 19D223857006 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683158890; bh=pUcSqWM7uDCuU9Rv157NkLCVksRJbgK3pQ82Mfd0TkU=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=x7H+pjiVP4UajDvwLWV3saZSOVziKoMjbf609V32AXYcnFEDJvrelFPoP5AwGJA7/ Yd/ma8YR8d444DthkCp3fk7FJ2IAyLW1gqssKLOfZhn3u6jehIq2Ywkb4uju0+rEOC xS7wK2PrbJFKSYVfKwcZi8Qz7qrmsajsAfwMigv8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by sourceware.org (Postfix) with ESMTPS id 19DBB3858D28 for ; Thu, 4 May 2023 00:07:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 19DBB3858D28 To: CC: Subject: [committed] CRIS-LRA: Fix uses of reload_in_progress MIME-Version: 1.0 Message-ID: <20230504000721.AA69920425@pchp3.se.axis.com> Date: Thu, 4 May 2023 02:07:21 +0200 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hans-Peter Nilsson via Gcc-patches From: Hans-Peter Nilsson Reply-To: Hans-Peter Nilsson Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764920017982984162?= X-GMAIL-MSGID: =?utf-8?q?1764920017982984162?= On previous occasions when a general LRA transition has been discussed, IIRC, the argument was used, that everything is ready for targets and their maintainers to make the transition. As I pointed out then (though more than a year ago last time, people forget) that's still not true: LRA documentation needs improvement to know what to do, and having to sneak peaks at other targets is not a valid level of documentation. Here's an example and its fall-out: what to do with lra_in_progress vs. reload_in_progress. I "guess" lra_in_progress is supposed to be used like reload_in_progress. The consequences of missing it is quite mild though: LRA takes most of its data from state collected during IRA, and lra_in_progress has much less impact there, than reload_in_progress has for reload. Anyway, many supposedly-transformed targets (without TARGET_LRA_P) still mention reload_in_progress, like aarch64, arm, csky, epiphany, iq2000, m32r, microblaze, mmix (I'll deal with this one), moxie, nds32, stormy16, v850 (with reservations for grep-errors; the list may be erroneous or incomplete). While this may have been of no measureable consequence to CRIS, it *might* be a build-breaker for other targets, transformed or about-to-be transformed, thus heads-up to eager converters. ;-) (JFTR: in comparison, reload_completed is used for both LRA and reload; there's no "lra_completed".) Committed. -- >8 -- This shows no difference neither in arith-rand-ll nor coremark numbers. Comparing libgcc and newlib libc before/after, the only difference can be seen in a few functions where it's mostly neutral (newlib's _svfprintf_r et al) and one function (__gdtoa), which improves ever so slightly (four bytes less; one load less, but one instruction reading from memory instead of a register). * config/cris/cris.cc (cris_side_effect_mode_ok): Use lra_in_progress, not reload_in_progress. * config/cris/cris.md ("movdi", "*addi_reload"): Ditto. * config/cris/constraints.md ("Q"): Ditto. --- gcc/config/cris/constraints.md | 18 +++++++++--------- gcc/config/cris/cris.cc | 18 +++++++++--------- gcc/config/cris/cris.md | 4 ++-- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/gcc/config/cris/constraints.md b/gcc/config/cris/constraints.md index fa9aa19d13e3..3df8cc27d8d4 100644 --- a/gcc/config/cris/constraints.md +++ b/gcc/config/cris/constraints.md @@ -96,7 +96,7 @@ (define_constraint "G" (define_memory_constraint "Q" "@internal" (and (match_code "mem") - (match_test "cris_base_p (XEXP (op, 0), reload_in_progress + (match_test "cris_base_p (XEXP (op, 0), lra_in_progress || reload_completed)"))) ;; Extra constraints. @@ -107,7 +107,7 @@ (define_memory_constraint "T" ;; Double indirect: [[reg]] or [[reg+]]? (ior (and (match_code "mem" "0") (match_test "cris_base_or_autoincr_p (XEXP (XEXP (op, 0), 0), - reload_in_progress + lra_in_progress || reload_completed)")) ;; Just an explicit indirect reference: [const]? (match_test "CONSTANT_P (XEXP (op, 0))") @@ -115,29 +115,29 @@ (define_memory_constraint "T" (and (match_code "plus" "0") ;; A BDAP constant: [reg+(8|16|32)bit offset]? (ior (and (match_test "cris_base_p (XEXP (XEXP (op, 0), 0), - reload_in_progress + lra_in_progress || reload_completed)") (match_test "CONSTANT_P (XEXP (XEXP (op, 0), 1))")) ;; A BDAP register: [reg+[reg(+)].S]? (and (match_test "cris_base_p (XEXP (XEXP (op, 0), 0), - reload_in_progress + lra_in_progress || reload_completed)") (match_test "cris_bdap_index_p (XEXP (XEXP (op, 0), 1), - reload_in_progress + lra_in_progress || reload_completed)")) ;; Same, but with swapped arguments (no canonical ;; ordering between e.g. REG and MEM as of LAST_UPDATED ;; "Thu May 12 03:59:11 UTC 2005"). (and (match_test "cris_base_p (XEXP (XEXP (op, 0), 1), - reload_in_progress + lra_in_progress || reload_completed)") (match_test "cris_bdap_index_p (XEXP (XEXP (op, 0), 0), - reload_in_progress + lra_in_progress || reload_completed)")) ;; A BIAP: [reg+reg.S] (MULT comes first). (and (match_test "cris_base_p (XEXP (XEXP (op, 0), 1), - reload_in_progress + lra_in_progress || reload_completed)") (match_test "cris_biap_index_p (XEXP (XEXP (op, 0), 0), - reload_in_progress + lra_in_progress || reload_completed)"))))))) diff --git a/gcc/config/cris/cris.cc b/gcc/config/cris/cris.cc index 7ce1b754e76e..3013e01f22ac 100644 --- a/gcc/config/cris/cris.cc +++ b/gcc/config/cris/cris.cc @@ -2134,12 +2134,12 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, /* The operands may be swapped. Canonicalize them in reg_rtx and val_rtx, where reg_rtx always is a reg (for this constraint to match). */ - if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) + if (! cris_base_p (reg_rtx, lra_in_progress || reload_completed)) reg_rtx = val_rtx, val_rtx = ops[rreg]; /* Don't forget to check that reg_rtx really is a reg. If it isn't, we have no business. */ - if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) + if (! cris_base_p (reg_rtx, lra_in_progress || reload_completed)) return 0; /* Don't do this when -mno-split. */ @@ -2164,9 +2164,9 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, /* Check if the lvalue register is the same as the "other operand". If so, the result is undefined and we shouldn't do this. FIXME: Check again. */ - if ((cris_base_p (ops[lreg], reload_in_progress || reload_completed) + if ((cris_base_p (ops[lreg], lra_in_progress || reload_completed) && cris_base_p (ops[other_op], - reload_in_progress || reload_completed) + lra_in_progress || reload_completed) && REGNO (ops[lreg]) == REGNO (ops[other_op])) || rtx_equal_p (ops[other_op], ops[lreg])) return 0; @@ -2179,7 +2179,7 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, return 0; if (code == PLUS - && ! cris_base_p (val_rtx, reload_in_progress || reload_completed)) + && ! cris_base_p (val_rtx, lra_in_progress || reload_completed)) { /* Do not allow rx = rx + n if a normal add or sub with same size @@ -2195,13 +2195,13 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, if (MEM_P (val_rtx) && cris_base_or_autoincr_p (XEXP (val_rtx, 0), - reload_in_progress || reload_completed)) + lra_in_progress || reload_completed)) return 1; if (GET_CODE (val_rtx) == SIGN_EXTEND && MEM_P (XEXP (val_rtx, 0)) && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx, 0), 0), - reload_in_progress || reload_completed)) + lra_in_progress || reload_completed)) return 1; /* If we got here, it's not a valid addressing mode. */ @@ -2210,7 +2210,7 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, else if (code == MULT || (code == PLUS && cris_base_p (val_rtx, - reload_in_progress || reload_completed))) + lra_in_progress || reload_completed))) { /* Do not allow rx = rx + ry.S, since it doesn't give better code. */ if (rtx_equal_p (ops[lreg], reg_rtx) @@ -2222,7 +2222,7 @@ cris_side_effect_mode_ok (enum rtx_code code, rtx *ops, return 0; /* Only allow r + ... */ - if (! cris_base_p (reg_rtx, reload_in_progress || reload_completed)) + if (! cris_base_p (reg_rtx, lra_in_progress || reload_completed)) return 0; /* If we got here, all seems ok. diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index 366b4bc304bf..3796a78480cb 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -528,7 +528,7 @@ (define_expand "movdi" emitted) is the final value. */ if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) && ! reload_completed - && ! reload_in_progress) + && ! lra_in_progress) { rtx insns; rtx op0 = operands[0]; @@ -1328,7 +1328,7 @@ (define_insn_and_split "*addi_reload" && operands[1] != frame_pointer_rtx && CONST_INT_P (operands[3]) && (INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4) - && (reload_in_progress || reload_completed)" + && (lra_in_progress || reload_completed)" "#" "&& 1" [(set (match_dup 0)