From patchwork Wed May 3 16:33:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 89785 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1478651vqo; Wed, 3 May 2023 10:03:57 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6LbC75KQ8wDIeWz/BnG1YE8rr6lQSuYJQN/kvNUWvXZFUG8PWiPdS73VvNwXzAHdxw6P0y X-Received: by 2002:a05:6a00:1955:b0:63b:6911:8928 with SMTP id s21-20020a056a00195500b0063b69118928mr29972466pfk.3.1683133436925; Wed, 03 May 2023 10:03:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683133436; cv=none; d=google.com; s=arc-20160816; b=k+O84/wYtYwF57eH+irovkEGNaISTi1PVMPWiYsKWE7rC2errKlE5V0Tp0T2WO+agZ sI7U7sNmsfSCYQW6FbV1n7TJk0fdJzrG7Rm6GmMOBIEMjnjnv4I+jrVbYKCEiMoU5WQs qd7oINsLAQXtsJ1fCL0a5PQ8aUY5hcSJI3PQ1H/XNd7/3PFYCW9olI+Uhu++zFtnA814 Ae94R/xsJlzjNyrOMffG4qBZvVUprbjmm2jebwJtY+BRZNaMF6NwDmY35FDTUAPW9F1u Q5oe5WT+PpcbbKdLQ9vBh/jUroVWy8FIVvmq1vx+1+A8M+51ibwPPVUaZrZ03+/O3hQq lU4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XpB9Qsa5ysbMqR5vQpemAUlG5S8C8bacv3P8I3Dbn2Q=; b=QgVy31nB8Lt4Whg5R4JHKwkHa1D5+n5di79a+qPa9va0TLo6QmOW2ZToFHaaIG9+z4 Y+L6bDEHL8iO1TykoHfOBXBwbXVM/OP8dUvTuty+5JIUPLSa5oB9oSniwVDkQ9zmIiJA y34Uia6/kLtNihe4dm4HkKY7N0lItYHtyvks6g/C2YHrb/pGznhUEQV6sneHuZQ65Xje KnmdsZEvuApnWZ2be47HbN5rI05Yq4ZhhbcY9i+ChL4dnDimKbuDep06SVGfVIfx2MZX q8+fL/ZDmo1YN1dDe63oaJsblTzGY2PuhZXkWUM9nIt5jG5IzSQvPoQz5jHx7c2LUEZF Evtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=CgseNmfW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a138-20020a621a90000000b005e06c0a9852si33336590pfa.179.2023.05.03.10.03.41; Wed, 03 May 2023 10:03:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=CgseNmfW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229670AbjECQdo (ORCPT + 99 others); Wed, 3 May 2023 12:33:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229502AbjECQdm (ORCPT ); Wed, 3 May 2023 12:33:42 -0400 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 673B94EF9 for ; Wed, 3 May 2023 09:33:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6AFF5BFBA7; Wed, 3 May 2023 18:33:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1683131616; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=XpB9Qsa5ysbMqR5vQpemAUlG5S8C8bacv3P8I3Dbn2Q=; b=CgseNmfWzz5i1BKVwb2ndpUP21VlGSBMvwIHZ0pXLuLpGSUnuwT7dFHPpdiYHqYAE3ll43 b6QriMM6PFrKmemHLibj4YeGxf1wy7jRak9nxGAwR7JovCzdwsSwr5YgsfmI5j09wF5wj6 R3Epht6IA6FwRj2reSNkCPc3lTn2cAL2cb9BlQ+wLNbbNJBeYu2Fb/kZ+33Sqw3fHXlUmP pdAsqqxp96Yqu5LYpk1mNRYarLq9J595VY6RZyTzK9sgtf8UTXwPLo4VqDmb4RW3NbG9JO ICxvQIsmTsocEcvsnd3doTslg6p7SXolxWDoMemNzV3aZH43zbt49ktPNnQsaw== From: Frieder Schrempf To: Andrzej Hajda , Daniel Vetter , David Airlie , dri-devel@lists.freedesktop.org, Inki Dae , Jagan Teki , linux-kernel@vger.kernel.org, Marek Szyprowski , Neil Armstrong , Robert Foss Cc: Frieder Schrempf , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Marek Vasut Subject: [PATCH v2 1/2] drm: bridge: samsung-dsim: Fix i.MX8M enable flow to meet spec Date: Wed, 3 May 2023 18:33:06 +0200 Message-Id: <20230503163313.2640898-2-frieder@fris.de> In-Reply-To: <20230503163313.2640898-1-frieder@fris.de> References: <20230503163313.2640898-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764893326445813751?= X-GMAIL-MSGID: =?utf-8?q?1764893326445813751?= From: Frieder Schrempf According to the documentation [1] the proper enable flow is: 1. Enable DSI link and keep data lanes in LP-11 (stop state) 2. Disable stop state to bring data lanes into HS mode Currently we do this all at once within enable(), which doesn't allow to meet the requirements of some downstream bridges. To fix this we now enable the DSI in pre_enable() and force it into stop state using the FORCE_STOP_STATE bit in the ESCMODE register until enable() is called where we reset the bit. We currently do this only for i.MX8M as Exynos uses a different init flow where samsung_dsim_init() is called from samsung_dsim_host_transfer(). [1] https://docs.kernel.org/gpu/drm-kms-helpers.html#mipi-dsi-bridge-operation Signed-off-by: Frieder Schrempf Tested-by: Alexander Stein #TQMa8MxML/MBa8Mx Reviewed-by: Neil Armstrong --- Changes for v2: * Drop RFC --- drivers/gpu/drm/bridge/samsung-dsim.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index e0a402a85787..9775779721d9 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -859,6 +859,10 @@ static int samsung_dsim_init_link(struct samsung_dsim *dsi) reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); reg &= ~DSIM_STOP_STATE_CNT_MASK; reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); + + if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) + reg |= DSIM_FORCE_STOP_STATE; + samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg); reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); @@ -1340,6 +1344,9 @@ static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, ret = samsung_dsim_init(dsi); if (ret) return; + + samsung_dsim_set_display_mode(dsi); + samsung_dsim_set_display_enable(dsi, true); } } @@ -1347,9 +1354,16 @@ static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { struct samsung_dsim *dsi = bridge_to_dsi(bridge); + u32 reg; - samsung_dsim_set_display_mode(dsi); - samsung_dsim_set_display_enable(dsi, true); + if (samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { + samsung_dsim_set_display_mode(dsi); + samsung_dsim_set_display_enable(dsi, true); + } else { + reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); + reg &= ~DSIM_FORCE_STOP_STATE; + samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg); + } dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; } @@ -1358,10 +1372,17 @@ static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { struct samsung_dsim *dsi = bridge_to_dsi(bridge); + u32 reg; if (!(dsi->state & DSIM_STATE_ENABLED)) return; + if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { + reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); + reg |= DSIM_FORCE_STOP_STATE; + samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg); + } + dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; } From patchwork Wed May 3 16:33:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 89786 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1479439vqo; Wed, 3 May 2023 10:04:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4gxRBKm5OKfj1GCBLburoWmLLtTGd+IeoS5qURmZN0c2bRiVeCN0dzDkf8E2wtMry2kx67 X-Received: by 2002:a17:902:f693:b0:1a9:6dfb:4b09 with SMTP id l19-20020a170902f69300b001a96dfb4b09mr598300plg.67.1683133493604; Wed, 03 May 2023 10:04:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683133493; cv=none; d=google.com; s=arc-20160816; b=odO0dJU380N8a+XbMfd/9afOLrUDzR0xalnnKBKFcJ9TK75Q4aO7TsdpTcIKgn1h5/ 45o00aVa/ImrOduFvzNYZ/znBu+UYxod72C2GHFtndPpRabT2qklMuqyeR5dsJuayuZv RDC1Hdu8myJA6QSsyvzWKsxmQbbN4Ipy+jZbxKG94wOmZ+WfpwbClc+NUzCNdsmqiRaE iGIgC/P/kU1ScpKEpEWo2pSJFS/hv7qfwMZG5/IFqLP5gP6m14lpjZIFD2Zkrd0PjCBU 3SnFOJ0sFEkOf1x12ipOZo2bmhaICYZJT6u0XO1DHMRPnPEA6EV8BIvY/3YeQ+q56A9W 1Oow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ECOLwka8y269nmiwqwK0dagIvHnwYeTwEk+YJlIW4mI=; b=lBf7JQGzon39LSboXfowbkWOCCaui2BPkQaYRXSRNry2gvliUT8j5JDCHr9rsuki2G m2a6hQfYwkGacePN6BAcYxQoB8x5T8VlNV77gatbf+3wPfWtlCBtRHVPUAw+ke4VbOVd JmAqT8GEZeI50Qb2v++KW11FQP7yb2ttAaoCcGfu1vAEJMBHM6P9OySkkLvO1HrecXIx sUvAZSBz1PuKlvd9Jtcgjmy1Ki7+QKtcYIreFy4Ob+tqVNPchn51TzTc6j9WywaCzacy lMBgE0S57CtpWpeXzvJNfEwPsgHjoYd9XfxkgQ7doWSMONoJf6Yj7+nijIV1nRVMfs9f GhQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=kAGsKEdU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d2-20020a170902cec200b001a6e8791efbsi4056849plg.465.2023.05.03.10.04.40; Wed, 03 May 2023 10:04:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=kAGsKEdU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229696AbjECQdq (ORCPT + 99 others); Wed, 3 May 2023 12:33:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229524AbjECQdo (ORCPT ); Wed, 3 May 2023 12:33:44 -0400 Received: from mail.fris.de (mail.fris.de [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C07765257 for ; Wed, 3 May 2023 09:33:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DF9B8C03A6; Wed, 3 May 2023 18:33:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1683131618; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ECOLwka8y269nmiwqwK0dagIvHnwYeTwEk+YJlIW4mI=; b=kAGsKEdUacte067gXcSVW07KKf/jmOPySsIdr/tR/yxGeu/lblDnvSU647fz1Vv03brR1j +nzpbVjJ7hcP7ABY8kMzEO0OPr0/++hdNkmg2E21Yoh4szBEem5NF+bXIG0/6Pw81elidV gVBA/2Hfe3/6tdq7Kuv7dsj7CIXy25idr651KsATwmgxG+iMZRzmYTUFQDfDgibfHBAEjx k5TZYJZ88c24x1hpjkcfWTz/DkQgWcaKdoJXALtbNd/1Q2NwjDmYvnaO9+R2TY4qEhsb3O of4+jC3RX4kvwifSaEHPniN4RHI9Mhuk1vt+/RljeKAA2tYgqYYlay2VnQjugQ== From: Frieder Schrempf To: Andrzej Hajda , Daniel Vetter , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Neil Armstrong , Robert Foss Cc: Frieder Schrempf , Alexander Stein , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Marek Vasut , Sam Ravnborg , =?utf-8?q?Uwe?= =?utf-8?q?_Kleine-K=C3=B6nig?= , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v2 2/2] drm/bridge: ti-sn65dsi83: Fix enable/disable flow to meet spec Date: Wed, 3 May 2023 18:33:07 +0200 Message-Id: <20230503163313.2640898-3-frieder@fris.de> In-Reply-To: <20230503163313.2640898-1-frieder@fris.de> References: <20230503163313.2640898-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764893385878862601?= X-GMAIL-MSGID: =?utf-8?q?1764893385878862601?= From: Frieder Schrempf The datasheet describes the following initialization flow including minimum delay times between each step: 1. DSI data lanes need to be in LP-11 and the clock lane in HS mode 2. toggle EN signal 3. initialize registers 4. enable PLL 5. soft reset 6. enable DSI stream 7. check error status register To meet this requirement we need to make sure the host bridge's pre_enable() is called first by using the pre_enable_prev_first flag. Furthermore we need to split enable() into pre_enable() which covers steps 2-5 from above and enable() which covers step 7 and is called after the host bridge's enable(). Signed-off-by: Frieder Schrempf Tested-by: Alexander Stein #TQMa8MxML/MBa8Mx Reviewed-by: Neil Armstrong --- Changes for v2: * Drop RFC --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c index 75286c9afbb9..a82f10b8109f 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -321,8 +321,8 @@ static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) return dsi_div - 1; } -static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, - struct drm_bridge_state *old_bridge_state) +static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) { struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); struct drm_atomic_state *state = old_bridge_state->base.state; @@ -484,11 +484,22 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, /* Trigger reset after CSR register update. */ regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); + /* Wait for 10ms after soft reset as specified in datasheet */ + usleep_range(10000, 12000); +} + +static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); + unsigned int pval; + /* Clear all errors that got asserted during initialization. */ regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); regmap_write(ctx->regmap, REG_IRQ_STAT, pval); - usleep_range(10000, 12000); + /* Wait for 1ms and check for errors in status register */ + usleep_range(1000, 1100); regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); if (pval) dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval); @@ -555,6 +566,7 @@ static const struct drm_bridge_funcs sn65dsi83_funcs = { .attach = sn65dsi83_attach, .detach = sn65dsi83_detach, .atomic_enable = sn65dsi83_atomic_enable, + .atomic_pre_enable = sn65dsi83_atomic_pre_enable, .atomic_disable = sn65dsi83_atomic_disable, .mode_valid = sn65dsi83_mode_valid, @@ -697,6 +709,7 @@ static int sn65dsi83_probe(struct i2c_client *client) ctx->bridge.funcs = &sn65dsi83_funcs; ctx->bridge.of_node = dev->of_node; + ctx->bridge.pre_enable_prev_first = true; drm_bridge_add(&ctx->bridge); ret = sn65dsi83_host_attach(ctx);