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Signed-off-by: Wayne Chang --- .../bindings/usb/nvidia,tegra-xudc.yaml | 24 ++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index fd6e7c81426e..517fb692f199 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -22,6 +22,7 @@ properties: - nvidia,tegra210-xudc # For Tegra210 - nvidia,tegra186-xudc # For Tegra186 - nvidia,tegra194-xudc # For Tegra194 + - nvidia,tegra234-xudc # For Tegra234 reg: minItems: 2 @@ -90,21 +91,27 @@ properties: phys: minItems: 1 + maxItems: 8 description: Must contain an entry for each entry in phy-names. See ../phy/phy-bindings.txt for details. phy-names: minItems: 1 + maxItems: 8 items: - - const: usb2-0 - - const: usb2-1 - - const: usb2-2 - - const: usb2-3 - - const: usb3-0 - - const: usb3-1 - - const: usb3-2 - - const: usb3-3 + anyOf: + - const: usb2-0 + - const: usb2-1 + - const: usb2-2 + - const: usb2-3 + - const: usb3-0 + - const: usb3-1 + - const: usb3-2 + - const: usb3-3 + + dma-coherent: + type: boolean avddio-usb-supply: description: PCIe/USB3 analog logic power supply. Must supply 1.05 V. @@ -153,6 +160,7 @@ allOf: enum: - nvidia,tegra186-xudc - nvidia,tegra194-xudc + - nvidia,tegra234-xudc then: properties: reg: From patchwork Mon Oct 24 07:41:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 8188 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp307218wru; Mon, 24 Oct 2022 00:44:15 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7dnDrBcKf6ZgZkKvbELK0dFkAT57XhmKKkH0pUdw78QJoK6qX+qqhUfDgBDjoa81YSE/TK X-Received: by 2002:a17:902:ef47:b0:179:d18e:4262 with SMTP id e7-20020a170902ef4700b00179d18e4262mr31613141plx.22.1666597443807; Mon, 24 Oct 2022 00:44:03 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666597443; cv=pass; d=google.com; s=arc-20160816; b=py+uhbY2Jq9LGU+bFmaJA50tPq0wNlHy8EjKjcw0OoX4C1XcIWaN8fLpfnWql5UakT SzljH8ZTYAvt6KC8locvkES5wt6J4q03hWBsaJ08fd0gEqJXUWKzUgj3gfDZjq3O/eq1 88WIU9r47oxyFeiD4XASwE4kkvBIbIW4MYmIKaTNconomoG9nE9nz7VIDESTsCoCpCsD 4NipJXKMilA/d+6RXC18eIeBR9vPVx5JqbrNtOfPWOdH5iNzePd4gQwDbKuggWg+4WvN blXjlhz+T18n4pPDEDcUtp8BwQdIXfUAriIcRSaPzfHS87X1A9PLOl+Uo/O7ZWDGumQ0 2xZg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=S5qquIuupNl7ZliE5kSBRHSY//1lm/47aCgcaZGAkzo=; b=z0panlelBkhr8btK2yNvJ8NMk7oPGbjKK1yjZIGndWYaUbldzz0S/TbdQJFARQDHyw U6575tHJ73W5hpby0n1QSxSg+/fTgSRoIkTSglWNae1cwzmTebXBTCDcbP4cskVZ7RBS JhhBZx6XMtAvB5p7L+Bmp0HAH74p1Og++z1kYTH+j1cOKMjAM3kNPeqSoSngA6oEFxgd tEvHtMk1RWYZdwf0DXDEqBT073YYlwK2YcPlAZDNWSJIBrafEJUpKkel1m9Lcjv0Ky6s v96Qta4BMTBur+kZi4blUmIUgsaDkiSB6ThhNhtW1z+0vjNBYqR+MZPtGd0s/6z7cz8t W2rQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="ibKie/gu"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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This controller supports the USB 3.1 specification. Signed-off-by: Wayne Chang --- .../bindings/usb/nvidia,tegra-xhci.yaml | 213 ++++++++++++++++++ 1 file changed, 213 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml new file mode 100644 index 000000000000..d261a419a04f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/nvidia,tegra-xhci.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra XUSB host controller + +description: + The Tegra XHCI controller supports both USB 2.0 HighSpeed/FullSpeed and + USB 3.1 SuperSpeed protocols. + +maintainers: + - Wayne Chang + +properties: + compatible: + items: + - enum: + - nvidia,tegra194-xusb # For Tegra194 + - nvidia,tegra234-xusb # For Tegra234 + + reg: + minItems: 2 + items: + - description: XUSB host controller registers + - description: XUSB host PCI Config registers + - description: XUSB host bar2 registers + + reg-names: + minItems: 2 + items: + - const: hcd + - const: fpci + - const: bar2 + + interrupts: + items: + - description: Must contain the XUSB host interrupt. + - description: Must contain the XUSB mbox interrupt. + + clocks: + items: + - description: Clock to enable core XUSB host clock. + - description: Clock to enable XUSB falcon clock. + - description: Clock to enable XUSB super speed clock. + - description: Clock to enable XUSB super speed dev clock. + - description: Clock to enable XUSB high speed dev clock. + - description: Clock to enable XUSB full speed dev clock. + - description: Clock to enable XUSB UTMI PLL clock. + - description: Clock to enable core XUSB dev clock. + - description: Clock to enable XUSB PLLE clock. + + clock-names: + items: + - const: xusb_host + - const: xusb_falcon_src + - const: xusb_ss + - const: xusb_ss_src + - const: xusb_hs_src + - const: xusb_fs_src + - const: pll_u_480m + - const: clk_m + - const: pll_e + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + power-domains: + items: + - description: XUSBC(host) power-domain + - description: XUSBA(superspeed) power-domain + + power-domain-names: + items: + - const: xusb_host + - const: xusb_ss + + nvidia,xusb-padctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the XUSB pad controller that is used to configure the USB pads + used by the XUDC controller. + + phys: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. + + phy-names: + minItems: 1 + maxItems: 8 + items: + anyOf: + - const: usb2-0 + - const: usb2-1 + - const: usb2-2 + - const: usb2-3 + - const: usb3-0 + - const: usb3-1 + - const: usb3-2 + - const: usb3-3 + + dma-coherent: + type: boolean + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - power-domains + - power-domain-names + - nvidia,xusb-padctl + - phys + - phy-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-xusb + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + clocks: + minItems: 9 + clock-names: + minItems: 9 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-xusb + then: + properties: + reg: + minItems: 3 + reg-names: + minItems: 3 + clocks: + minItems: 9 + clock-names: + minItems: 9 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x03610000 0x40000>, + <0x03600000 0x10000>, + <0x03650000 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = , + ; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + + phys = <&pad_lanes_usb2_0>; + phy-names = "usb2-0"; + + }; From patchwork Mon Oct 24 07:41:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 8189 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp307241wru; Mon, 24 Oct 2022 00:44:21 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5V8gu41p/z4lJ5qkWDaZlwqi5ilukTGL8pmBs1e7MLZv7F+Cksne7VmKvTUjmCegtwCxqt X-Received: by 2002:a63:1f13:0:b0:455:80ce:6d36 with SMTP id f19-20020a631f13000000b0045580ce6d36mr27753588pgf.111.1666597460844; Mon, 24 Oct 2022 00:44:20 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666597460; cv=pass; d=google.com; s=arc-20160816; b=W3xPI09uzNaLE4mkVGlaUpBfJkhEXCPeOxHSbcsrUZXJ0CDi8oYcY870257lUo6U6G miHH4/qKSe68OTlTEpAzJbYsoB9af+/2aeN4vUpwmTb9BmSIrR5HuhA1FHHJzimcjwEp ACUlcsyTAD7BRzwa+ETONfVoTQvolmoFdHfkTcrGkgdIg7jgo/+v4XmN180Ar7e6c4Eq poDGLFnXeHiqQrAa4RKH2nuYw9VyTrEBONGAO+3zSzQK7ixxyTkkG2iOwnACkX++tocL p9XLRCmtCykZeKDTqPMQbGLRk7q62bplsItRQRCfJS5bKMgnmX+Zvqh1HtGSXSHCLXUr 3d5g== ARC-Message-Signature: i=2; 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It is a standard i2c slave with GPIO input as IRQ interface. Signed-off-by: Wayne Chang --- .../bindings/usb/cypress,cypd4226.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml diff --git a/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml new file mode 100644 index 000000000000..5ac28ab4e7a1 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cypress,cypd4226.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress cypd4226 UCSI I2C Type-C Controller + +maintainers: + - Wayne Chang + +description: | + The Cypress cypd4226 UCSI I2C type-C controller is a I2C interface type-C + controller. + +properties: + compatible: + const: cypress,cypd4226 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + const: 0x08 + + interrupts: + maxItems: 1 + + cypress,firmware-build: + enum: + - nv + - gn + description: | + the name of the CCGx firmware built for product series. + should be set one of following: + - "nv" for the RTX product series + - "gn" for the Jetson product series + +patternProperties: + '^connector@[0-9a-f]+$': + $ref: /schemas/connector/usb-connector.yaml# + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: true + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <2>; + + ucsi_ccg: ucsi_ccg@8 { + compatible = "cypress,cypd4226"; + interrupt-parent = <&gpio_aon>; + interrupts = ; + reg = <0x08>; + cypress,firmware-build = "gn"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + port { + ucsi_ccg_p0: endpoint { + remote-endpoint = <&usb_role_switch0>; + }; + }; + }; + }; + }; From patchwork Mon Oct 24 07:41:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 8197 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp308082wru; Mon, 24 Oct 2022 00:46:59 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6tN6/7mlBmWEVkALeNlF4JSvtKCoRrPuNBoYi/dUVhIrynSq43PsevZhiO5i5WZ6VKGV3R X-Received: by 2002:a05:6402:5253:b0:461:e870:8507 with SMTP id t19-20020a056402525300b00461e8708507mr922382edd.323.1666597619317; Mon, 24 Oct 2022 00:46:59 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666597619; cv=pass; d=google.com; s=arc-20160816; b=JhQi2ldelx+GbqcD2G1QTKL8EgpmSrRAJjifJC/2Gc3/tExsABNuFDRUn0t8aYSoVj JEVqdD8sEw9dR7tbdE6dbaxhQ8F/Dv2WBH9dISoJSjgdH2xcRTKF/bXxq/rLZ/NCI7ly LtwW2Ddn9aeWMYo8g/7BIFJUqEFNNiC4+5Y1HPQJAJsidr5rClCGUwmV2PAsZdugvY/d 17zq3nFO5VUEe4xLReeLzwPAtGt1/PfAQwdGGBdOxAnhfmtPuf/C6bthQ5XG/D9jqEIB cnRwmcjPMinMnVqCWRKneH2TExTvQ7W18DngvXXnCK2b+HTfdUyJaLEHbkQJ3/J+Dc/v I4tw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AhSz5jILqnukDwOGOPi+0uJTqbDtoYlWacteSGGHesE=; b=dFfU0OPTE1FXXmBNCtBTWNf1DyH80WsIKD3vi0GpYxpItKJBfXPyKahNPEtji4lzCl dSPvH7OnofqpDDJYXxrAYlaiP/8P8z6RfGhtsocUC12t3LA+zNCEUeTK4Dnh7dP8GvV+ GhjmBzpueRRGSAa9rnqb2XtrYdgwWOKWWSTJuFF3dR4PETmo1X9Y3YlT6oRO3CttLz/U OAoa6orPL4rXmisltUe/02sU+TgRcs2KjvMRCHddhEZPUBcktnAor29HZ2Iap0ZRIdRP F/R6cVWN5j85m5mrC4poQdSgLxDfUm2E2QN71KpAmygKpJqtKYPd9z8cE7d+fcusxUbq 6caQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="RRaik/uV"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Wayne Chang --- .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 48 +++++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 184 ++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 170 ++++++++++++++++ 3 files changed, 402 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 9e4d72cfa69f..8acef87a5398 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -61,6 +61,29 @@ mmc@3460000 { non-removable; }; + padctl@3520000 { + vclamp-usb-supply = <&vdd_ao_1v8>; + avdd-usb-supply = <&vdd_ao_3v3>; + + ports { + usb2-0 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-2 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + vbus-supply = <&vdd_5v0_sys>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; }; @@ -69,4 +92,29 @@ pmc@c360000 { nvidia,invert-interrupt; }; }; + + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ao_1v8: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd-AO-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_ao_3v3: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd-AO-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 57ab75328814..b4630280bb32 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2011,6 +2011,190 @@ hda@3510000 { nvidia,model = "NVIDIA Jetson AGX Orin HDA"; status = "okay"; }; + + padctl@3520000 { + status = "okay"; + + pads { + usb2 { + lanes { + usb2-0 { + status = "okay"; + }; + + usb2-1 { + status = "okay"; + }; + + usb2-2 { + status = "okay"; + }; + + usb2-3 { + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + status = "okay"; + }; + + usb3-1 { + status = "okay"; + }; + + usb3-2 { + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "otg"; + usb-role-switch; + status = "okay"; + port { + hs_typec_p1: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p1>; + }; + }; + }; + + usb2-1 { + mode = "host"; + status = "okay"; + port { + hs_typec_p0: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p0>; + }; + }; + }; + + usb2-2 { + mode = "host"; + status = "okay"; + }; + + usb2-3 { + mode = "host"; + status = "okay"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + port { + ss_typec_p0: endpoint { + remote-endpoint = <&ss_ucsi_ccg_p0>; + }; + }; + }; + + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + port { + ss_typec_p1: endpoint { + remote-endpoint = <&ss_ucsi_ccg_p1>; + }; + }; + }; + + usb3-2 { + nvidia,usb2-companion = <3>; + status = "okay"; + }; + }; + }; + + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb3-1"; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", + "usb3-0", "usb3-1", "usb3-2"; + }; + + i2c@c240000 { + status = "okay"; + ucsi_ccg: ucsi_ccg@8 { + compatible = "cypress,cypd4226"; + cypress,firmware-build = "gn"; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0x08>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "host"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + hs_ucsi_ccg_p0: endpoint { + remote-endpoint = <&hs_typec_p0>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + ss_ucsi_ccg_p0: endpoint { + remote-endpoint = <&ss_typec_p0>; + }; + }; + }; + ccg_typec_con1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "USB-C"; + data-role = "dual"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + hs_ucsi_ccg_p1: endpoint { + remote-endpoint = <&hs_typec_p1>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + ss_ucsi_ccg_p1: endpoint { + remote-endpoint = <&ss_typec_p1>; + }; + }; + }; + }; + }; }; chosen { diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 0170bfa8a467..27635d459e4c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -942,6 +942,174 @@ hda@3510000 { status = "disabled"; }; + xusb_padctl: padctl@3520000 { + compatible = "nvidia,tegra234-xusb-padctl"; + reg = <0x03520000 0x20000>, + <0x03540000 0x10000>; + reg-names = "padctl", "ao"; + interrupts = ; + + resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + + usb@3550000 { + compatible = "nvidia,tegra234-xudc"; + reg = <0x03550000 0x8000>, + <0x03558000 0x8000>; + reg-names = "base", "fpci"; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x03610000 0x40000>, + <0x03600000 0x10000>, + <0x03650000 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = , + ; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + fuse@3810000 { compatible = "nvidia,tegra234-efuse"; reg = <0x03810000 0x10000>; @@ -1470,6 +1638,8 @@ gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0xc240000 0x100>; interrupts = ; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C2 From patchwork Mon Oct 24 07:41:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 8190 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp307321wru; Mon, 24 Oct 2022 00:44:38 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6D4uBDVgBx1XXDhKO+g1dgsWA32TYQ+5bjsysYJ4RnbZztuY+MWyONdAVAuHbur983i+JZ X-Received: by 2002:a17:903:1105:b0:178:ae31:aad with SMTP id n5-20020a170903110500b00178ae310aadmr31998746plh.3.1666597477684; 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Signed-off-by: Wayne Chang --- drivers/usb/typec/ucsi/ucsi_ccg.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/typec/ucsi/ucsi_ccg.c b/drivers/usb/typec/ucsi/ucsi_ccg.c index 835f1c4372ba..139707a2f3d6 100644 --- a/drivers/usb/typec/ucsi/ucsi_ccg.c +++ b/drivers/usb/typec/ucsi/ucsi_ccg.c @@ -643,7 +643,7 @@ static int ccg_request_irq(struct ucsi_ccg *uc) { unsigned long flags = IRQF_ONESHOT; - if (!has_acpi_companion(uc->dev)) + if (!dev_fwnode(uc->dev)) flags |= IRQF_TRIGGER_HIGH; return request_threaded_irq(uc->irq, NULL, ccg_irq_handler, flags, dev_name(uc->dev), uc); @@ -1427,6 +1427,12 @@ static void ucsi_ccg_remove(struct i2c_client *client) free_irq(uc->irq, uc); } +static const struct of_device_id ucsi_ccg_of_match_table[] = { + { .compatible = "cypress,cypd4226", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ucsi_ccg_of_match_table); + static const struct i2c_device_id ucsi_ccg_device_id[] = { {"ccgx-ucsi", 0}, {} @@ -1481,6 +1487,7 @@ static struct i2c_driver ucsi_ccg_driver = { .pm = &ucsi_ccg_pm, .dev_groups = ucsi_ccg_groups, .acpi_match_table = amd_i2c_ucsi_match, + .of_match_table = ucsi_ccg_of_match_table, }, .probe = ucsi_ccg_probe, .remove = ucsi_ccg_remove, From patchwork Mon Oct 24 07:41:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 8191 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp307356wru; Mon, 24 Oct 2022 00:44:44 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4HTOkEQasHvv9sz6zS6fbLbGGiVUWZ7hbnhnE2AapJyCKQ1fzAMYrQHCdSU7zRm9nbgwN6 X-Received: by 2002:a65:6753:0:b0:438:e83a:bebc with SMTP id c19-20020a656753000000b00438e83abebcmr26568491pgu.602.1666597484138; Mon, 24 Oct 2022 00:44:44 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666597484; cv=pass; d=google.com; s=arc-20160816; b=iv6v8Bu9dd4Udo8D7ScqiuaoMKBKy8S2PJMLXJuFxsE8XzIl+3TjH5pgT23Xw9H7Hy YhV2TSQ3Vt2if0EVI2z92O0j0jyk69bkpxs4nxO2ANiA+yMDWdYfR293lDm5qwWbr/x0 NjLknwzTPPVAxdsDZzbgXEGG90+vCH6j6CMnvxjDoRh9KX203B2Ct/XAo3AgsUQ2cH8E UQIXLczGEGd4V2mW0GooxKYfUNs+xvUOuZ4gQrENThIFyTBAk/kXAGesfDQv5KZGKp1L zqLmQNh1+DGjqavrqwmi0ffr6mCtN2nE9RaR80xdWuX54JaMRRqiyt5gRwynzbWULgVR JdGw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+rwtb7/RpN/I5cxrexV0M2/iXpnfSaH0+kSxcLazcdY=; b=LS2Zh/RQmGmCxMVZ7IXB0El8DXbkAb5+yV63zeCV5M4ZqdK0Amc/oaP5tMjq3NjbbM JBPIflAcZRX3lNyXJEK9QfM1Tszd/zqLmLT9BglMWL5JlRNddGjg4WtntwJA8FAN+6Ut MV3rpd8/OIUnp54MLcvDckYUPvRYrH+67Gb9jXbBS6xqG/7MOKgYZOboKAcsZYtSoo+S iFGQ86qZzxsaeFqzlNaT7K+XdpgjkUfVmIIQS2NxYLsJ3EqS/e0cnVTm7wfjCtmL608y VIVJFQdATqbdpyX99QeUrhoaCBm+Y+5SAjHKNp4wR2XXCJLQ3Frg9reRAze3SegDE5g6 JHAw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=ExOFtQoW; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Replace ccgx to well-known regex "cypress". Signed-off-by: Wayne Chang --- drivers/usb/typec/ucsi/ucsi_ccg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/typec/ucsi/ucsi_ccg.c b/drivers/usb/typec/ucsi/ucsi_ccg.c index 139707a2f3d6..5d3099e6eb77 100644 --- a/drivers/usb/typec/ucsi/ucsi_ccg.c +++ b/drivers/usb/typec/ucsi/ucsi_ccg.c @@ -1358,7 +1358,7 @@ static int ucsi_ccg_probe(struct i2c_client *client, INIT_WORK(&uc->pm_work, ccg_pm_workaround_work); /* Only fail FW flashing when FW build information is not provided */ - status = device_property_read_u16(dev, "ccgx,firmware-build", + status = device_property_read_u16(dev, "cypress,firmware-build", &uc->fw_build); if (status) dev_err(uc->dev, "failed to get FW build information\n"); From patchwork Mon Oct 24 07:41:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 8192 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp307357wru; Mon, 24 Oct 2022 00:44:44 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4ieFFgvLKxqKLDwNOy0Ly86Vf2LagFZR5WzTzV17MOAVgXggmPdHltJqaQsnn4eFbRAI5Y X-Received: by 2002:a63:6e81:0:b0:46e:9fda:21a8 with SMTP id j123-20020a636e81000000b0046e9fda21a8mr18023682pgc.30.1666597484134; Mon, 24 Oct 2022 00:44:44 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666597484; cv=pass; d=google.com; s=arc-20160816; b=ZvNPy5hYTQieUuDk+Bi6MObllFqob7374qfVjYbP/XAwZ3BkrbMyG70NCdpF7Q6lig PdwBg1EmtTYc3gkvaDFpaoxaTU+zrj0+Jd9rp/bWqUY/9zWmfONmXUiA6N9I0JaoWBsZ A9VcjphGKXAqcAFJQoVmoaLB0Iw87XPPTmyLT5bDRdpPCA7VixOEVO+vfUWOy9CbHjfd jKq6nq8Alq2xyFGpitKfoLGQ1rNwjtgRpC4OeIGEjQfpD0H98Z7DUSCGiD3VYtQb+SXX zwgF6cW+yfP3Xk+yH4rzMO+4bbjGrYpcEtZ7w5KNtiKd5JYOvKCvuFrn6U2chL5t7dax MLNg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TcBLF/mq2RZ/H9uP6zpacL5O9ahpQcoGYxQCfS4Y3W0=; b=UDM2C8Ak9WVTbymcCVxNz2O9je9VK0Iz4LogYQm7l9DxBPJT5Tzh40mU5Yzp7J+QN1 cFmqHY858vlDFhLE8OAmxnqqzh5ioAwKuTZhsj4ZQguQBhri8zthblcYo4VWjh9gZkgT tyrE5BQLS2R53LJ2QyK8WtxgPjqaVClL4r98y/l1IZTbvJgGEvsTTjYQ55llITZbfidb bsGqHafUpFXcyTgO7dvrHEmqqAuS5SIiISUqXFDwsQu2lflxynUZoXbplme7chUmjQE5 UYGSLkrejPv5TfVBALkOmTmn7zSd/dYWUC3OELH5KL5xoaMKtUG5XIXf0sE80VOWaMua mQpw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Vuy472l7; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Replace ccgx to well-known regex "cypress". Signed-off-by: Wayne Chang --- drivers/i2c/busses/i2c-nvidia-gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-nvidia-gpu.c b/drivers/i2c/busses/i2c-nvidia-gpu.c index 12e330cd7635..0934f8ad7f49 100644 --- a/drivers/i2c/busses/i2c-nvidia-gpu.c +++ b/drivers/i2c/busses/i2c-nvidia-gpu.c @@ -260,7 +260,7 @@ MODULE_DEVICE_TABLE(pci, gpu_i2c_ids); static const struct property_entry ccgx_props[] = { /* Use FW built for NVIDIA (nv) only */ - PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'), + PROPERTY_ENTRY_U16("cypress,firmware-build", ('n' << 8) | 'v'), { } }; From patchwork Mon Oct 24 07:41:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 8194 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp307432wru; Mon, 24 Oct 2022 00:45:02 -0700 (PDT) X-Google-Smtp-Source: AMsMyM45btqNl/Zpi1XwrESiXWFGxj7+4/DURYkunkYVHNtzH3S/SR4jEwLMI7TjgbzhJGmKrha7 X-Received: by 2002:a17:90a:7849:b0:20d:2d54:65d with SMTP id y9-20020a17090a784900b0020d2d54065dmr72987860pjl.219.1666597502327; Mon, 24 Oct 2022 00:45:02 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666597502; cv=pass; d=google.com; s=arc-20160816; b=NrvjFDCItjj/KmJ5iqEEOnJs4yYOzTCS3gbE957HbsRP33dtWB+qWYOw7mdp6jHq+C 9wdjpQgkdggzChFlrGFan40DD50GcI4S22PUJvJwfdVvXzwGv8S5GomlhWa+1DAqfgWo YsWNlOpZinxKrKcSybkw9NbRWlKKtIx/ZH1PTqJLmi4OLLgrLLPeYY5Z+QYzQtxkcbV7 ZTHNote77hwl33JiXu2hV+S5wtS0g7fTWge1C6163JGnsULOt8saproxCOgDyFXk6eOY f9iqFaDXfhLKLxb8bxIawvVMFsv0Xpg/QAGhvQXjwERvP3RYjoo7f5Cdgtmc81j/uyhp Abmw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UD6OlE4UhvJktg5lu6zNVkPtW2S5bf69ggfnIUC33Zs=; b=VeFX2FkHkNnGKaJI2q94PS0kSNVT/kN1mBJemRVJqcUWUp4d8o4JNutwGtbtbtl8Ba Y+XRLfPBzMe9SW4NAWuIK/BOtUw8NBsiUSFYC1e6GcIIfNrPw9JbgV8ygI6U0233hfMU T165rUSuxsA3ZcV/egBbCg7iA0jE/UIOQPaEjrSmGimcvAZhwOw88dBXDfeTrf6QrEva WlZ9M7tfhe8ZSWawjM/qJ0eZnTfVs6PmcNQt6eGocL4RHxdmcys0nYVzKOqbawnMzuNe LVGr/Ah8NylVd3XSi/pLCUh1h+QFVFo+vFdAQbhKKTpxReVCut80eGaJB33UNl1LprMj bmDA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=YELKBu+K; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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We should disable the clk when it is done. The 100us delay is for HW recording the calibration value. Signed-off-by: Wayne Chang --- drivers/phy/tegra/xusb-tegra186.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index 0996ede63387..f121b4ffbbfd 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -609,6 +609,10 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) value &= ~USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + udelay(100); + + clk_disable_unprepare(priv->usb2_trk_clk); + mutex_unlock(&padctl->lock); } @@ -633,8 +637,6 @@ static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) value |= USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - clk_disable_unprepare(priv->usb2_trk_clk); - mutex_unlock(&padctl->lock); } From patchwork Mon Oct 24 07:41:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 8193 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp307420wru; Mon, 24 Oct 2022 00:44:59 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4bVDLk9sRhf2oF3JH+DobuMtUhZA6t5vJqgnrTF9c0yTYdlObxt8ez444JqgXmyWUqdB3z X-Received: by 2002:a17:902:e94f:b0:17f:6df3:1a99 with SMTP id b15-20020a170902e94f00b0017f6df31a99mr32356035pll.20.1666597499624; Mon, 24 Oct 2022 00:44:59 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666597499; cv=pass; d=google.com; s=arc-20160816; b=zU/Vc9Fd3OQ2rHBh4jH3DLhs+QueJezG9XnLWj/pH6Iymp4/SeBOL7B9ZXNtmXvfLy x+zPdt/UVKMGARtYiWTB14FqlEEuuMWbwBtyzyZKaXNxOHGvK/v9j1sM+kcHhzw9FFqg wVe+AbJ7Pt9c/DgmhaePU+fPz9YYp6SfichbddcPnPE2iEu7nj9h3/2hrWBf6s+5nm8W 8Tuo6si5IgWhkjCu8hQABklZOW92YKzzlKuMDanwmgCcd44dmWzEjBjx9FiZCPLZrHOl +k5Gi9LMvsorEzbjn2bfm9IUwLyq8umA04zuvYqRL0esTRt2Bs0GpmCwiLo3vlb1UB+P aKGA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=r8cf9GVdx5sRqGXNt6fGcCPxZa/EL1AS2tqtVZPD/co=; b=MVmMTshbHEycs3IPzLZNfywTNe9IwbUlWTR1XSw9TJj+6CiZnGojQw2uCA7drmRStY JmJb9G73Twp732aXoBOnjx48/3FdXHWsgKO/3YQTn+hpfH4cTKj9hrmCE/FtlLz4KwBY lfo8Nn9yIx24c/hgrnUWtij+aBcsADzpt20BG9C2lnFtlow/YCjLZNE/nErZeEqTTBuq nRfN3VtoCFXIspul375LLZ+8Wwv/dpHFEA+YWTYkEyCWkS50YXaH0fci6lyWqPI0Thl4 jUxuVxN2jCCDhe53Uw0kyKGjhey/o86ngln7evfeGKjWmqmGVZlWQZYoNHKg1h8FUwYN B1BA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=LeDNpRKJ; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:21.6604 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf6e61b6-4eb1-48e9-2657-08dab5934920 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5020 X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747554139668160421?= X-GMAIL-MSGID: =?utf-8?q?1747554139668160421?= From: Sing-Han Chen Add support for the XUSB pad controller found on Tegra234 SoCs. It is mostly similar to the same IP found on Tegra194, because most of the Tegra234 XUSB PADCTL registers definition and programming sequence are the same as Tegra194, Tegra234 XUSB PADCTL can share the same driver with Tegra186 and Tegra194 XUSB PADCTL. Introduce a new feature, USB2 HW tracking, for Tegra234. The feature is to enable HW periodical PAD tracking which measure and capture the electric parameters of USB2.0 PAD. Signed-off-by: Sing-Han Chen Co-developed-by: Wayne Chang Signed-off-by: Wayne Chang --- drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 65 +++++++++++++++++++++++++++++-- drivers/phy/tegra/xusb.c | 6 +++ drivers/phy/tegra/xusb.h | 23 +++++++++++ 4 files changed, 92 insertions(+), 3 deletions(-) diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile index 89b84067cb4c..eeeea72de117 100644 --- a/drivers/phy/tegra/Makefile +++ b/drivers/phy/tegra/Makefile @@ -7,4 +7,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_234_SOC) += xusb-tegra186.o obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index f121b4ffbbfd..cc02cea65a21 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -89,6 +89,11 @@ #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12) #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19) #define USB2_PD_TRK BIT(26) +#define USB2_TRK_COMPLETED BIT(31) + +#define XUSB_PADCTL_USB2_BIAS_PAD_CTL2 0x28c +#define USB2_TRK_HW_MODE BIT(0) +#define CYA_TRK_CODE_UPDATE_ON_IDLE BIT(31) #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) #define HSIC_PD_TX_DATA0 BIT(1) @@ -609,9 +614,32 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) value &= ~USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - udelay(100); + if (padctl->soc->poll_trk_completed) { + err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, + USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 100); + if (err) { + /* The failure with polling on trk complete will not + * cause the failure of powering on the bias pad. + */ + dev_warn(dev, "failed to poll USB2 trk completed: %d\n", + err); + } - clk_disable_unprepare(priv->usb2_trk_clk); + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + value |= USB2_TRK_COMPLETED; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + } else { + udelay(100); + } + + if (padctl->soc->trk_hw_mode) { + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + value |= USB2_TRK_HW_MODE; + value &= ~CYA_TRK_CODE_UPDATE_ON_IDLE; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + } else { + clk_disable_unprepare(priv->usb2_trk_clk); + } mutex_unlock(&padctl->lock); } @@ -637,6 +665,13 @@ static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) value |= USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + if (padctl->soc->trk_hw_mode) { + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + value &= ~USB2_TRK_HW_MODE; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + clk_disable_unprepare(priv->usb2_trk_clk); + } + mutex_unlock(&padctl->lock); } @@ -1560,7 +1595,8 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); #endif -#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) +#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ + IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) static const char * const tegra194_xusb_padctl_supply_names[] = { "avdd-usb", "vclamp-usb", @@ -1616,8 +1652,31 @@ const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = { .supply_names = tegra194_xusb_padctl_supply_names, .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), .supports_gen2 = true, + .poll_trk_completed = true, }; EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc); + +const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = { + .num_pads = ARRAY_SIZE(tegra194_pads), + .pads = tegra194_pads, + .ports = { + .usb2 = { + .ops = &tegra186_usb2_port_ops, + .count = 4, + }, + .usb3 = { + .ops = &tegra186_usb3_port_ops, + .count = 4, + }, + }, + .ops = &tegra186_xusb_padctl_ops, + .supply_names = tegra194_xusb_padctl_supply_names, + .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), + .supports_gen2 = true, + .poll_trk_completed = true, + .trk_hw_mode = true, +}; +EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc); #endif MODULE_AUTHOR("JC Kuo "); diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 95091876c422..23d179b1a5b5 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -71,6 +71,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = { .compatible = "nvidia,tegra194-xusb-padctl", .data = &tegra194_xusb_padctl_soc, }, +#endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) + { + .compatible = "nvidia,tegra234-xusb-padctl", + .data = &tegra234_xusb_padctl_soc, + }, #endif { } }; diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index 8cfbbdbd6e0c..ec0b5b023ad1 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -8,6 +8,7 @@ #define __PHY_TEGRA_XUSB_H #include +#include #include #include @@ -433,6 +434,8 @@ struct tegra_xusb_padctl_soc { unsigned int num_supplies; bool supports_gen2; bool need_fake_usb3_port; + bool poll_trk_completed; + bool trk_hw_mode; }; struct tegra_xusb_padctl { @@ -475,6 +478,23 @@ static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, return value; } +static inline u32 padctl_readl_poll(struct tegra_xusb_padctl *padctl, + unsigned long offset, u32 val, u32 mask, int us) +{ + u32 regval; + int err; + + err = readl_poll_timeout_atomic(padctl->regs + offset, regval, + (regval & mask) == val, 1, us); + dev_dbg(padctl->dev, "%08lx poll > %08x\n", offset, regval); + if (err) { + dev_err(padctl->dev, "%08lx poll timeout > %08x\n", offset, + regval); + } + + return err; +} + struct tegra_xusb_lane *tegra_xusb_find_lane(struct tegra_xusb_padctl *padctl, const char *name, unsigned int index); @@ -491,5 +511,8 @@ extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc; #if defined(CONFIG_ARCH_TEGRA_194_SOC) extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc; #endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) +extern const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc; +#endif #endif /* __PHY_TEGRA_XUSB_H */ From patchwork Mon Oct 24 07:41:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 8196 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp307625wru; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:23.0978 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9dafc26c-4ba8-4add-7b7c-08dab59349fb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7660 X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747554183908994757?= X-GMAIL-MSGID: =?utf-8?q?1747554183908994757?= From: Sing-Han Chen This change adds Tegra234 XUSB host mode controller support. In Tegra234, some of the registers have moved to bar2 space. The new soc variable has_bar2 indicates the chip with bar2 area. This patch adds new reg helper to let the driver reuse the same code for those chips with bar2 support. The new soc variables has_ifr indicates the chip with IFR FW loading support. IFR registers would be configured in MB1, and FW loading will be triggered in MB2. Signed-off-by: Sing-Han Chen Co-developed-by: Wayne Chang Signed-off-by: Wayne Chang --- drivers/usb/host/xhci-tegra.c | 277 +++++++++++++++++++++++++++++----- 1 file changed, 237 insertions(+), 40 deletions(-) diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c index bdb776553826..86036eeece43 100644 --- a/drivers/usb/host/xhci-tegra.c +++ b/drivers/usb/host/xhci-tegra.c @@ -44,6 +44,9 @@ #define XUSB_CFG_4 0x010 #define XUSB_BASE_ADDR_SHIFT 15 #define XUSB_BASE_ADDR_MASK 0x1ffff +#define XUSB_CFG_7 0x01c +#define XUSB_BASE2_ADDR_SHIFT 16 +#define XUSB_BASE2_ADDR_MASK 0xffff #define XUSB_CFG_16 0x040 #define XUSB_CFG_24 0x060 #define XUSB_CFG_AXI_CFG 0x0f8 @@ -75,6 +78,20 @@ #define MBOX_SMI_INTR_FW_HANG BIT(1) #define MBOX_SMI_INTR_EN BIT(3) +/* BAR2 registers */ +#define XUSB_BAR2_ARU_MBOX_CMD 0x004 +#define XUSB_BAR2_ARU_MBOX_DATA_IN 0x008 +#define XUSB_BAR2_ARU_MBOX_DATA_OUT 0x00c +#define XUSB_BAR2_ARU_MBOX_OWNER 0x010 +#define XUSB_BAR2_ARU_SMI_INTR 0x014 +#define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0 0x01c +#define XUSB_BAR2_ARU_IFRDMA_CFG0 0x0e0 +#define XUSB_BAR2_ARU_IFRDMA_CFG1 0x0e4 +#define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD 0x0e8 +#define XUSB_BAR2_ARU_C11_CSBRANGE 0x9c +#define XUSB_BAR2_ARU_FW_SCRATCH 0x1000 +#define XUSB_BAR2_CSB_BASE_ADDR 0x2000 + /* IPFS registers */ #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4 @@ -111,6 +128,9 @@ #define IMFILLRNG1_TAG_HI_SHIFT 16 #define XUSB_FALC_IMFILLCTL 0x158 +/* CSB ARU registers */ +#define XUSB_CSB_ARU_SCRATCH0 0x100100 + /* MP CSB registers */ #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 @@ -131,6 +151,9 @@ #define IMEM_BLOCK_SIZE 256 +#define FW_IOCTL_TYPE_SHIFT (24) +#define FW_IOCTL_CFGTBL_READ (17) + struct tegra_xusb_fw_header { __le32 boot_loadaddr_in_imem; __le32 boot_codedfi_offset; @@ -175,6 +198,7 @@ struct tegra_xusb_mbox_regs { u16 data_in; u16 data_out; u16 owner; + u16 smi_intr; }; struct tegra_xusb_context_soc { @@ -189,6 +213,7 @@ struct tegra_xusb_context_soc { } fpci; }; +struct tegra_xusb_soc_ops; struct tegra_xusb_soc { const char *firmware; const char * const *supply_names; @@ -205,11 +230,15 @@ struct tegra_xusb_soc { } ports; struct tegra_xusb_mbox_regs mbox; + struct tegra_xusb_soc_ops *ops; bool scale_ss_clock; bool has_ipfs; bool lpm_support; bool otg_reset_sspi; + + bool has_bar2; + bool has_ifr; }; struct tegra_xusb_context { @@ -230,6 +259,8 @@ struct tegra_xusb { void __iomem *ipfs_base; void __iomem *fpci_base; + void __iomem *bar2_base; + resource_size_t bar2_start; const struct tegra_xusb_soc *soc; @@ -276,6 +307,17 @@ struct tegra_xusb { struct tegra_xusb_context context; }; +struct tegra_xusb_soc_ops { + u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, + unsigned int offset); + void (*mbox_reg_writel)(struct tegra_xusb *tegra, + u32 value, unsigned int offset); + u32 (*csb_reg_readl)(struct tegra_xusb *tegra, + unsigned int offset); + void (*csb_reg_writel)(struct tegra_xusb *tegra, + u32 value, unsigned int offset); +}; + static struct hc_driver __read_mostly tegra_xhci_hc_driver; static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) @@ -300,7 +342,33 @@ static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, writel(value, tegra->ipfs_base + offset); } +static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + return readl(tegra->bar2_base + offset); +} + +static inline void bar2_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + writel(value, tegra->bar2_base + offset); +} + static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; + + return ops->csb_reg_readl(tegra, offset); +} + +static void csb_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; + + ops->csb_reg_writel(tegra, value, offset); +} + +static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset) { u32 page = CSB_PAGE_SELECT(offset); u32 ofs = CSB_PAGE_OFFSET(offset); @@ -310,7 +378,7 @@ static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); } -static void csb_writel(struct tegra_xusb *tegra, u32 value, +static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value, unsigned int offset) { u32 page = CSB_PAGE_SELECT(offset); @@ -320,6 +388,26 @@ static void csb_writel(struct tegra_xusb *tegra, u32 value, fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); } +static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + u32 page = CSB_PAGE_SELECT(offset); + u32 ofs = CSB_PAGE_OFFSET(offset); + + bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); + + return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs); +} + +static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + u32 page = CSB_PAGE_SELECT(offset); + u32 ofs = CSB_PAGE_OFFSET(offset); + + bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); + bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs); +} + static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, unsigned long rate) { @@ -451,6 +539,7 @@ static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, const struct tegra_xusb_mbox_msg *msg) { + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; bool wait_for_idle = false; u32 value; @@ -459,15 +548,15 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, * ACK/NAK messages. */ if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_NONE) { dev_err(tegra->dev, "mailbox is busy\n"); return -EBUSY; } - fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); + ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_SW) { dev_err(tegra->dev, "failed to acquire mailbox\n"); return -EBUSY; @@ -477,17 +566,17 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, } value = tegra_xusb_mbox_pack(msg); - fpci_writel(tegra, value, tegra->soc->mbox.data_in); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in); - value = fpci_readl(tegra, tegra->soc->mbox.cmd); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); value |= MBOX_INT_EN | MBOX_DEST_FALC; - fpci_writel(tegra, value, tegra->soc->mbox.cmd); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); if (wait_for_idle) { unsigned long timeout = jiffies + msecs_to_jiffies(250); while (time_before(jiffies, timeout)) { - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value == MBOX_OWNER_NONE) break; @@ -495,7 +584,7 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, } if (time_after(jiffies, timeout)) - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_NONE) return -ETIMEDOUT; @@ -507,11 +596,12 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) { struct tegra_xusb *tegra = data; + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; u32 value; /* clear mailbox interrupts */ - value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); - fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr); if (value & MBOX_SMI_INTR_FW_HANG) dev_err(tegra->dev, "controller firmware hang\n"); @@ -664,6 +754,7 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) { struct tegra_xusb *tegra = data; + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; struct tegra_xusb_mbox_msg msg; u32 value; @@ -672,16 +763,16 @@ static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) if (pm_runtime_suspended(tegra->dev) || tegra->suspended) goto out; - value = fpci_readl(tegra, tegra->soc->mbox.data_out); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out); tegra_xusb_mbox_unpack(&msg, value); - value = fpci_readl(tegra, tegra->soc->mbox.cmd); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); value &= ~MBOX_DEST_SMI; - fpci_writel(tegra, value, tegra->soc->mbox.cmd); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); /* clear mailbox owner if no ACK/NAK is required */ if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) - fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); + ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); tegra_xusb_mbox_handle(tegra, &msg); @@ -709,6 +800,15 @@ static void tegra_xusb_config(struct tegra_xusb *tegra) value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); fpci_writel(tegra, value, XUSB_CFG_4); + /* Program BAR2 space */ + if (tegra->soc->has_bar2) { + value = fpci_readl(tegra, XUSB_CFG_7); + value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); + value |= tegra->bar2_start & + (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); + fpci_writel(tegra, value, XUSB_CFG_7); + } + usleep_range(100, 200); /* Enable bus master */ @@ -881,21 +981,36 @@ static int tegra_xusb_request_firmware(struct tegra_xusb *tegra) return 0; } +static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra) +{ + struct xhci_cap_regs __iomem *cap_regs; + struct xhci_op_regs __iomem *op_regs; + int ret; + u32 val; + + cap_regs = tegra->regs; + op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase)); + + ret = readl_poll_timeout(&op_regs->status, val, !(val & STS_CNR), 1000, 200000); + + if (ret) + dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n", + csb_readl(tegra, XUSB_FALC_CPUCTL)); + + return ret; +} + static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) { unsigned int code_tag_blocks, code_size_blocks, code_blocks; - struct xhci_cap_regs __iomem *cap = tegra->regs; struct tegra_xusb_fw_header *header; struct device *dev = tegra->dev; - struct xhci_op_regs __iomem *op; - unsigned long timeout; time64_t timestamp; u64 address; u32 value; int err; header = (struct tegra_xusb_fw_header *)tegra->fw.virt; - op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase)); if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { dev_info(dev, "Firmware already loaded, Falcon state %#x\n", @@ -968,26 +1083,43 @@ static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */ csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); - timeout = jiffies + msecs_to_jiffies(200); + if (tegra_xusb_wait_for_falcon(tegra)) + return -EIO; - do { - value = readl(&op->status); - if ((value & STS_CNR) == 0) - break; + timestamp = le32_to_cpu(header->fwimg_created_time); - usleep_range(1000, 2000); - } while (time_is_after_jiffies(timeout)); + dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); + + return 0; +} - value = readl(&op->status); - if (value & STS_CNR) { - value = csb_readl(tegra, XUSB_FALC_CPUCTL); - dev_err(dev, "XHCI controller not read: %#010x\n", value); +static u32 tegra_xusb_read_firmware_header(struct tegra_xusb *tegra, u32 offset) +{ + /* + * We only accept reading the firmware config table + * The offset should not exceed the fw header structure + */ + if (offset >= sizeof(struct tegra_xusb_fw_header)) + return 0; + + bar2_writel(tegra, (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset, + XUSB_BAR2_ARU_FW_SCRATCH); + return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0); +} + +static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra) +{ + time64_t timestamp; + + if (tegra_xusb_wait_for_falcon(tegra)) return -EIO; - } - timestamp = le32_to_cpu(header->fwimg_created_time); +#define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32))) + timestamp = tegra_xusb_read_firmware_header(tegra, + offsetof_32(struct tegra_xusb_fw_header, + fwimg_created_time) << 2); - dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); + dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); return 0; } @@ -1403,7 +1535,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) struct of_phandle_args args; struct tegra_xusb *tegra; struct device_node *np; - struct resource *regs; + struct resource *res, *regs; struct xhci_hcd *xhci; unsigned int i, j, k; struct phy *phy; @@ -1435,6 +1567,11 @@ static int tegra_xusb_probe(struct platform_device *pdev) tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2); if (IS_ERR(tegra->ipfs_base)) return PTR_ERR(tegra->ipfs_base); + } else if (tegra->soc->has_bar2) { + tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, 2, &res); + if (IS_ERR(tegra->bar2_base)) + return PTR_ERR(tegra->bar2_base); + tegra->bar2_start = res->start; } tegra->xhci_irq = platform_get_irq(pdev, 0); @@ -1651,10 +1788,13 @@ static int tegra_xusb_probe(struct platform_device *pdev) goto disable_phy; } - err = tegra_xusb_request_firmware(tegra); - if (err < 0) { - dev_err(&pdev->dev, "failed to request firmware: %d\n", err); - goto disable_phy; + if (!tegra->soc->has_ifr) { + err = tegra_xusb_request_firmware(tegra); + if (err < 0) { + dev_err(&pdev->dev, + "failed to request firmware: %d\n", err); + goto disable_phy; + } } err = tegra_xusb_unpowergate_partitions(tegra); @@ -1663,7 +1803,10 @@ static int tegra_xusb_probe(struct platform_device *pdev) tegra_xusb_config(tegra); - err = tegra_xusb_load_firmware(tegra); + if (tegra->soc->has_ifr) + err = tegra_xusb_init_ifr_firmware(tegra); + else + err = tegra_xusb_load_firmware(tegra); if (err < 0) { dev_err(&pdev->dev, "failed to load firmware: %d\n", err); goto powergate; @@ -2070,7 +2213,10 @@ static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime) tegra_xusb_config(tegra); tegra_xusb_restore_context(tegra); - err = tegra_xusb_load_firmware(tegra); + if (tegra->soc->has_ifr) + err = tegra_xusb_init_ifr_firmware(tegra); + else + err = tegra_xusb_load_firmware(tegra); if (err < 0) { dev_err(tegra->dev, "failed to load firmware: %d\n", err); goto disable_phy; @@ -2271,6 +2417,13 @@ static const struct tegra_xusb_context_soc tegra124_xusb_context = { }, }; +static struct tegra_xusb_soc_ops tegra124_ops = { + .mbox_reg_readl = &fpci_readl, + .mbox_reg_writel = &fpci_writel, + .csb_reg_readl = &fpci_csb_readl, + .csb_reg_writel = &fpci_csb_writel, +}; + static const struct tegra_xusb_soc tegra124_soc = { .firmware = "nvidia/tegra124/xusb.bin", .supply_names = tegra124_supply_names, @@ -2286,11 +2439,13 @@ static const struct tegra_xusb_soc tegra124_soc = { .scale_ss_clock = true, .has_ipfs = true, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, }; MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); @@ -2322,11 +2477,13 @@ static const struct tegra_xusb_soc tegra210_soc = { .scale_ss_clock = false, .has_ipfs = true, .otg_reset_sspi = true, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, }; MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); @@ -2363,11 +2520,13 @@ static const struct tegra_xusb_soc tegra186_soc = { .scale_ss_clock = false, .has_ipfs = false, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, .lpm_support = true, }; @@ -2394,21 +2553,59 @@ static const struct tegra_xusb_soc tegra194_soc = { .scale_ss_clock = false, .has_ipfs = false, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0x68, .data_in = 0x6c, .data_out = 0x70, .owner = 0x74, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, .lpm_support = true, }; MODULE_FIRMWARE("nvidia/tegra194/xusb.bin"); +static struct tegra_xusb_soc_ops tegra234_ops = { + .mbox_reg_readl = &bar2_readl, + .mbox_reg_writel = &bar2_writel, + .csb_reg_readl = &bar2_csb_readl, + .csb_reg_writel = &bar2_csb_writel, +}; + +static const struct tegra_xusb_soc tegra234_soc = { + .firmware = "nvidia/tegra234/xusb.bin", + .supply_names = tegra194_supply_names, + .num_supplies = ARRAY_SIZE(tegra194_supply_names), + .phy_types = tegra194_phy_types, + .num_types = ARRAY_SIZE(tegra194_phy_types), + .context = &tegra186_xusb_context, + .ports = { + .usb3 = { .offset = 0, .count = 4, }, + .usb2 = { .offset = 4, .count = 4, }, + }, + .scale_ss_clock = false, + .has_ipfs = false, + .otg_reset_sspi = false, + .ops = &tegra234_ops, + .mbox = { + .cmd = XUSB_BAR2_ARU_MBOX_CMD, + .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN, + .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT, + .owner = XUSB_BAR2_ARU_MBOX_OWNER, + .smi_intr = XUSB_BAR2_ARU_SMI_INTR, + }, + .lpm_support = true, + .has_bar2 = true, + .has_ifr = true, +}; +MODULE_FIRMWARE("nvidia/tegra234/xusb.bin"); + static const struct of_device_id tegra_xusb_of_match[] = { { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc }, + { .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc }, { }, }; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:24.0354 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 233c5e8a-88cf-4bd0-8d27-08dab5934a8a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT087.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5241 X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747554168821940635?= X-GMAIL-MSGID: =?utf-8?q?1747554168821940635?= From: Sing-Han Chen This commit adds support for XUSB device mode controller support on Tegra234 SoC. This is very similar to the existing Tegra194 XUDC. Signed-off-by: Sing-Han Chen Signed-off-by: Wayne Chang --- drivers/usb/gadget/udc/tegra-xudc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 76919d7570d2..ff697190469b 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -3660,6 +3660,19 @@ static struct tegra_xudc_soc tegra194_xudc_soc_data = { .has_ipfs = false, }; +static struct tegra_xudc_soc tegra234_xudc_soc_data = { + .clock_names = tegra186_xudc_clock_names, + .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), + .num_phys = 4, + .u1_enable = true, + .u2_enable = true, + .lpm_enable = true, + .invalid_seq_num = false, + .pls_quirk = false, + .port_reset_quirk = false, + .has_ipfs = false, +}; + static const struct of_device_id tegra_xudc_of_match[] = { { .compatible = "nvidia,tegra210-xudc", @@ -3673,6 +3686,10 @@ static const struct of_device_id tegra_xudc_of_match[] = { .compatible = "nvidia,tegra194-xudc", .data = &tegra194_xudc_soc_data }, + { + .compatible = "nvidia,tegra234-xudc", + .data = &tegra234_xudc_soc_data + }, { } }; MODULE_DEVICE_TABLE(of, tegra_xudc_of_match);