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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w127-20020a623085000000b0063b57ad9891si31917542pfw.315.2023.05.03.06.05.27; Wed, 03 May 2023 06:05:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=GDgWhCa7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229712AbjECNCD (ORCPT + 99 others); Wed, 3 May 2023 09:02:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229601AbjECNCB (ORCPT ); Wed, 3 May 2023 09:02:01 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C3611A5; Wed, 3 May 2023 06:01:58 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-959a3e2dc72so1010251766b.2; Wed, 03 May 2023 06:01:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683118917; x=1685710917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JhiOdhDEfb+iWh2Mv/2vV0thu45ELxEEl7Ux8olY3M8=; b=GDgWhCa7cTPRM91qlWVp/Nbs6yAAzQTxkEm9m3fVLU05H+ocy+NgohNDdjESCghGYH pqeZbQHx/QVpX+CWCp9T/QRqvV3Vnl4e6jhqqtAHTxMeNTLLl8KDEl6dF1aDfH46bXuM 0RaDonz5kNkl4RUHwaKFsXP0PS9NSwIVO7JqfS4xb/rSqPAD6u8QcQ109WAC++fWH5si wt2eEFU5qXN7HhHQ5P08n85ETKpzJIxQRnJhRMVHbfyICPnxiqwP0N1IKeZUcs8Y+Rw8 2ifiKzBy0i4GzGz8dSpo+2UjlKo4bMNkAlqqBNhjCzaezSEVgEbuNBVo7wWyFsGCIQ8H SYMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683118917; x=1685710917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JhiOdhDEfb+iWh2Mv/2vV0thu45ELxEEl7Ux8olY3M8=; b=EaPgHR1HGz+gkq0PbQBN+q5ibIyUWbTaEq/hb66Z2DmgxSYJ/09bOO/6BEnR8Jc31F kmPk3wyFFX2oTLPNweqHUErcG/OwBEmZIEs1J6euAPyN4AnZOvT1NR3POzSMAgyzxeIc Fxj25nXJYGUm2M8TIPfSP1cLmt56HbEy910ayOXwxG8V7x4CuoPN636AQT8FFdAJFZ6B L7e4+0Pkr2vMUb+XqaxlvyQ+p3cDiwmtfmC9twNvHEOUf9f7E6nc3iWWnWoeEc8l/ryb fYtO4JfMXdMfak/N/k5zyD8S8b0L4tq6M4LoHWL4YuiCzTeXLnhwUJQu5ZFWFKrB8p7x zsWA== X-Gm-Message-State: AC+VfDz0qEF32QF+cDxqEWESfTkCNSPwmP3YDKxzhfjEpWFgemKQnqqO 6hwHGwpT8joReuG7UQKkG1o= X-Received: by 2002:a17:906:ef0a:b0:958:5c21:3fa7 with SMTP id f10-20020a170906ef0a00b009585c213fa7mr3490600ejs.25.1683118916731; Wed, 03 May 2023 06:01:56 -0700 (PDT) Received: from localhost.localdomain ([95.183.227.33]) by smtp.gmail.com with ESMTPSA id my17-20020a1709065a5100b0095728081944sm16105578ejc.146.2023.05.03.06.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 06:01:56 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov Cc: Yassine Oudjana , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 1/3] dt-bindings: clock: qcom,msm8996-cbf: Add compatible for MSM8996 Pro Date: Wed, 3 May 2023 16:00:50 +0300 Message-Id: <20230503130051.144708-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230503130051.144708-1-y.oudjana@protonmail.com> References: <20230503130051.144708-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764878336795936183?= X-GMAIL-MSGID: =?utf-8?q?1764878336795936183?= From: Yassine Oudjana The CBF clock on MSM8996 Pro has a different divisor compared to MSM8996 and is therefore not fully compatible with it. Add a new compatible string to differentiate between them. Signed-off-by: Yassine Oudjana Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml index 3ffe69d8cdd5..0dfbd8c4d465 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml @@ -15,7 +15,9 @@ description: > properties: compatible: - const: qcom,msm8996-cbf + enum: + - qcom,msm8996-cbf + - qcom,msm8996pro-cbf reg: maxItems: 1 From patchwork Wed May 3 13:00:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 89744 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1314920vqo; Wed, 3 May 2023 06:09:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7izOCgths0KyTMOR3AeZh3reyrETfdBDXQHzGNXpfMsi6N0QRJqBmn3KpQX19a8D7T5KVq X-Received: by 2002:a05:6a00:248c:b0:623:c117:f20e with SMTP id c12-20020a056a00248c00b00623c117f20emr29822217pfv.19.1683119364241; Wed, 03 May 2023 06:09:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683119364; cv=none; d=google.com; s=arc-20160816; b=NMEMANf/2rRXhuGAYAPbdMZrYQJFpsOr364BRTr4kAKLHzs4XUEhA4Cx5C0WVDrYoZ ozcipkWEXvk+lIMvH/Po+3/7cGYO3jgm2L/80IAZPR7APnhPtkb42agwmFNf44X8QCqH yOYekgQTb8uJLhPtZyODYtFbQRaMMENZm61s66RH6njoMjwQ6RWHfekNQdZ5OaD5Fwrl AD42+PZ3woUMV6srSUT6uDSm2N8GNC9vsD3Kcds/f89mhT4mfEniorNi4MLfNrB/BVx7 umQHbVi5s83Zqz1P1nDDuehBJj8zZ9S3PUKmFv++EA2EznVUvkq04bcVTW2bj5h8vT85 JHWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1V3rgI/5A2MTfAJo/8hueKDPxSOGXJm1mCHXT4uBpmY=; b=q969yGm0D802l7qolG6KiUO6aUmkweVvaaoOVa1Mpq/yfrVqsSodvcLx2pgm7jb2Jx Ux6lxZuELNr3n9t9HdpMddl4dxpHDOeIXUyq4vhw8Z6AcZQulyEPs2g2kfMFXaPzKfHr iHFnr5qFXuEKxWcYpNZyFlkWmH2Qn+c6t4wuVhxtpEo80e7zxA5Zed9SkX84UI9ZKonp VjI2s6CA+yIzfuYUXjZt5RdCivhEJbHmEEHDbhQMvGnsx9M5D8tHOP9XA2he2KqdXRwM iGr9NadRLI51rBNI52fTdN4/HJmgdDhrvsM6UDK4G2zzI+dVFlaCH8vr2gbn5K5zIYgL SIDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=PNvCtK6W; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996pro.dtsi | 51 ++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi index a679a9c0cf99..b74cff06f300 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi @@ -24,101 +24,121 @@ opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-460800000 { opp-hz = /bits/ 64 <460800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-537600000 { opp-hz = /bits/ 64 <537600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-614400000 { opp-hz = /bits/ 64 <614400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-691200000 { opp-hz = /bits/ 64 <691200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-768000000 { opp-hz = /bits/ 64 <768000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <441600>; }; opp-979200000 { opp-hz = /bits/ 64 <979200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <614400>; }; opp-1132800000 { opp-hz = /bits/ 64 <1132800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <691200>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <768000>; }; opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <844800>; }; opp-1363200000 { opp-hz = /bits/ 64 <1363200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <979200>; }; opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; opp-supported-hw = <0x20>; clock-latency-ns = <200000>; + opp-peak-kBps = <1516800>; }; opp-2188800000 { opp-hz = /bits/ 64 <2188800000>; opp-supported-hw = <0x10>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; }; @@ -131,136 +151,163 @@ opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-460800000 { opp-hz = /bits/ 64 <460800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-537600000 { opp-hz = /bits/ 64 <537600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-614400000 { opp-hz = /bits/ 64 <614400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <192000>; }; opp-691200000 { opp-hz = /bits/ 64 <691200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-748800000 { opp-hz = /bits/ 64 <748800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-825600000 { opp-hz = /bits/ 64 <825600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <441600>; }; opp-979200000 { opp-hz = /bits/ 64 <979200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <441600>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-1132800000 { opp-hz = /bits/ 64 <1132800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <614400>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <691200>; }; opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <768000>; }; opp-1363200000 { opp-hz = /bits/ 64 <1363200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <844800>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <979200>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1056000>; }; opp-1670400000 { opp-hz = /bits/ 64 <1670400000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1747200000 { opp-hz = /bits/ 64 <1747200000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1286400>; }; opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-supported-hw = <0x70>; clock-latency-ns = <200000>; + opp-peak-kBps = <1363200>; }; opp-1977600000 { opp-hz = /bits/ 64 <1977600000>; opp-supported-hw = <0x30>; clock-latency-ns = <200000>; + opp-peak-kBps = <1440000>; }; opp-2054400000 { opp-hz = /bits/ 64 <2054400000>; opp-supported-hw = <0x30>; clock-latency-ns = <200000>; + opp-peak-kBps = <1516800>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; opp-supported-hw = <0x30>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2246400000 { opp-hz = /bits/ 64 <2246400000>; opp-supported-hw = <0x10>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2342400000 { opp-hz = /bits/ 64 <2342400000>; opp-supported-hw = <0x10>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; }; }; @@ -289,3 +336,7 @@ opp-560000000 { }; /* The rest is inherited from msm8996 */ }; + +&cbf { + compatible = "qcom,msm8996pro-cbf"; +}; From patchwork Wed May 3 13:00:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 89750 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1322185vqo; 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Handle the difference accordingly. Signed-off-by: Yassine Oudjana --- drivers/clk/qcom/clk-cbf-8996.c | 121 ++++++++++++++++++++++++++++---- 1 file changed, 106 insertions(+), 15 deletions(-) diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-8996.c index 1bb2cd956d68..a3e96578ddd9 100644 --- a/drivers/clk/qcom/clk-cbf-8996.c +++ b/drivers/clk/qcom/clk-cbf-8996.c @@ -65,6 +65,19 @@ static const struct alpha_pll_config cbfpll_config = { .early_output_mask = BIT(3), }; +static const struct alpha_pll_config cbfpll_pro_config = { + .l = 72, + .config_ctl_val = 0x200d4828, + .config_ctl_hi_val = 0x006, + .test_ctl_val = 0x1c000000, + .test_ctl_hi_val = 0x00004000, + .pre_div_mask = BIT(12), + .post_div_mask = 0x3 << 8, + .post_div_val = 0x3 << 8, + .main_output_mask = BIT(0), + .early_output_mask = BIT(3), +}; + static struct clk_alpha_pll cbf_pll = { .offset = CBF_PLL_OFFSET, .regs = cbf_pll_regs, @@ -93,6 +106,20 @@ static struct clk_fixed_factor cbf_pll_postdiv = { }, }; +static struct clk_fixed_factor cbf_pro_pll_postdiv = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data){ + .name = "cbf_pll_postdiv", + .parent_hws = (const struct clk_hw*[]){ + &cbf_pll.clkr.hw + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static const struct clk_parent_data cbf_mux_parent_data[] = { { .index = DT_XO }, { .hw = &cbf_pll.clkr.hw }, @@ -100,6 +127,13 @@ static const struct clk_parent_data cbf_mux_parent_data[] = { { .index = DT_APCS_AUX }, }; +static const struct clk_parent_data cbf_pro_mux_parent_data[] = { + { .index = DT_XO }, + { .hw = &cbf_pll.clkr.hw }, + { .hw = &cbf_pro_pll_postdiv.hw }, + { .index = DT_APCS_AUX }, +}; + struct clk_cbf_8996_mux { u32 reg; struct notifier_block nb; @@ -140,12 +174,14 @@ static int clk_cbf_8996_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_hw *parent; + struct clk_hw *post_div_hw = clk_hw_get_parent_by_index(hw, CBF_DIV_INDEX); + struct clk_fixed_factor *post_div = to_clk_fixed_factor(post_div_hw); - if (req->rate < (DIV_THRESHOLD / 2)) + if (req->rate < (DIV_THRESHOLD / post_div->div)) return -EINVAL; if (req->rate < DIV_THRESHOLD) - parent = clk_hw_get_parent_by_index(hw, CBF_DIV_INDEX); + parent = post_div_hw; else parent = clk_hw_get_parent_by_index(hw, CBF_PLL_INDEX); @@ -177,10 +213,24 @@ static struct clk_cbf_8996_mux cbf_mux = { }, }; +static struct clk_cbf_8996_mux cbf_pro_mux = { + .reg = CBF_MUX_OFFSET, + .nb.notifier_call = cbf_clk_notifier_cb, + .clkr.hw.init = &(struct clk_init_data) { + .name = "cbf_mux", + .parent_data = cbf_pro_mux_parent_data, + .num_parents = ARRAY_SIZE(cbf_pro_mux_parent_data), + .ops = &clk_cbf_8996_mux_ops, + /* CPU clock is critical and should never be gated */ + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + }, +}; + static int cbf_clk_notifier_cb(struct notifier_block *nb, unsigned long event, void *data) { struct clk_notifier_data *cnd = data; + struct clk_hw *hw = __clk_get_hw(cnd->clk); switch (event) { case PRE_RATE_CHANGE: @@ -188,19 +238,19 @@ static int cbf_clk_notifier_cb(struct notifier_block *nb, unsigned long event, * Avoid overvolting. clk_core_set_rate_nolock() walks from top * to bottom, so it will change the rate of the PLL before * chaging the parent of PMUX. This can result in pmux getting - * clocked twice the expected rate. + * clocked twice (or 4 times) the expected rate. * - * Manually switch to PLL/2 here. + * Manually switch to PLL/DIV here. */ if (cnd->old_rate > DIV_THRESHOLD && cnd->new_rate < DIV_THRESHOLD) - clk_cbf_8996_mux_set_parent(&cbf_mux.clkr.hw, CBF_DIV_INDEX); + clk_cbf_8996_mux_set_parent(hw, CBF_DIV_INDEX); break; case ABORT_RATE_CHANGE: /* Revert manual change */ if (cnd->new_rate < DIV_THRESHOLD && cnd->old_rate > DIV_THRESHOLD) - clk_cbf_8996_mux_set_parent(&cbf_mux.clkr.hw, CBF_PLL_INDEX); + clk_cbf_8996_mux_set_parent(hw, CBF_PLL_INDEX); break; default: break; @@ -213,11 +263,50 @@ static struct clk_hw *cbf_msm8996_hw_clks[] = { &cbf_pll_postdiv.hw, }; +static struct clk_hw *cbf_msm8996pro_hw_clks[] = { + &cbf_pro_pll_postdiv.hw, +}; + static struct clk_regmap *cbf_msm8996_clks[] = { &cbf_pll.clkr, &cbf_mux.clkr, }; +static struct clk_regmap *cbf_msm8996pro_clks[] = { + &cbf_pll.clkr, + &cbf_pro_mux.clkr, +}; + +struct cbf_match_data { + const struct alpha_pll_config *config; + struct clk_fixed_factor *cbf_pll_postdiv; + struct clk_cbf_8996_mux *cbf_mux; + struct clk_hw **hw_clks; + size_t nr_hw_clks; + struct clk_regmap **clks; + size_t nr_clks; +}; + +static const struct cbf_match_data cbf_msm8996_match_data = { + .config = &cbfpll_config, + .cbf_pll_postdiv = &cbf_pll_postdiv, + .cbf_mux = &cbf_mux, + .hw_clks = cbf_msm8996_hw_clks, + .nr_hw_clks = ARRAY_SIZE(cbf_msm8996_hw_clks), + .clks = cbf_msm8996_clks, + .nr_clks = ARRAY_SIZE(cbf_msm8996_clks) +}; + +static const struct cbf_match_data cbf_msm8996pro_match_data = { + .config = &cbfpll_pro_config, + .cbf_pll_postdiv = &cbf_pro_pll_postdiv, + .cbf_mux = &cbf_pro_mux, + .hw_clks = cbf_msm8996pro_hw_clks, + .nr_hw_clks = ARRAY_SIZE(cbf_msm8996pro_hw_clks), + .clks = cbf_msm8996pro_clks, + .nr_clks = ARRAY_SIZE(cbf_msm8996pro_clks) +}; + static const struct regmap_config cbf_msm8996_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -274,6 +363,7 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) void __iomem *base; struct regmap *regmap; struct device *dev = &pdev->dev; + const struct cbf_match_data *data = of_device_get_match_data(dev); int i, ret; base = devm_platform_ioremap_resource(pdev, 0); @@ -295,7 +385,7 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL); - clk_alpha_pll_configure(&cbf_pll, regmap, &cbfpll_config); + clk_alpha_pll_configure(&cbf_pll, regmap, data->config); /* Wait for PLL(s) to lock */ udelay(50); @@ -311,27 +401,27 @@ static int qcom_msm8996_cbf_probe(struct platform_device *pdev) /* Switch CBF to use the primary PLL */ regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1); - for (i = 0; i < ARRAY_SIZE(cbf_msm8996_hw_clks); i++) { - ret = devm_clk_hw_register(dev, cbf_msm8996_hw_clks[i]); + for (i = 0; i < data->nr_hw_clks; i++) { + ret = devm_clk_hw_register(dev, data->hw_clks[i]); if (ret) return ret; } - for (i = 0; i < ARRAY_SIZE(cbf_msm8996_clks); i++) { - ret = devm_clk_register_regmap(dev, cbf_msm8996_clks[i]); + for (i = 0; i < data->nr_clks; i++) { + ret = devm_clk_register_regmap(dev, data->clks[i]); if (ret) return ret; } - ret = devm_clk_notifier_register(dev, cbf_mux.clkr.hw.clk, &cbf_mux.nb); + ret = devm_clk_notifier_register(dev, data->cbf_mux->clkr.hw.clk, &data->cbf_mux->nb); if (ret) return ret; - ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &cbf_mux.clkr.hw); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &data->cbf_mux->clkr.hw); if (ret) return ret; - return qcom_msm8996_cbf_icc_register(pdev, &cbf_mux.clkr.hw); + return qcom_msm8996_cbf_icc_register(pdev, &data->cbf_mux->clkr.hw); } static int qcom_msm8996_cbf_remove(struct platform_device *pdev) @@ -340,7 +430,8 @@ static int qcom_msm8996_cbf_remove(struct platform_device *pdev) } static const struct of_device_id qcom_msm8996_cbf_match_table[] = { - { .compatible = "qcom,msm8996-cbf" }, + { .compatible = "qcom,msm8996-cbf", .data = &cbf_msm8996_match_data }, + { .compatible = "qcom,msm8996pro-cbf", .data = &cbf_msm8996pro_match_data }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, qcom_msm8996_cbf_match_table);