From patchwork Wed May 3 01:19:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 89529 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1007819vqo; Tue, 2 May 2023 18:26:27 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6lmL/I25Y8qIq+/lRP6Tbo72Cxve2FPAWAnRn+4IoPl60y1WqhqhOBY7nG+p3CZBzWBx5f X-Received: by 2002:a05:6a20:8e0b:b0:f3:756e:e116 with SMTP id y11-20020a056a208e0b00b000f3756ee116mr25369755pzj.38.1683077187314; Tue, 02 May 2023 18:26:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683077187; cv=none; d=google.com; s=arc-20160816; b=H820yv/17UVFXAY1lROQpADfimDObdmjmWWamCyAEuK7cGxF0LsJzO7CHYo73qAz0I 17N1uPuyMuSRrRipweUQfxLk+YKzw8n/+vccwt8pOVl+QGierymLRnqNUzorftSsxSii lXo+7ye7xLOnNEH4biSoU03Y1DP4j3oManb5QTplC6dsfoEQbf94Ztx8IXrTVmuDazbT tG4Xtv2gzcQhY3cit793E/qOKzuTpcfR3m7/QQ9O2jIxiUstEcfS8ZD53IczocUFBXPi 8T+YUYIhUeBEVprjGR/CR+ITq/Lx7wdoytP3ofFoNkZ3xcaJstmfogAsybuKJBa6J3Ux qPEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=++vq3grPoz9MeaQo1ceDEHmqSkkTASiWLja7R0S6tGQ=; b=boVPsMADiE4r9zaAwGjeA+y6XwfP5heajQpoykMLn4aMMBKQ5qkv9LAu6b9svGDB8b PnapPUnLKfiGWJ9IlxjyJ6iA29MBB4UeYNMlWf+SgZ/xCoFyouDLYA8gAY8Qbv43E7G+ I4W+Sebo0H2AGfVpgoh6KzqqhMBjzBZ9aTxoJ7SU6dEbDnE6iIALKSlpwZ5OFgpgS2w5 KqeTpUDExBKAazUx3AxHKIEhIUexiznV9q2ymd8+YteuzpJq58IL0wFC5R1umOb5vBAg nF+StsXJMAHOSIHq0UUNhHTQ9mEA86rpUGm7saYXD93zMHRw0gZIWhGrx9hzbCwZ5XZo DSfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=COX7K+Je; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p20-20020a63f454000000b0050fa04005e6si32086286pgk.412.2023.05.02.18.26.13; Tue, 02 May 2023 18:26:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=COX7K+Je; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229586AbjECBTw (ORCPT + 99 others); Tue, 2 May 2023 21:19:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229455AbjECBTu (ORCPT ); Tue, 2 May 2023 21:19:50 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD3A730CA; Tue, 2 May 2023 18:19:44 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3430uCMi019769; Wed, 3 May 2023 01:19:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=++vq3grPoz9MeaQo1ceDEHmqSkkTASiWLja7R0S6tGQ=; b=COX7K+JeE/hUMDVyD10/idDK3zFRgEsF9UU956WEpzyB6N5QEDHg1GqyMKiohNIfctHg OP5f6LAJnQ7H4Sx8kkouYN5NERksGT0ARhDPj0sfPoGwxRHbEHgOSULtxJgxSMQLxJg7 VO40cszRIZphjEL66oF+f40cCP5MZoVbFXZKsLjsTZNaMS/FiFLSUm5gKOx6vOTpzWnB /ldbBeD2X4bmtaMfnsOqUdOcLWBMhej4Lq+faU3pFkriamU90Yk5zc8kFd82dJrRiIOT ucxigSaF///YmOlG/Le3hOjiYfIU5+lRjOERfoye011cnplBTzZhsU+fa8y+TakuiDHz Ng== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qawama7fm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 03 May 2023 01:19:37 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3431JaPu025044 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 May 2023 01:19:36 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 2 May 2023 18:19:36 -0700 From: Jessica Zhang Date: Tue, 2 May 2023 18:19:12 -0700 Subject: [PATCH 1/4] drm/msm/dsi: Adjust pclk rate for compression MIME-Version: 1.0 Message-ID: <20230405-add-dsc-support-v1-1-6bc6f03ae735@quicinc.com> References: <20230405-add-dsc-support-v1-0-6bc6f03ae735@quicinc.com> In-Reply-To: <20230405-add-dsc-support-v1-0-6bc6f03ae735@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten CC: Konrad Dybcio , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683076775; l=2523; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=+nd3fKUDQE67UnP1gKxYdD/NiOvH3OI/CjTl6hloB/Q=; b=MXf+vGjMBODVmlI7EvaeiZBOM2KnDFUp5puLc8L9kUwc7jbmOl2sCuI/yMb/ZKes/dZhn8O6l EojpciWfDanDQSDY5/8G2CwMVDvVCw/ABGxgAukcrBBBG/QduWE15dZ X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: qyDk2NkvJMNWOp5O8OALQGftLPI8QYc0 X-Proofpoint-GUID: qyDk2NkvJMNWOp5O8OALQGftLPI8QYc0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-02_14,2023-04-27_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 mlxscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 suspectscore=0 adultscore=0 bulkscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305030009 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764834344531064154?= X-GMAIL-MSGID: =?utf-8?q?1764834344531064154?= Divide the pclk rate by the compression ratio when DSC is enabled Signed-off-by: Jessica Zhang Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/dsi/dsi_host.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 43a5ec33eee8..35c69dbe5f6f 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -561,7 +561,8 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->byte_clk); } -static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, bool is_bonded_dsi) +static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, + struct drm_dsc_config *dsc, bool is_bonded_dsi) { unsigned long pclk_rate; @@ -576,6 +577,11 @@ static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, bool if (is_bonded_dsi) pclk_rate /= 2; + /* If DSC is enabled, divide pclk by compression ratio */ + if (dsc) + pclk_rate = DIV_ROUND_UP(pclk_rate, + dsc->bits_per_component * 3 / msm_dsc_get_bpp_int(dsc)); + return pclk_rate; } @@ -585,7 +591,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d struct msm_dsi_host *msm_host = to_msm_dsi_host(host); u8 lanes = msm_host->lanes; u32 bpp = dsi_get_bpp(msm_host->format); - unsigned long pclk_rate = dsi_get_pclk_rate(mode, is_bonded_dsi); + unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); u64 pclk_bpp = (u64)pclk_rate * bpp; if (lanes == 0) { @@ -604,7 +610,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) { - msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi); + msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, msm_host->mode); @@ -634,7 +640,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) dsi_calc_pclk(msm_host, is_bonded_dsi); - pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp; + pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi) * bpp; do_div(pclk_bpp, 8); msm_host->src_clk_rate = pclk_bpp; From patchwork Wed May 3 01:19:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 89530 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1007852vqo; Tue, 2 May 2023 18:26:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7ILgKiI/x8Szo4iaZpmJ63RzmlTcQRpB7WXfhdy4DhIlkU3JuZ6TIDgGkl/bH2dULbIa0f X-Received: by 2002:a17:902:8bc1:b0:1ab:1355:1a45 with SMTP id r1-20020a1709028bc100b001ab13551a45mr436473plo.30.1683077197877; Tue, 02 May 2023 18:26:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683077197; cv=none; d=google.com; s=arc-20160816; b=IHS8X+u7XWzjsspxYI99fcRwjIpCxHY5GX/9V35lYtmO/uRjk2Zs5pQpPdlEo5liDb WmlRL0om+9f2O2sHtlghxIP9Kn4sRqKJxEM0wKKWnTUutMaSjpzIFbR+NDmVDUfroCdE pIVJad3WwIk0EYP/pjiswis70q/PZjOr76Nmo/yIUTSFb8rCJNjZSHwvO9li2v3h9yzU 3eRA2mAnZCJ0DLknfEJXXe1yk6W1Qa300PZnUDEaXjEki5U96yRKBpeQyuMErth3/yPB hyVEEsCTBm1gnvLIvvAq9WVRcr3/+FgiMhUbNNYG3GYyupqwBVq4JTrmAluFd4g6HN+v jFUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=LtM6s7Lrstdtx1MusfgnMv3PxZUc28iuLAVm8ZI+9dY=; b=OjEdGCEI/khq4JqTpf5TG+Gyd9fCry61mqpHPM/JlZvi6lCY1gxVXag7+MbXAj5pDn piIAd+riMbdUh8oTYF9ow/b0TPYR5pfXm05dgIRNILVptx+VxSL+eaUsgEKlA2GGG0dQ mP8OgatMF2hmr/bD1Aj36cYVbolcEyT4ePWYPdNH8KrDF2a0dT1LJK+e1qnykuHFdjmZ Jdfhicd6lhRQrZ1IUJLz+4m5UTHBwtv1yV1mosowDdPyTxEZfeJjRFCFCY+lZOEXJcBR MtfuwDPrdcLrJl9uhlH8lsS68Ijy/Eme1Cx8O3qXfOaY8wGjx4bIKmvCSdk34h4y0eD8 ZYGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=aGOmRe0L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s5-20020a170902ea0500b001ab0c4174d7si2858227plg.646.2023.05.02.18.26.25; Tue, 02 May 2023 18:26:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=aGOmRe0L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229609AbjECBT4 (ORCPT + 99 others); Tue, 2 May 2023 21:19:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229573AbjECBTu (ORCPT ); Tue, 2 May 2023 21:19:50 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE5F230DD; Tue, 2 May 2023 18:19:44 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3430noKq020830; Wed, 3 May 2023 01:19:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=LtM6s7Lrstdtx1MusfgnMv3PxZUc28iuLAVm8ZI+9dY=; b=aGOmRe0LFwAGzgS2F+LUD6EcTUYldtAE+5v5tkNRdtFK20Q+qPZkdoiErB6nVMRz1z09 zAMRNWAFpkCucCuCbyPVI+mocnd0lfkbX52RHUk6r25wIOBgIBpS5huS7kWeFpXyOlYr IkU5HReCuI7V+LGsmYtjl+jVcHf69BgNfXsLw7c9s7Bj4geaLpHNeWY66TI5X+ekeumr M4rXi14nihZYm/xb6TrQpTNy62Y2GKgNjgz5gL+fZKwjkGGOk3Asq2ZpPUEzuKwcFR14 ToHg8eaIIe6C0FM/wMEPYU4omz1BKog7wxn64wZqZrYeOZyu5rrAFa+jrCbiEdPXT8w/ fg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qawak29g4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 03 May 2023 01:19:37 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3431Jabb030207 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 May 2023 01:19:36 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 2 May 2023 18:19:36 -0700 From: Jessica Zhang Date: Tue, 2 May 2023 18:19:13 -0700 Subject: [PATCH 2/4] drm/msm/dsi: Fix compressed word count calculation MIME-Version: 1.0 Message-ID: <20230405-add-dsc-support-v1-2-6bc6f03ae735@quicinc.com> References: <20230405-add-dsc-support-v1-0-6bc6f03ae735@quicinc.com> In-Reply-To: <20230405-add-dsc-support-v1-0-6bc6f03ae735@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten CC: Konrad Dybcio , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683076776; l=1759; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=lkEVFOv91fpXtzkXbOv4q+pszclzbtiApLWiP0WoyC8=; b=VrvjNQx/vcaxctv3YaicuRUja5QhBfLiOfgl5JY6qZah8L7R1Rkv0thYQ6zGZDn393CQ8sH5o IKzK7SziSuOCA8/GFgL9phdRBPlAqzrAuiwkasEDYvbDOKQUQTIvbpg X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fxhHL7j_Hs39RGzm80XAHZIXerGrQ-BV X-Proofpoint-ORIG-GUID: fxhHL7j_Hs39RGzm80XAHZIXerGrQ-BV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-02_14,2023-04-27_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 phishscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305030009 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764834355834551433?= X-GMAIL-MSGID: =?utf-8?q?1764834355834551433?= Currently, word count is calculated using slice_count. This is incorrect as downstream uses slice per packet, which is different from slice_count. Slice count represents the number of soft slices per interface, and its value will not always match that of slice per packet. For example, it is possible to have cases where there are multiple soft slices per interface but the panel specifies only one slice per packet. Thus, use the default value of one slice per packet and remove slice_count from the word count calculation. Fixes: bc6b6ff8135c ("drm/msm/dsi: Use DSC slice(s) packet size to compute word count") Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 35c69dbe5f6f..b0d448ffb078 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -996,7 +996,14 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) if (!msm_host->dsc) wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; else - wc = msm_host->dsc->slice_chunk_size * msm_host->dsc->slice_count + 1; + /* + * When DSC is enabled, WC = slice_chunk_size * slice_per_packet + 1. + * Currently, the driver only supports default value of slice_per_packet = 1 + * + * TODO: Expand drm_panel struct to hold slice_per_packet info + * and adjust DSC math to account for slice_per_packet. + */ + wc = msm_host->dsc->slice_chunk_size + 1; dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | From patchwork Wed May 3 01:19:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 89532 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1008765vqo; Tue, 2 May 2023 18:29:48 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7DJl0b4AtjaaHpZWR5Rwfj70UUtqIsKFk899vS2r1HfxvWLJcewfJOOtZj+ei6voCRWEQN X-Received: by 2002:a05:6a21:3a97:b0:f0:ec12:7bdf with SMTP id zv23-20020a056a213a9700b000f0ec127bdfmr20023260pzb.32.1683077387962; Tue, 02 May 2023 18:29:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683077387; cv=none; d=google.com; s=arc-20160816; b=pfRnXGzsHkrZWUG0pgV3ckZhKQ6Nmb+luEC5uovYwoa40gpQRqqIpBMNDXxNs/miV6 PopoCDCO60AFMt/YKhXsIJ4eFWs+Ty68fNaN6wqMFHwF4B8ew3HM99HmHHeNUY3wXQBC mRU43PywuFPi+TVr9dik9bJGwRqVRt3rama7caKY1haUGt4ZcGl3GYZvXcWyQDgioLdg +5nFiK9gnjn26NygC+djbyIwitBAdBRCi5RTYpLjruYVtlXsnVNKK0xehl1t2yoqLsxh CidxZO/rLd3Cc0t1F6pVfh5107U8Dxe67GWALH7g0b+4is7RhQtBMdjo3KSOo29JXlBu /uNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=OF2VnFdhujCmFeGKI2HLEe3SKiyrivuVS+bVyj+o/To=; b=UO2rLEWFphZfViHQIjMsEOirCKz2UJJDu+vW4IYGNCORCf/QLVD8Yf1p0NtsXk06p3 rcXjBMqpMe1UJ3imI3VrPVTCNRlP/DZx0bzMTNUpE3SjCVP8smtMG+QIf/Brf4HQ0nwp 6nGqqJkz0yj+DHf8pKDbMV4xOfmRcJ2DjNG52w1YUlmr+t6BkCjY1g6AQQTbPhIcumef KqFotC8xOHFCnoI/qdF/p+tw5Y6vmSWoqpFTXZIVLTlSqNoeTwOwGdgte9UUOZ4iMS+p /ZNtVeSw40Xi8/Jlp+k2DspM+QMpnr/6zzy21En6VeX7uGq8Qt7pki6ZosGYCFdhQmZ+ stMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=RPFcXOKo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v202-20020a6361d3000000b00519d4818029si31919774pgb.152.2023.05.02.18.29.30; Tue, 02 May 2023 18:29:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=RPFcXOKo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229636AbjECBUE (ORCPT + 99 others); Tue, 2 May 2023 21:20:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229584AbjECBTw (ORCPT ); Tue, 2 May 2023 21:19:52 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34DD5358E; Tue, 2 May 2023 18:19:45 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3430bCdE010835; Wed, 3 May 2023 01:19:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=OF2VnFdhujCmFeGKI2HLEe3SKiyrivuVS+bVyj+o/To=; b=RPFcXOKoPD7c3+aqIQeh+XFFMey51GxhWzyi0n/T08wSR/3AHIEdT1HeWetGLrwiFdM4 43yU2huxdz3MSrK9suOgNW2hE0b94lStRLz/cy6XOsGkaEZAXAJO9sjO1+chzAkmq0em NwE0ShVYGrQi+3bIyj0C2tCJLJz0j0wQgIgvpwkcyVBJgxmhWY5+fNgwJCU0rjdaRnKU Ka5ANiW5jx/hNPTVZC3CoZzosycCFxPJRBp8PRo3eGopKqSDBuQ8OSeZfDrqFx8FKUnb hYHo5ZnqK09A9EH6js5hF+3wod7ey5k9PNkJNbh4q4pB61R3ycGEO/3c53SUv8TETTcY vg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qawcta91u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 03 May 2023 01:19:37 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3431JbAt030947 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 May 2023 01:19:37 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 2 May 2023 18:19:36 -0700 From: Jessica Zhang Date: Tue, 2 May 2023 18:19:14 -0700 Subject: [PATCH 3/4] drm/msm/dpu: Add has_data_compress to dpu_caps MIME-Version: 1.0 Message-ID: <20230405-add-dsc-support-v1-3-6bc6f03ae735@quicinc.com> References: <20230405-add-dsc-support-v1-0-6bc6f03ae735@quicinc.com> In-Reply-To: <20230405-add-dsc-support-v1-0-6bc6f03ae735@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten CC: Konrad Dybcio , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683076776; l=4545; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=EyX2HzVpF+s4qNGJ4/Ak1aWEbr+vHD9TC8TKXecgFpk=; b=oku0BFAA/Zgs0lcXAVjTY8m6C9g+nzbJHSmVdF9irFDROflHUBieYaoJhMvtlqjZE1xQ7tofZ gZ8kgPYJ5B7ADn4XEgZELEBWanTF+0n69oG+dt2hAzX2Z5cW37Tsx5k X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DemErI50akr63HF1reAwx-2cIhLVzVyt X-Proofpoint-GUID: DemErI50akr63HF1reAwx-2cIhLVzVyt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-02_14,2023-04-27_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 phishscore=0 adultscore=0 mlxlogscore=764 impostorscore=0 malwarescore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305030009 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764834555128529287?= X-GMAIL-MSGID: =?utf-8?q?1764834555128529287?= Add data_compress feature to DPU HW catalog. In DPU 7.x and later, there is a DATA_COMPRESS register that must be set within the DPU INTF block for DSC to work. As core_rev (and related macros) was removed from the dpu_kms struct, the most straightforward way to indicate the presence of this register would be to have a flag in dpu_caps. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ 6 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index f98c2a5b0e87..4160a35ff20f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_data_compress = true, .max_linewidth = 4096, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 3fd0498ab420..23230841a0d1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = { .qseed_type = DPU_SSPP_SCALER_QSEED4, .has_dim_layer = true, .has_idle_pc = true, + .has_data_compress = true, .max_linewidth = 2400, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index ce583eb14b06..c990406e4bca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_data_compress = true, .max_linewidth = 5120, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 3950e7b946a5..7094640e2fbf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -15,6 +15,7 @@ static const struct dpu_caps sm8450_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_data_compress = true, .max_linewidth = 5120, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 1b3f5424aea8..970049559e02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_data_compress = true, .max_linewidth = 5120, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index b410a85c109c..c5bbd4ad6da8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -380,6 +380,7 @@ struct dpu_rotation_cfg { * @has_dim_layer dim layer feature status * @has_idle_pc indicate if idle power collapse feature is supported * @has_3d_merge indicate if 3D merge is supported + * @has_data_compress indicate if data compression is supported * @max_linewidth max linewidth for sspp * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes * @max_hdeci_exp max horizontal decimation supported (max is 2^value) @@ -393,6 +394,7 @@ struct dpu_caps { bool has_dim_layer; bool has_idle_pc; bool has_3d_merge; + bool has_data_compress; /* SSPP limits */ u32 max_linewidth; u32 pixel_ram_size; From patchwork Wed May 3 01:19:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 89531 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1008738vqo; Tue, 2 May 2023 18:29:43 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5MGpR8s8haKXWpleUF4dNJwUYYdsFHd9+Z/jWd85FAfYZG23Qx5aVJWChV454rj1lplsD4 X-Received: by 2002:a17:90a:318c:b0:24e:1f5:2e05 with SMTP id j12-20020a17090a318c00b0024e01f52e05mr8674189pjb.13.1683077383390; Tue, 02 May 2023 18:29:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683077383; cv=none; d=google.com; s=arc-20160816; b=L5qyIrw9UnbRQrrkR8VB3cS8NngsJeCc5z2Cgb9iC0pt5SoYyZG1gl+pv3B/TJ13m5 fxMtI128Jl7+jr+8Rozz8D6SZZU1FwkIXmRn1Ffk+CBpGQJgHDZjFlZ4mlu1yY5z7QYF vjqXV6yt9n5k6LAbxuFV/GCxCefP5rvU+rNzGVvqtmBljh/LY5tbvTNYDyaewDu4lXX7 NnLuRkNGuV5hpYvvncIHseORMCJ7GeeaJMH39CQk9vgkH1Q9eKwOjIJQFewQuWpqNuxe t/+ULdTBmJUKhsAxjrVMyoKoaK4jolvG3HU3ZTjiWvnq/RwqKQKc0BEmm0Al2i/sE6sc NSiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=Dlmi8ttPHa718tsyDxsZ9LTXyy4isTwomG9XccKgjh4=; b=bPvkx7kNqwIPHf88rJ/hWwCQfEAQqMyxwMSpztvVx8+BRYyj+pmbkISoMOgL5oTB2Q Xfgyd1empXS5cgWGJIM/n7V0QdlHmGFxoL6QVl0GmVNsuVc6B3kyMzJYgPCXyHbqo2TY JNrkzW44+kfkulkcPWN7Jdemf1DgrfkZ0zTFkvc6/brwOUI2yHjNnPYMsDwfLjeY6pfa I5NX9zMUoHZIGGUi9cV6ErNdbKvfezn7XDjNR7crMFQc+9XkLroiYLTOen5CxAraFurv 3okJSQBQv+2XRo80/6ozfSVOLult3cXnHxBClD67wRrKizmzYs6q7bHVzvXd6YyvhLwc 2xVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=a0EF+q6g; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bb11-20020a17090b008b00b0024711d63febsi325475pjb.173.2023.05.02.18.29.30; Tue, 02 May 2023 18:29:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=a0EF+q6g; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229629AbjECBUA (ORCPT + 99 others); Tue, 2 May 2023 21:20:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229585AbjECBTw (ORCPT ); Tue, 2 May 2023 21:19:52 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE16130D8; Tue, 2 May 2023 18:19:44 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 342Nr23H011168; Wed, 3 May 2023 01:19:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=Dlmi8ttPHa718tsyDxsZ9LTXyy4isTwomG9XccKgjh4=; b=a0EF+q6ghnEW2wqzDOk74pvUJ+yyf67C0aOITj9PNvuqWEPHrbDXYl09S+7YTVlFVJTd Nq49EGESycgawNWrPYEC+x9h0HVM/68WUjRkmv2FSdgFESC2/gajTY5ANa+G6ZPgkOYB v3aomaf8l9GnzcnYQQJ4NjC66FnOMWT6F7cE2bo/vod/zJcRjOPNbskMKNYQFdf5BLh6 Rtvwq2HhVDCz45nbSlKZJ+sFmW4navSyoevfXR2aydu6fnQb61mxBdKNzdmGmTdas55h xvKSMUWS5nyq3Xzu2rGCEUqBuqeltbqrQG1dCHX8KxAoVIKn56o4ouNRQb+DsaPO4it7 uA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qawcba8tp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 03 May 2023 01:19:38 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3431Jb2w031354 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 May 2023 01:19:37 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 2 May 2023 18:19:37 -0700 From: Jessica Zhang Date: Tue, 2 May 2023 18:19:15 -0700 Subject: [PATCH 4/4] drm/msm/dpu: Enable compression for command mode MIME-Version: 1.0 Message-ID: <20230405-add-dsc-support-v1-4-6bc6f03ae735@quicinc.com> References: <20230405-add-dsc-support-v1-0-6bc6f03ae735@quicinc.com> In-Reply-To: <20230405-add-dsc-support-v1-0-6bc6f03ae735@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten CC: Konrad Dybcio , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683076776; l=3059; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=1DC1vTomN+IXwi1E2dJXxXSzLYYrRpXHpSX0sGbldnM=; b=Axt9D/WCcOGuDEy3U0pLwgGzdTpCAa7OSRnnksppvSDf6HxuC2AWQOCffZBtJc0sUgWadZbHH ym/MK2rPNYUBfWgTfRpnKFXcqSdHXjY0MO+gS7I81XLdBhUznDiBstN X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Id7_C3Ad-e5NQfNqn12_x1B9fTFvyWY- X-Proofpoint-ORIG-GUID: Id7_C3Ad-e5NQfNqn12_x1B9fTFvyWY- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-02_14,2023-04-27_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 mlxscore=0 bulkscore=0 adultscore=0 mlxlogscore=893 impostorscore=0 priorityscore=1501 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305030009 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764834550267329122?= X-GMAIL-MSGID: =?utf-8?q?1764834550267329122?= Add a dpu_hw_intf op to enable data compression. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 +++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 ++ 3 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 74470d068622..4321a1aba17f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -72,6 +72,10 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( phys_enc->hw_intf, true, phys_enc->hw_pp->idx); + + if (phys_enc->dpu_kms->catalog->caps->has_data_compress && + phys_enc->hw_intf->ops.enable_compression) + phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf); } static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 671048a78801..4ce7ffdd7a05 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -64,10 +64,16 @@ #define INTF_CFG2_DATABUS_WIDEN BIT(0) #define INTF_CFG2_DATA_HCTL_EN BIT(4) +#define INTF_CFG2_DCE_DATA_COMPRESS BIT(12) #define INTF_MISR_CTRL 0x180 #define INTF_MISR_SIGNATURE 0x184 +static inline void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx) +{ + DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, INTF_CFG2_DCE_DATA_COMPRESS); +} + static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, const struct intf_timing_params *p, const struct dpu_format *fmt) @@ -325,6 +331,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; ops->setup_misr = dpu_hw_intf_setup_misr; ops->collect_misr = dpu_hw_intf_collect_misr; + ops->enable_compression = dpu_hw_intf_enable_compression; } struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 102c4f0e812b..99528c735368 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -60,6 +60,7 @@ struct intf_status { * feed pixels to this interface * @setup_misr: enable/disable MISR * @collect_misr: read MISR signature + * @enable_compression: Enable data compression */ struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, @@ -82,6 +83,7 @@ struct dpu_hw_intf_ops { const enum dpu_pingpong pp); void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count); int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value); + void (*enable_compression)(struct dpu_hw_intf *intf); }; struct dpu_hw_intf {