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[58.96.106.158]) by smtp.gmail.com with ESMTPSA id jj21-20020a170903049500b001a69e002c7esm20339486plb.178.2023.05.02.17.00.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 May 2023 17:00:10 -0700 (PDT) Received: by squeak.grove.modra.org (Postfix, from userid 1000) id 0BE801142C0E; Wed, 3 May 2023 09:30:08 +0930 (ACST) Date: Wed, 3 May 2023 09:30:08 +0930 To: binutils@sourceware.org Subject: _bfd_mips_elf_lo16_reloc vallo comment Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-3034.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alan Modra via Binutils From: Alan Modra Reply-To: Alan Modra Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764828929353444229?= X-GMAIL-MSGID: =?utf-8?q?1764828929353444229?= This explains exactly why the high reloc adjustment is as it is, replacing the rather nebulous existing comment. I've also changed the expression from (lo+0x8000)&0xffff to (lo&0xffff)^0x8000 which better matches part of the standard 16-bit sign extension (resulting in exactly the same value), and hoisted the calculation out of the loop. * elfxx-mips.c (_bfd_mips_elf_lo16_reloc): Expand vallo comment. Hoist calculation out of loop. diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index c9cd2f8099f..49355a42f7d 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -2624,7 +2624,21 @@ _bfd_mips_elf_lo16_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol, _bfd_mips_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, false, location); - vallo = bfd_get_32 (abfd, location); + /* The high 16 bits of the addend are stored in the high insn, the + low 16 bits in the low insn, but there is a catch: You can't + just concatenate the high and low parts. The high part of the + addend is adjusted for the fact that the low part is sign + extended. For example, an addend of 0x38000 would have 0x0004 in + the high part and 0x8000 (=0xff..f8000) in the low part. + To extract the actual addend, calculate (a) + ((hi & 0xffff) << 16) + ((lo & 0xffff) ^ 0x8000) - 0x8000. + We will be applying (symbol + addend) & 0xffff to the low insn, + and we want to apply (b) (symbol + addend + 0x8000) >> 16 to the + high insn (the +0x8000 adjusting for when the applied low part is + negative). Substituting (a) into (b) and recognising that + (hi & 0xffff) is already in the high insn gives a high part + addend adjustment of (lo & 0xffff) ^ 0x8000. */ + vallo = (bfd_get_32 (abfd, location) & 0xffff) ^ 0x8000; _bfd_mips_elf_reloc_shuffle (abfd, reloc_entry->howto->type, false, location); @@ -2648,9 +2662,7 @@ _bfd_mips_elf_lo16_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol, else if (hi->rel.howto->type == R_MICROMIPS_GOT16) hi->rel.howto = MIPS_ELF_RTYPE_TO_HOWTO (abfd, R_MICROMIPS_HI16, false); - /* VALLO is a signed 16-bit number. Bias it by 0x8000 so that any - carry or borrow will induce a change of +1 or -1 in the high part. */ - hi->rel.addend += (vallo + 0x8000) & 0xffff; + hi->rel.addend += vallo; ret = _bfd_mips_elf_generic_reloc (abfd, &hi->rel, symbol, hi->data, hi->input_section, output_bfd,