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Tue, 2 May 2023 08:53:37 -0500 From: Michal Simek To: , , , CC: Varalaxmi Bingi , Krzysztof Kozlowski , Rob Herring , , Subject: [PATCH] ARM: zynq: dts: Setting default i2c clock frequency to 400kHz Date: Tue, 2 May 2023 15:53:35 +0200 Message-ID: <4dde5d1eb8e4572dae4295a19a4c83002a58e5da.1683035611.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT012:EE_|SA1PR12MB7412:EE_ X-MS-Office365-Filtering-Correlation-Id: 28531aad-25d5-46ac-a0b7-08db4b14ac0f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IU1KmrWyh3y1mn9IJyR1QOeEQusnU6x9TfqMv6pGY5WFMqW+f87YaIsXh+NolI/AhLug2G9y6sH9/4p39V8b1cleCZPH2HYezZFKx+HI1VwJJelFcTWCBkEo+GTUoHmxz4i/EK4QW6uQbHGednzG7vIUVZ1gW5x7gYr0Zr94y3t7276HYSExE3UjaauMxot1YzzukZxTOvbGP6VGkV9K3z9vNeX5VIfUQ/C8g4nVlNitaven16N38IiTPkSg6E0+fxo/7gv8PryXkoSU8Y+WRyRqv4Hlq35ngZg5fk/4jX45FTtHuf4cbOAvoREMFfGwEbLnb2x7aCQkf7X30iUcog/vdWn++Kl7kSynYbNGBk6ZipOMOUj5N0QRWnMQggMVlkEXJDjI6+JttUS4u1JFTHJoBkzmpKM7ZKpqCtwkzEJe4bXyqZjb4V9Vk0u4FynIf4hWCFn1gjlj7+dhMSq5hUz1QEZSfyK98fiGTPo9E16QZq+ifnqNVrTEw8UslHQrLeXzuIVPA2m17jVe0l7po5/SM70y6ksUjVPka0EHZFrQ3JTfnUIzzN4Lz3pCh5jw780fSbBhpHaaiBPBVrsyX8IVzVkEor6WIxjsunjFDZ+5QDDCLXJth2FNucn5QwiJAYeaA1rtpe3jfsJXQHb7S21eMOEbAEKMdCHNM4BYkk2c278lgBXy9fLlqSk3IvJIH08NSPefpkMutaocy4ICgkgG+uY288NZ3f7H89zEvCqgOpRQbpJrTHv6Hh4iiEdm X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(396003)(346002)(376002)(451199021)(46966006)(40470700004)(36840700001)(426003)(336012)(2616005)(40480700001)(82310400005)(26005)(186003)(16526019)(5660300002)(54906003)(8676002)(316002)(478600001)(110136005)(70206006)(4326008)(70586007)(2906002)(82740400003)(81166007)(41300700001)(356005)(36756003)(86362001)(83380400001)(36860700001)(47076005)(4744005)(44832011)(8936002)(40460700003)(36900700001)(2101003);DIR:OUT;SFP:1101; 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Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi Signed-off-by: Michal Simek Acked-by: Krzysztof Kozlowski --- arch/arm/boot/dts/zynq-7000.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index cd9931f6bcbd..a7db3f3009f2 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -149,6 +149,7 @@ i2c0: i2c@e0004000 { clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; + clock-frequency = <400000>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -160,6 +161,7 @@ i2c1: i2c@e0005000 { clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; + clock-frequency = <400000>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>;