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Tue, 2 May 2023 08:35:58 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , Ashok Reddy Soma , Krzysztof Kozlowski , Laurent Pinchart , Parth Gajjar , "Rob Herring" , Vishal Sagar , , Subject: [PATCH 01/23] arm64: zynqmp: Describe TI phy as ethernet-phy-id Date: Tue, 2 May 2023 15:35:29 +0200 Message-ID: <9eefc40c727928e0c7b794a3a2e061ecf6ea230c.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E638:EE_|SJ0PR12MB8167:EE_ X-MS-Office365-Filtering-Correlation-Id: 5009ebc9-6b32-40b8-3277-08db4b122a82 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rKmO0Mb44MBVcvBlDvYFwqfJ6PCtR7OwQ/IIT2A1lQb2bOkICjnFeKgc2wA2B1J99ivBcUt3kZ7gOb6awXQalTNERTnwyxgZS8E9HRfBzYr2gzX1cNGgt1jOA9DoPmcPYUg19XlxXqw/ZW1sl6Wk/3XRhNaHBQOqrxaBGEBY49D8W1k/MfGPxEkI6l2cYN2mGWXOq8uaEv5JgueW9RdmeJPlMA/BQrNtcHW5jszDbgnxWolw806a2uxV3aBcTW5MIXoiGfIHusxLKOP7M3ci0WYjm9almyBBXaE4jMbJ6ndb51raIaL/SH1cwJNLuXi4Nz/xBa4+GGgBzArokkhrHwA/dOaA59XTZobRzy1NmdvQqKsJ7t+E7yguHxbRI0v7NZmePnmeLtP6qCzSg7JUgudoFokVKOJGGmazx7wGJJ9rAXrwr9FiGy/QYThr0R9tn6TedFS/VR5aEpKwl7b+CKKE43TNn2C1q5KiwXQ1CLygvlNCvt90n64/4i8mxsIhJCK1G/pJbGCahvtcatjXogqaKaaMm/YxCvzPFkPqs2up5CrDW3KCp3LflivV758JUiUMMrClLnZd1KeRVCk7R54Wmf/ki1oOaJr0rTK+V2o7hx5s9mFfZw91JQ4Bsx/OEAq50Tjqh5eDvCBeFEmmyQFTX/WquQfy/xYun1Z2dCbyQR7lZo779qPSVAgMrIH5aa/6jJDWaB0i2lyVq+wPld+pIRvIbRroefnpQT9QztvMoRb+CaIOU1IGpP/Q2Xkd X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199021)(46966006)(36840700001)(40470700004)(2616005)(83380400001)(478600001)(36860700001)(186003)(16526019)(4326008)(54906003)(70586007)(70206006)(110136005)(26005)(47076005)(426003)(6666004)(336012)(44832011)(316002)(8676002)(40460700003)(82740400003)(8936002)(7416002)(5660300002)(356005)(41300700001)(2906002)(40480700001)(81166007)(82310400005)(86362001)(36756003)(36900700001)(2101003);DIR:OUT;SFP:1101; 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Tristate setup can influce PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset. Phy reset is done via gpio. Signed-off-by: Michal Simek --- Checkpatch is reporting issue warning: DT compatible string "ethernet-phy-id2000.a231" appears un-documented but it should be fully aligned with Documentation/devicetree/bindings/net/ethernet-phy.yaml --- .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 23 +++++++++++------ .../boot/dts/xilinx/zynqmp-zcu102-revB.dts | 25 +++++++++++-------- .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 22 ++++++++++------ .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 22 ++++++++++------ .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 22 ++++++++++------ .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 22 ++++++++++------ 6 files changed, 90 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 13c43324f1d2..c193579400cf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -200,13 +201,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@21 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts index f7d718ff116b..00b930f20718 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -16,16 +17,20 @@ / { &gem3 { phy-handle = <&phyc>; - phyc: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + phyc: ethernet-phy@c { + #phy-cells = <0x1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; + /* Cleanup from RevA */ + /delete-node/ ethernet-phy@21; }; - /* Cleanup from RevA */ - /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 485585c491f4..11c1eaef9f53 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -109,12 +110,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 44ec9edd2452..c06c138fa3e5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU104 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -114,12 +115,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 09773b7200f8..52cdec33f190 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU106 * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -212,12 +213,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + reg = <0xc>; + compatible = "ethernet-phy-id2000.a231"; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index e0305dcbb010..699cc9ce7898 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU111 * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -172,12 +173,19 @@ &gem3 { phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; + }; }; }; From patchwork Tue May 2 13:35:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89377 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp629107vqo; Tue, 2 May 2023 06:51:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7XBJL3QwHKi9IxpybRwozbJBOfJ+jME1CdHaXBkGzNuXy1mzezvu0lODYNi4ywXSOCpa2M X-Received: by 2002:a05:6a00:158f:b0:626:2ce1:263c with SMTP id u15-20020a056a00158f00b006262ce1263cmr24823608pfk.5.1683035484047; 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Tue, 2 May 2023 08:36:02 -0500 From: Michal Simek To: , , , CC: Ashok Reddy Soma , Amit Kumar Mahapatra , Andrew Davis , "Geert Uytterhoeven" , Krzysztof Kozlowski , Laurent Pinchart , Parth Gajjar , Piyush Mehta , Rob Herring , Vishal Sagar , , Subject: [PATCH 02/23] arm64: zynqmp: Fix usb node drive strength and slew rate Date: Tue, 2 May 2023 15:35:30 +0200 Message-ID: <1b2914e5e6010b174c14603f92626ac3b11a2263.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E63D:EE_|DM4PR12MB5120:EE_ X-MS-Office365-Filtering-Correlation-Id: f7fdb5ff-be59-4feb-e753-08db4b122ccd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: spABzgjiyC3vU2DXClSDJgrq2zgU1J/GqccKEVztNsZh5wHIw7Fp388Y/1rXka3CZQPuFn/Ifaw+bd9WpM2deIBcltwz7d5W5JsajUAtuYeilEvx6D24oQTegW7kBRZlbceV+sUL7SUk5LRMeQcGqkzkiP+BvhZIU7UuenAp2L0HZSY20YYTrWDj/5H+MQdJR5Nbpi7a3K/MotLZma+nnfqAakCLQaLAub2/rO5ZrAbgDgjiDSTrT+6D0vDqLukLis6Xfx8e4p3swfBKc1moZDHaTYK+DxnxnBzzr1MdQLX1ubJdh6adsEI5PVOzqIRxWc4qx3N+BTIoIJgInIQYBrVrjM/rd76IoD+L7bm+sq+Ca8yFWTYzkounT5Jv8v8tLOVyr2HWz108X/SX4Y1C2siw404LuOQqM+ikDidgerumYTCfzXoht9KVsVCM2Y3DaqPluCQVdLQVr0KB8zSYZqOX+jdeJEg7lpbVuUhc8XE3dfEF0GjHygoWcXLI5wOLJuvJ6dbPhXKyWgSzE80Sr6tIaSknappzWV75m7SuRia0CgfbiaqRNTZPlIFHGFYpBu8gKHGLjJxDYZEqIc6DNsiuZFdoCeMxohOG0pAKR8bhkk23SQDNkFlZQ3M6LdZXqXQ+o1Ds4rNILQi+tOztkV5d1wS0C5KL9Q24GV6NbcOmgw2IkP1bJzKqZOqw8j/shdlJXiSUkS2rMTn5WJRGxYzSkTUatGCXz/SAKRGTirXGUCT9IfxePLiDwgWbmWOQ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199021)(46966006)(40470700004)(36840700001)(54906003)(110136005)(426003)(336012)(26005)(36860700001)(2616005)(6666004)(478600001)(4326008)(316002)(41300700001)(186003)(83380400001)(47076005)(16526019)(70206006)(70586007)(5660300002)(8936002)(7416002)(30864003)(81166007)(82740400003)(40460700003)(2906002)(356005)(44832011)(40480700001)(86362001)(8676002)(36756003)(82310400005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:36:03.5461 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7fdb5ff-be59-4feb-e753-08db4b122ccd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E63D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5120 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790615361261248?= X-GMAIL-MSGID: =?utf-8?q?1764790615361261248?= From: Ashok Reddy Soma As per design, all input/rx pins should have fast slew rate and 12mA drive strength. Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb group pins. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek --- .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 8 ++++++-- .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 8 ++++++-- .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 8 ++++++-- .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 8 ++++++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 13 ++++++++++--- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 6 ++++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 6 ++++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 5 ++++- 10 files changed, 54 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index b610e65e0cdf..2f7a17ec58b4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -2,7 +2,8 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * SD level shifter: * "A" – A01 board un-modified (NXP) @@ -259,19 +260,22 @@ mux { pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; mux { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a52dafbfd59e..4695e0e3714f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -2,7 +2,8 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2020 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -242,19 +243,22 @@ mux { pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; mux { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index f89ef2afcd9e..5fa9604f05d1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -187,19 +188,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 938b76bd0527..a2031187d9b3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015 - 2021, Xilinx, Inc. + * (C) Copyright 2015 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -281,19 +282,22 @@ mux { conf { groups = "usb1_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index c74bc3ff703b..2dd552cf51fb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx ZynqMP ZCU100 revC * - * (C) Copyright 2016 - 2021, Xilinx, Inc. + * (C) Copyright 2016 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek * Nathalie Chan King Choy @@ -423,19 +424,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; @@ -447,19 +451,22 @@ mux { conf { groups = "usb1_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index c193579400cf..78043d9de7cc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -783,19 +783,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 11c1eaef9f53..c1779c88ec34 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -410,20 +410,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; - drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index c06c138fa3e5..b857c1950496 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -422,20 +422,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; - drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 52cdec33f190..e4e09afbdc1a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -794,19 +794,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 699cc9ce7898..791b2ac9fbdb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -660,19 +660,22 @@ mux { conf { groups = "usb0_0_grp"; - slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; + drive-strength = <12>; + slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + drive-strength = <4>; + slew-rate = ; }; }; From patchwork Tue May 2 13:35:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89358 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp621288vqo; Tue, 2 May 2023 06:39:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6P7NIGCPFhvkLHUMy531Nb5zAq7UXFq17l1msTNJbhy3gbXy5lKK+LZiQpxVb/3N8YEPCd X-Received: by 2002:a05:6a00:181e:b0:624:7c9a:c832 with SMTP id y30-20020a056a00181e00b006247c9ac832mr25314813pfa.8.1683034752409; Tue, 02 May 2023 06:39:12 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683034752; cv=pass; d=google.com; s=arc-20160816; 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Tue, 2 May 2023 08:36:05 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , Ashok Reddy Soma , Krzysztof Kozlowski , Laurent Pinchart , Parth Gajjar , "Rob Herring" , Srinivas Neeli , Vishal Sagar , , Subject: [PATCH 03/23] arm64: zynqmp: Set qspi tx-buswidth to 4 Date: Tue, 2 May 2023 15:35:31 +0200 Message-ID: <0cc9dce0330abf3df46252ab63a3930bded23e4b.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E63B:EE_|CY8PR12MB7241:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e61c285-21aa-4de4-9e13-08db4b122f41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZL45kF3MHOfrYF6k03e8RsZtBq19QPfeHIxdISxCW3eEalCpNDvmY99qYHeik0YmQKqbDCxFYz1XlvltBE/4ObU/WPP5l6KL4D9e7/iNDB/Gm/t1KIIoronTnguf2pyI92WamjAv0Sm8mEcRYdF8jrg0FW8+CRhYNUH9Z5bsOxNhx2Fl4Ol/6DRwShT/gvO4TNXKAo5ethPSWJYpgWZSyo+x41uh3dQiABClyc1OxRevSUfj18ZUBDBz7y5hGWti2BycK8de7WhTPx1Bi2/HEoLixWwXL6EVz2j47RvqqLBv02vamW36kR5EXAQnA16S/JdUFOvIVp+c0BbN9RZ+1gpOA854GbZnA3Lci+5IinIRRCPSt0/CiAydTclEj5EsJDebQhh7k688LR6cs6qX2OP/o5UkNEXjb/gnwpmRtRLdsV2ozU/2wvYtNB7qdCWMtKnTw3G0I6BtYQHyv286IM3UlIfIOIYp6PtshXgaAgQ+g2Yd7G0RHp7NyBTknT5hAdSLh1hDtpRnPEVmAROw5yy1Wz8EoeySDMp8DWFulnrSog5+feCk027ZAoE1W4XOUgBwlyTmcag+VmFoC112mMHUaxoHDYvUP5VTfn+xTMCIGy4uA/gncdFa9f2dAYOpSSn5k4DQfww9YCD6TrxVK0GFiuF+kiulqWBURFOKrCyZLzKiElnu4nwxxIKSQ9MWVznY6uzVrMlODzlewjz4MOpj2u+28/FMhMUvW0OAJYCm7C7ujVRPKF1/130VhREd X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(396003)(346002)(136003)(39860400002)(451199021)(46966006)(40470700004)(36840700001)(7416002)(44832011)(36756003)(40480700001)(16526019)(186003)(40460700003)(5660300002)(26005)(2906002)(356005)(86362001)(478600001)(110136005)(54906003)(41300700001)(336012)(426003)(81166007)(70206006)(70586007)(47076005)(82740400003)(316002)(4326008)(83380400001)(82310400005)(8676002)(8936002)(2616005)(36860700001)(6666004)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:36:07.4412 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e61c285-21aa-4de4-9e13-08db4b122f41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E63B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7241 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764789848118030047?= X-GMAIL-MSGID: =?utf-8?q?1764789848118030047?= From: Amit Kumar Mahapatra All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4. This would enable the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 34412304d09f..dcc17e3ea961 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -85,7 +85,7 @@ flash@0 { /* MT25QU512A */ #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index f1598527e5ec..4d301ea0bdcb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -44,7 +44,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 04efa1683eaa..485a7b21157a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -45,7 +45,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts index e971ba8c1418..676b8550a625 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts @@ -47,7 +47,7 @@ &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 5fa9604f05d1..35fe7857459a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -355,7 +355,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 6e0106bf1294..311cb2f81c7b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -173,7 +173,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 78043d9de7cc..5b6403865541 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -957,7 +957,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index c1779c88ec34..a74a2061431a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -444,7 +444,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index b857c1950496..73972d83ed4d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -456,7 +456,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index e4e09afbdc1a..5a54d066db86 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -964,7 +964,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 791b2ac9fbdb..3b37df98700c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -794,7 +794,7 @@ flash@0 { #address-cells = <1>; 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Tue, 2 May 2023 08:36:09 -0500 From: Michal Simek To: , , , CC: Ashok Reddy Soma , Krzysztof Kozlowski , Parth Gajjar , "Rob Herring" , Vishal Sagar , , Subject: [PATCH 04/23] arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 Date: Tue, 2 May 2023 15:35:32 +0200 Message-ID: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E636:EE_|PH7PR12MB6659:EE_ X-MS-Office365-Filtering-Correlation-Id: 7d753b7a-52ae-4b0b-96e4-08db4b12330b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YVXXy8lXskiyM38uWva57ZEY/EHZ3zOMl3ETWPYQMskYuI/AOdVJmkCP8jJp3oQBX8p3/aBIfndbqR4hLtO2d0kYnccA6+yoFcLa3rm0KEyR2Hpk2sehoEzfQB5iQupbisnpkcsEfhn/oNOZ+0NiGeeuzWTnpYFO3U/7lgcd3ClZsMhN6mw8+cMnNWvrtZfxMqoYZPGFEQ5w0v3BSejepH1RVYO0s1p5VwIPbLSXNHyc8EbY3HL+3VZjf55pYUt6HdBCYG0otnREk9l3/6m+w1TULl+cA8YT3fWlZyteomhP5TpuxNWQWRWalenYSZpeHK5QUcleZLLKNc3QWVGuON0pbCj45yIfrKY4OKZyu2SK8rxl6PbxR/nnsNgqa+XsOEWFIxmDpH9TMNNdfaunbw21PMW/TpZ/0fXGkJSZaMqPpFPvLv+xLEjNQVjQDMuwg8j6A11zqrRDIvDAQ1veLS6Oeb6pAIPFhvtr8gQfNOC3Xoj4wwhdT4T7vOhydFP5T498LiiM7N3AUWUuEwoGHXlS+lT/0JnisYZgMs+T/gLb6sUKfs0slhn2Dfg0ovQiluK3XuTM+dcvGsjx0CVqWfwIpICE+JAF6udkLWiAR2i8P85qprNai7WlGaMonEk0EI/0051fVygwR5jF6ptUjxzLc3YuEF8PPxGFoW/Iz3wLEya2Z9GcE9cm697s1wO3MlqIw0j+XnqEcVbBDQAezJcRy3/kwLH2zJIHPnNi9B8wVcJDRQi+12IrPGqv7h4e X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(136003)(396003)(39860400002)(451199021)(46966006)(40470700004)(36840700001)(16526019)(70206006)(70586007)(4326008)(186003)(356005)(316002)(82740400003)(40460700003)(478600001)(82310400005)(110136005)(54906003)(86362001)(36756003)(40480700001)(6666004)(2906002)(36860700001)(26005)(426003)(2616005)(336012)(83380400001)(5660300002)(8676002)(47076005)(44832011)(8936002)(81166007)(41300700001)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:36:14.0167 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d753b7a-52ae-4b0b-96e4-08db4b12330b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E636.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6659 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790565646712102?= X-GMAIL-MSGID: =?utf-8?q?1764790565646712102?= The commit 53ba1b2bdaf7 ("arm64: dts: zynqmp: Add mode-pin GPIO controller DT node") added usb phy reset over bootmode pins by default on usb0 only. zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744 hub which is used only in host mode. Especially this chip requires reset to operate properly that's why better assign gpio reset to usb1 instead of usb0. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 2dd552cf51fb..c99abb99efcb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -552,6 +552,7 @@ &usb0 { pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; + /delete-property/ reset-gpios; }; &dwc3_0 { @@ -567,6 +568,7 @@ &usb1 { pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { From patchwork Tue May 2 13:35:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89371 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp628732vqo; Tue, 2 May 2023 06:50:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6kkM1hvZJ3dFUUnviYKstK5i19WLUHUXB/YLHld8ZUgjxqohjtDvfW1yseVt2WOV5RHWm7 X-Received: by 2002:a17:902:d4c8:b0:1a9:4601:a7c9 with SMTP id o8-20020a170902d4c800b001a94601a7c9mr21746181plg.12.1683035445873; Tue, 02 May 2023 06:50:45 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035445; cv=pass; d=google.com; s=arc-20160816; b=EKDoB9WAPdlLeYbo8VBfL3sj1l8N/C6B9dRmsrTgyrszn0msHsF7/w5VfLzgmQVfp+ OaJieUWDB60gveeJeascf2F1nOHrUSAXT+lcR1SS+Y7Fgth1srWBM5tGohWsAvrEEGrP NE/BDtTAsxcbjsUPJIYCgpNMcNKAQl8w78bNcqDPfnn2KgHmFMA6A0X4zIaPjf3x5+jc 5X0QF2K/z1tzTnbC+4CD1fz9/mqYHALuUU5ukMHXqBBoWd0k74xxwfVeOQDowBXPHXt/ pwcJpZVeDx5lSRp0WECexi4QwlE7Fn+R9W/SrjwTmq5gCf3q2FlcT+0GyYO7mNPOS8bF 9W6g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vuLkITE3e3K/3zPWJ4BQyWtIhiqtVvKTzsxOR9XEff8=; b=y50txc6tghYr86bd/xEFhwPlf2nYSURVVAD4w0J1LajfztjceBIXKIYz2HNOyBjC3X dgQyFhImQynDRGdgabZxkR2eJYcr/TAnXprSrvrIFm6KfpdP3458KM2cSMyeiFnDgeTY Imj0/8ATBxck/kuTY4YeCYANe5KyC1+9G2Ef2iDSlgP8A93hk+TEJGr9mLsNNfGwADb2 U6rOvjF0J5DSNvF5u07ziGiC33TRvfEgyOgFIbLKuetHOi19F33cxwp2N2FJS9W0RIEI eJn39gOiwJp0Vm5VPtbwXRWZLxkl+bqNmTEhwh6WtpWJn3C7QYxWKol0PXP7oZqvNXnP NVDQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=LiIv8WNO; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:36:13 -0500 From: Michal Simek To: , , , CC: Radhey Shyam Pandey , Harini Katakam , Krzysztof Kozlowski , Laurent Pinchart , Mathieu Poirier , Michael Grzeschik , Rob Herring , Robert Hancock , Tanmay Shah , , Subject: [PATCH 05/23] arm64: zynqmp: Add L2 cache nodes Date: Tue, 2 May 2023 15:35:33 +0200 Message-ID: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E636:EE_|SA0PR12MB7075:EE_ X-MS-Office365-Filtering-Correlation-Id: 29505f44-0d7d-4a3e-3a2a-08db4b123433 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: o5FpvT1PT6gk38hELV2/cson+ItdbHeUMuLVvxMxOq+PBxlmqb7CV7LcylP5DIYU74gwNCL46/Pq1xA6+B9VJ5nAwsgpDvOSqHlEAETIavZJ3AYROSFUZ9HQ/jXJBR+KRhfThF4p37QLarP9QqyvefstqS/Qv8HeVwFhBcwoevN5jKl2eJYgdBstpwG47Op1L+5+ef0WBpXNU/UItvJ23o275YQMsFXrBijzZ9I8TV2nLSF4PF1KzqIhn6+4Im5H0UqhQBHsWYde5iT8qMkGgOZhNCJfGpebNfQ3fwIjjQLZByXT53si9a5eTEaP/ZDU04pzAiuBw+D275cw6Ma5wh5s7pCv/nPcIH4FzpHqscR+9yryLt09GcGAwT1Yfs+8svFttn93xb4qyXcUrAKlG6PSE/Fbv+/vrQa9/gEGNHvzURXVziEXOfl4aWdcMtfUfntd+5akejZiWpsYU+VxeaOUXGECaMAa0AO1oGvPICaNgMrVo4/+oKuek54szZCtUZ76wOa0vT8XgiO1mdU0za6caAUNJvJ32MRvFRGwxQA/CpGXLehyqSBz22RRih4fmDhruOYGMyY81/5VYbhyw6Cw2L9MD5RCA9aGMVlq/ww68awECJyStkMq8pKRxPUBAhN1FriV4ycRDklNMcIIn+DRk56SZu5D9QWREWwGG9o5sbDtCZ43JNiMuydA0FbsRz83hL5w3qjn+zMROhd15Q6A1V4NXr32q4wvOaxUnq6ZcreLzq8vGfQ+RXSsauW2 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199021)(46966006)(36840700001)(40470700004)(2616005)(16526019)(86362001)(356005)(4326008)(41300700001)(82740400003)(81166007)(40480700001)(316002)(83380400001)(6666004)(82310400005)(426003)(336012)(47076005)(26005)(186003)(36756003)(54906003)(40460700003)(36860700001)(110136005)(5660300002)(2906002)(70206006)(70586007)(8676002)(478600001)(44832011)(8936002)(7416002)(36900700001)(2101003);DIR:OUT;SFP:1101; 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To fix it add the L2 cache node and let each CPU point to it. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index bb0d0be30aa0..c2d80c7967e9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -33,6 +33,7 @@ cpu0: cpu@0 { operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -42,6 +43,7 @@ cpu1: cpu@1 { reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ cpu2: cpu@2 { reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -60,6 +63,12 @@ cpu3: cpu@3 { reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; }; idle-states { From patchwork Tue May 2 13:35:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89380 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp629595vqo; Tue, 2 May 2023 06:52:09 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5IaFriD03lu3cLV2PW+jL/Ffk4BetDaR6UbjhG0TKB7AEdNqpkf1dPisVPMImWVefzpar0 X-Received: by 2002:a05:6a00:1892:b0:62a:c1fa:b253 with SMTP id x18-20020a056a00189200b0062ac1fab253mr27522306pfh.31.1683035529550; Tue, 02 May 2023 06:52:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035529; cv=pass; d=google.com; s=arc-20160816; b=0NuPKX4a3X3zgsm3JjcV1ba4ipocrKw8rJkI1z/XDX13j6Lr7331l44ynpUtWyy5x8 /R32YPgZLmzoNZOmiCGmHD4p4KAeSvtVXZ2/9uZlBvVAaFRnccLmhrkZdS6DTh19bTqf 4iV+IN0vmmWFYu4E2Uboe1G/6awERZENecKPe1URVrrAqofQVbGYcjIdGwGER4yEOsxp 8OHAURsu8ziqsWWT/fjmoacV9d+hpukE+Q9QUeL3oz6qjTHpQxT2805kK4O9OiJWtao7 vGRS9olmjYfGKrHxr+79b4466hWOfCP2p+cHSxv7xtjaFS5mM4+cgEkmkBatWqTDTPdw yMrg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0XYWvYBsJgFC/Uolu8upj50xk2GLhvkzlH+sSaDQO4c=; b=S0Erv3YyU1XKKp/AeiELoCTjis5/nNrzdDN/ZyJnCN/G523DeNJ2MhdJsqnsKzjWUL LMzEqxvtC4IIL8QsF2H0dQmGeFEK6N0xLP1PtjMqsuyJO7WdzPbTAueupRZnXAihtLnT 4sLokh4O5Bx4InNfdWtQm9L+u/E4T+L0JWFNhRgTNrx1hM7UoxD4EO8WpBsOPi03c09s qUO9xUrl2ZYZXkozf5XAyiGo7OB5VmgR9F1RNzNwB4XAMdGmAIUR+WeUkrGmTKxuU+zc 7e7tC7QIQCllNam/0qqxySwa4yWuYuI0/v8RKajHiusYf8hBUhz0ZGskveAmX9+dQH7k 5CQg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=rMa9MyG2; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Michal Simek Reviewed-by: Laurent Pinchart --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index c2d80c7967e9..61c7045eb992 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -135,7 +135,7 @@ zynqmp_ipi: zynqmp_ipi { #size-cells = <2>; ranges; - ipi_mailbox_pmu1: mailbox@ff990400 { + ipi_mailbox_pmu1: mailbox@ff9905c0 { reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, From patchwork Tue May 2 13:35:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89359 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp621415vqo; Tue, 2 May 2023 06:39:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5zL6VKFhPNnnDGsSUGpaH1X5cJuanp6lYai6pQomH6Duv4LNwU4unDIxVfn5IikRChM/d4 X-Received: by 2002:a17:902:d4c7:b0:1a6:dc3b:9ed2 with SMTP id o7-20020a170902d4c700b001a6dc3b9ed2mr21060441plg.13.1683034762854; Tue, 02 May 2023 06:39:22 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683034762; cv=pass; d=google.com; s=arc-20160816; b=cyf6/8nmgWb+4yl1WOVGNrX+Q5phyLe8y2HytE5JcPAsAmdvJW/jO5zNTWW8by1zhJ GKgjK3AcC0lsGTaqpleg5gyerddKC0kTy0Hs63c2d7RROo0ySq6u3LCrz80ZU3Cg0xuJ ja/8Stt9XHoBdD0/amm4M9PkHqkJTPD0OhWLC/FdGuv5wd1eDAgISl2jW7IwYqLxUhny JmKV1V3vDXkApObhnjqqHBccYzUmPb2f7bbKe3yI/IsPM3Le6qzJ1ouffUrxr36/ZkJl I3ozhqAcS7U4QpXJ+El9kLbV9pw+Wf0s4sOXbWe0QP4IPFWTsGflaHq7/YvJXu6vE1yF eVSg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FYAxaiUQ3mc3pC3rp6MjVQciGbkJU6x5vjV8dTq/3yU=; b=kSuTq79aoyTHtDpA54D5rTqLy9igYnu4TR8oLjyWLaSQcble+n55QxSXwelqvVEsg8 qygL2rrsaqqj01xFE27ytfgGQSyc3QqsqVuHwTvzjnOyhcydqtHftxwPPKPPHpU8xOX3 IximG4wA4rZZyNpgrGYTZQeoTM6uqlIn6yaZ7tB4nyV10RByJ3wxgs4FxL9ayZ7YDNIW 1rWcpj54Arv017h7+OfTC62pNXQ0NyeDI5r3rCP8Choazp/qyc+3ER1mPuT/FzRvkAMl xCl3A5Idmr8K/8qXzQtCdSsn8QvZYHulAat+z2apzg7Lf5Vo++3EgPHf28EY/RRd3fgP wBLQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=bmqsKSGc; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:36:39 -0500 From: Michal Simek To: , , , CC: Radhey Shyam Pandey , Harini Katakam , Krzysztof Kozlowski , Laurent Pinchart , Parth Gajjar , Piyush Mehta , Rob Herring , Robert Hancock , Tanmay Shah , Vishal Sagar , , Subject: [PATCH 07/23] arm64: zynqmp: Add pmu interrupt-affinity Date: Tue, 2 May 2023 15:35:35 +0200 Message-ID: <4c6674bf7e048e7370248e50ed3d011d604d020e.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E636:EE_|LV3PR12MB9186:EE_ X-MS-Office365-Filtering-Correlation-Id: 97c3760f-735f-4a98-c258-08db4b124331 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jvqZ13gEJ2a4Q88synvCjLMz9XjRr2INvai0quMAWEX1bf+14rGeprEf6ZDb3BlTUhsoWw4BiGHsQSBXe/BqXGDpDo7k4N/KEjppU+18nNt2juzmBAHMdzzafqrWzWBnKgELDRDMaoP/e9Uam9GUuEkhnjhPpCV3dwItdAdA6cdvr2fo9xOGX+5VyVKJRo19Qtxm3lFyPPBUrXm4bNG9eZ2rRIJGvuf4N5RXuL5MgERfTf9eY6RLgHSpDZ5nTGRAn3DFf8rtybGEIQiWfbQZvdU2VdNRln8wnf/wvw8uasB+nXGZuXj2hqgb5/Kf11PPl3F/W9A77+m62+LGffCYBw2w2KOHHRakIrciJ3ctpLHx2j9dzjCOpMLO1OTw88dH6xoa8IJkCHn+CgIUwb9NVX+uGl/5G5ZQdIADQQfBoBKN0DY2YZyi4n3xGCG13hvDCc4a3lhxE+YHvm36YfhcrOmnZXZ4ZSVOEFsXuz5jzf1+CsGSGPf9yTPNsxobMRG4KQqWXt8tJb0D2fz167is6Aic9oTGjQyWU9BGRbdqqVFXh4wr12/tA58ZN1Y7yh02MLYEcJ+U1+8GcA0Hvn2ZPO2dJxoO1t64Enn+GdLkwwAotSwlPYsXx8epRSCd1pz5tFuY7N1T3l616WpTX7/ee5K0N4g26TH8aVHDOIgL1VF68RZ6aIp62Y1B3VW7SN1HWygRh7BBm5gwG0Zf4daOGFzKhZbyrIh5QfB4ItTW3Lalj9SMP3NxltJf3Wu9sw8J X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(396003)(39860400002)(346002)(451199021)(40470700004)(36840700001)(46966006)(26005)(86362001)(6666004)(8676002)(8936002)(40460700003)(5660300002)(4744005)(2906002)(70206006)(70586007)(4326008)(36860700001)(82740400003)(7416002)(81166007)(356005)(41300700001)(44832011)(316002)(16526019)(478600001)(186003)(40480700001)(110136005)(426003)(36756003)(47076005)(336012)(82310400005)(54906003)(2616005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:36:41.1104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97c3760f-735f-4a98-c258-08db4b124331 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E636.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9186 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764789859802187286?= X-GMAIL-MSGID: =?utf-8?q?1764789859802187286?= From: Radhey Shyam Pandey Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot: armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 61c7045eb992..a117294dc890 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -161,6 +161,10 @@ pmu { <0 144 4>, <0 145 4>, <0 146 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; }; psci { From patchwork Tue May 2 13:35:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89360 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp621603vqo; Tue, 2 May 2023 06:39:41 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6+zWB2axvsp5XlF8IKYinU60q8nJM40h7Cx7lhT4GOJ2Cuqp/GOIS1DEY4EeBBndDuItD/ X-Received: by 2002:a17:902:f551:b0:1a9:5674:281c with SMTP id h17-20020a170902f55100b001a95674281cmr21495936plf.23.1683034780551; Tue, 02 May 2023 06:39:40 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683034780; cv=pass; d=google.com; s=arc-20160816; b=YhGc3T4WgdYHMzoHzAQCfqhEgVLGrIDzrgghfoJESpuYcXcMJ74qxx61qlFytvqESE SFJ5oqz9wHeLl/puTXd7Wmu8a0DY2dM2yGtZfdc0EmuUlrV2GQmv7m2zQ/vF7t7C6Exc z5+4DWB7s42oAWdZWCueJTVF4B/UbHx7ElRx3N+x3xl5Nxkvop7+MyzOAxVkpaG9uay7 TBUk6tVakCRCuKC95kDZ6Lt7SUvLFE6SnU3ezJsimTn2R/70Pxekq8XpnBEoFTDYEnYc IwUYVJ7wzVutMJewdUO3Ch+Vdwa+VvT8dRFwtHC8+9BGOU7Vx8q28yMn3CVicJWEsfQL 3Hfw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eHZE6w/ntG770sHjG88RMPMVbPRfBcd+whTzcpKQI94=; b=g3zXbJvoStwdeDEiavmfGtUIXRTlfvmjiqfGcqCyWdx9K8B4HGDrjnepmAb1BAUI/q vS68Ud2UBHnDghWzsIiuo98MK0sXAmif0GePDNPeP80W9BkpCV65XwQKYUbNliOqYf3f TLQoaJJ2x2lvz19r+Ab1fQs6Ca9mN8Z2JTmKRPiKyhpQ4U2IiPDB2uYkW0Roo1uq7dnW wq/v71Dol06aRecBY7fHM9CCLv4hFtirQv/NEAAwtQuqhyNUvMLgr+w3SQKZa/UTG0DF gKtqrATbG0aGpWCgJ93n/QAYak/IKbH4LlsOdExq/dG7c0hpk/tP1VQ9ltr33z5CZTRf oUew== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=cPGaDB5f; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:36:42 -0500 From: Michal Simek To: , , , CC: Sai Krishna Potthuri , "Harini Katakam" , Krzysztof Kozlowski , Laurent Pinchart , Michael Grzeschik , Piyush Mehta , "Radhey Shyam Pandey" , Rob Herring , Robert Hancock , Tanmay Shah , , Subject: [PATCH 08/23] arm64: zynqmp: Add resets property to sdhci nodes Date: Tue, 2 May 2023 15:35:36 +0200 Message-ID: <8f8592d6454c024c8f8b92e56c9009c65ad1d54a.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT044:EE_|DM6PR12MB4481:EE_ X-MS-Office365-Filtering-Correlation-Id: 24256c72-cbb6-4926-3cf8-08db4b124511 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Qizz4p2zP4jR0kn+N3dxcumM6GLRPoAlvtZSR3iAPp8h85BxEytuEJo5U20si59502XbjwcOjyTaw/s+yqfWbJFgUh+kmKwiaiyKv0hHzQqGFQ/DcRFuiD729Wt4kAoyIpERA2jYM5efVmMlr7zjZvfx21tsI7I56wwoOCkmEtg1xqH80FhHIO8a2yQmQ8Dk2QAnliJFXpqq1fbWsIAFE5nqDy+o6bvEHf3cjZiQaCr39k3GWpMcPh8y4w/8zsZvThr9BOAcGOCWfXYmI8enCozp4H605Oh212rNXFfVrEJTrRsTKjwJCdcS+TKUlExlcjujWujcoaqW1CNj/mIZV7bY7yKqw4csdcXHIV/wPT/+YjPsRgndOOMffhOfSqHkRMQIgSXl1Td72e/9WBmHUl6lk8cHWmya3qUbNlTn3Hnsdnfeh7Io9Lmc9G3PucU5cOLJbynbx7HUbLy3lZ42HlC5G8LpqWQj1Rpm3G+FGjz844a8DMu/MzqHq+ntcJ+ChIAeMHpxrlLmDVGWdp/TezGr2/wOgz35szN9Oar0vA/s4nWUgQxZmH3i68SgQAqsO5ZcwKmVLsBYBJ4q0XUqKnWdTBqFGhFr2ku5r13Uh2/85BeKb8t6BPmVaadVMkXG/PkC3O5i+2ILdbscvV+z7oHXcwH5t1D+dh7QAwR9D2EmsRt3ienYExzUYPbaj0l6Y7PvlpmeViRxIYqqtCwEmqWxRugObD9t4re8CJN9f54Fb9w8vQyC5QLgh15FsIrr X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199021)(40470700004)(36840700001)(46966006)(2616005)(41300700001)(8676002)(81166007)(8936002)(356005)(36860700001)(478600001)(26005)(7416002)(83380400001)(44832011)(5660300002)(4326008)(2906002)(70206006)(70586007)(426003)(316002)(82740400003)(336012)(47076005)(110136005)(16526019)(40460700003)(54906003)(40480700001)(6666004)(86362001)(186003)(36756003)(82310400005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:36:44.2528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24256c72-cbb6-4926-3cf8-08db4b124511 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4481 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764789877897556000?= X-GMAIL-MSGID: =?utf-8?q?1764789877897556000?= From: Sai Krishna Potthuri Add "resets" property to sdhci nodes. Resets property is used to reset the SD host controller when dynamic configuration support is enabled. Signed-off-by: Sai Krishna Potthuri Signed-off-by: Michal Simek Reviewed-by: Laurent Pinchart --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index a117294dc890..7bd3e816226a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -755,6 +755,7 @@ sdhci0: mmc@ff160000 { #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { @@ -768,6 +769,7 @@ sdhci1: mmc@ff170000 { #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: iommu@fd800000 { From patchwork Tue May 2 13:35:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89361 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp621632vqo; Tue, 2 May 2023 06:39:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5ENx/DDVUr4HCd6tTbo02LFT9AjjpBL1uKqU83rJDbSvV7YibmmGJzPNEigHJEWONfecxh X-Received: by 2002:a17:90a:bb89:b0:24d:f77c:71e7 with SMTP id v9-20020a17090abb8900b0024df77c71e7mr7925773pjr.41.1683034782635; Tue, 02 May 2023 06:39:42 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683034782; cv=pass; d=google.com; s=arc-20160816; b=oQ9OYl073YxyQmwEd6or7q2GeZ3pAG8TeV1iqnKXWxp007r6FZ29/BghUnKKxvUkC/ o00Bz0bYF3xxSlIeQhQ+CZflMkMjXAWO/1BEtzIc/8iYS29plkEx/tlTgLIheE+jfNZj YWXqYrp375K8kDpMkok3hGNuTQ8twr34Q6+0AdsM/gZf1TWP/pNWSXnDLFOCmkk2tg0D DUdIkWJZqDLClWsDlelPzABEsRJZeRc0Wp8KBdlFgp+yCREWSSbWkw1mDlqrZftOJTGv hClgHraPNnf53GoZwoUjV9BP8ArZOOqW8DCSX70mBDSDLT7P7v5iYKEbzQmDHUumTYW3 RPKQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eRtMoRxiGch82YUC2TqCrzUaN6TEm8h/IxLWNZUXE8g=; b=BkZbi5YOYL3np9fpwLoe85HXYHenY/vLNrZitwl9UiJAKl7CbgHG36rtUIjKtQ29N5 BltjgWF7TdNu97p7eOAO6LtAOu0XRcfHigowlWBaWl7optNlKxqw5nV05ypy0mqXePEu +7nyAEdmyOJ+1Vc9cQsOBKLJJLZJOHutgCRQAKW1J7EzOXM89+mY2QdCE9ccz5ZEkZVs 8EJiKyrZHt++C6nE4jj3oinNYGK3cBzIohxOw0ChAp/RREx+ujNXEByYkcaWdpPdhFXJ C41TmCdY4xi2hkMTU+UMvzu/Q3fdOCTzDD3XZ59a4ge3U1jT1p4HY8rTSmxXlErzt56O BA4Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=m4MHHJNq; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:36:46 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , "Krzysztof Kozlowski" , Parth Gajjar , Rob Herring , Srinivas Neeli , , Subject: [PATCH 09/23] arm64: zynqmp: Add dmas, dp, rtc, watchdogs and opp nodes for SOM Date: Tue, 2 May 2023 15:35:37 +0200 Message-ID: <5d3777fdf91d114effe1921255a7ad71ef30d277.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT109:EE_|MN6PR12MB8516:EE_ X-MS-Office365-Filtering-Correlation-Id: 78f82ebf-6ab9-4f26-ac2e-08db4b1247ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZBqqUg1gdr0hTsm+fj6IhkqJw/mHt6LEFHtRhEuxAcxm9DR1mPXQN4JTuKzkqvj6y9n8DNwpeF0SyI+JjrqqcSqC5kPzwy9q6RJjXKrgk1djKGLfSb71wZd+UpqFc6Bd9CiczIWMJBZastswC3hGWR22JNCbo8lWONCyR70x7lPFfxnldjU4G2yrPVYGKUYOhQDuZoTsv0PTUi+NrFShNgcoS5WzM2DHMj4/IFzA9qPgu/bxlDYnbLS0sEDtb0FX7uuo9Htj/FloObFIe16Qzr/rgpcrB9rPTBFEyGvfsHmT3w4SaUeSgRWSq+RYtqrDXZ6hZ2BazWs4RfH6ixBERbAlsAlQrK6uGFQGxKOz20bSPgVmaMvFzz9PBP7XoelyKW4XR0ywcMbbiw8s8XUzXVR6sT8MmBJfG+tZYWOxb2QrhKGrUcHdh++q02H/6UdvSsAgxJa6K02hfqitvxYThzyJ1nvt0ITSMIBCQb6hDTgByBfuCnBqldsBHQk5eDt6CKxWme5ZZbJ3MrRzdxQ1GQYicP79Lpg7QDzq/TAuy2aa+oS1RV6vyyiZyYQ0HAfTCWT016IfvS1xmEdZDlm/SYbwYvIMYy6kFKUv5p2gd9QktN6iS0rOOixXov5yVCZUvZNhxr/xMWDXRlxJWWdUgFSFZizaGhSb6a8eRea3Mp9iufJ8lc9A4ZftlqI6kV7MGVisL3b+8hHR3gV0bdiyDOCYxs6qYsKscdYG17M5XVCZxju/fnA8LRZGiBOz5D4B X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199021)(40470700004)(46966006)(36840700001)(316002)(2616005)(4326008)(82310400005)(40460700003)(40480700001)(8936002)(44832011)(8676002)(86362001)(16526019)(5660300002)(478600001)(54906003)(70206006)(110136005)(426003)(336012)(36860700001)(26005)(70586007)(47076005)(41300700001)(356005)(36756003)(81166007)(2906002)(82740400003)(186003)(6666004)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:36:48.6269 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78f82ebf-6ab9-4f26-ac2e-08db4b1247ac X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8516 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764789879990086838?= X-GMAIL-MSGID: =?utf-8?q?1764789879990086838?= There are couple of IPs which are enabled in origin HW design which are missing in SOM dt. Add them to match default setup. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index dcc17e3ea961..3862168fa026 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -288,6 +288,101 @@ &gpio { "", "", "", ""; /* 170 - 173 */ }; +&zynqmp_dpsub { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + &gpu { status = "okay"; }; + +&lpd_watchdog { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&cpu_opp_table { + opp00 { + opp-hz = /bits/ 64 <1333333333>; + }; + opp01 { + opp-hz = /bits/ 64 <666666666>; + }; + opp02 { + opp-hz = /bits/ 64 <444444444>; + }; + opp03 { + opp-hz = /bits/ 64 <333333333>; + }; +}; From patchwork Tue May 2 13:35:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89385 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp633691vqo; Tue, 2 May 2023 06:58:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4+U4RBJKW5mLyB8RWiov3G9qMDor0NBKLVO6DTKKjwAnqNNKNHLo2QC3WwKPjiaKIqwFxl X-Received: by 2002:a17:902:da83:b0:1a5:1109:f58e with SMTP id j3-20020a170902da8300b001a51109f58emr21122808plx.29.1683035938349; Tue, 02 May 2023 06:58:58 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035938; cv=pass; d=google.com; s=arc-20160816; b=dVyBuDx/QGSEfwIiYmLwj3UjWwTg5D5tX2HDhM3YISGqZBB1Dba3DZLS89cLs7Eo5P aFbN2MTEwQVteOW52aiotALSGtQqRKiV86UfDwyKh1Xu1QjvjzWaN4KxCGOVXix+7MRt P8n+H1GLFz9ubVutsRlYuopkZmdHeAoxQqOg8Qpiu1vzpPWr0se9wrFeuyyhxtQuq9Er L9GFS/lWmK7DNBrofDS29/hohYP/tVFVKRibYb4luoq90xjBEuD2BDP8yUNcF8q8rZv2 GBTSJ9eCx9r1wScsw53XFcO2Fyn/3DXgpin9cPmY8FmoimxECQcDFA6oO/cda1cdO/Ty otIg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ylh8b5a2BN3/fjePm88uxNb9v1sqH+RyB+kr+738JDM=; b=qbuh8VR6nwj4RZGgPlzjsljAJ0vZGUAfBMWRA6BC4+tPsPyqkL6TiJbPzEH1nN4mCt qC8rOVXP5MUpd4JveT5cj2OmlMnLCXx5wfdNOV5EPRaS+JKolKpR9meE01//PZEkAwto LJPJWaFQ/O1SVG8CRtZXyifx9DHl4uo0h5qsqtT/uPS7leSvK3MXgKVZgrzrvDcb9dMd 0fzAdS8bFaHrChiVATqb8CJEdxK1mBxL088cs9BFHt+UfnsdVkmOF7UqUgI4X7ykMVzH aYUygeBPG2t735Y+7HRNJlfiommbFfib++kJ72iAItszXVMjGZR6ox9dzjGzCMGpxfID glZA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=hjkhRyaK; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:36:50 -0500 From: Michal Simek To: , , , CC: Srinivas Neeli , Amit Kumar Mahapatra , Krzysztof Kozlowski , Parth Gajjar , "Rob Herring" , Vishal Sagar , , Subject: [PATCH 10/23] arm64: zynqmp: Add linux,code for gpio button Date: Tue, 2 May 2023 15:35:38 +0200 Message-ID: <4e20661f43b1fb8432fa5fcda5c1cb50d0a27475.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT107:EE_|MN2PR12MB4440:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d654db8-68ae-454a-c0fd-08db4b1249ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PMThYcRWdnSpgIhIXhOGcT8sdoRr/8PwnBK5AgJ3/3f/zpb8kwxJKSZPzGIPY1UV6ZlP13kgh6s+JJXR9cN3YWIxcM46t77HtLsHtDPcL9BJZ07ctgGlZmvuFQX5wwtypkIoU3LML/t7opXI1G15dOftxebs7IXW1R/ie5OiIwoLcgkxLj15Ae/abkaUG0UvkoofXQrgsUSSLy/FZosBomIhehM4cw9aXNQbkhIbDvBumPbLFm22DgCxdUNocu7bJSGFc1pC9X2vdcDTh3TSq3ojmpD4fpXno8+tgkP6p54ibYKSvTFmiYTerQ7Plb5csy8MmvstSZ6/xbtuKy1J1H991o6plbJ+XMWs+qiRnli98Z+oQUeavrujh7/oMam2slJkK0gRlwoquvhBVBME4QPFsONjND9eBpIeEs0Ev1grA2yrS8XURdEDlKb+8MbEH+PzqDpGKttwsXJXBsNJ6zqpvbOxjHQppVCLvcRDROB7jeuOZDzSJZwS27QHDgFtp96B62O+QE+nZDVOWss47dEYmV1CXlRacQ+7mjbKj/VYiC+cytOoWelATxOayTdtMKxZy37cl+d0hNj9tJ9Afn6wPJIxhexiX4zSbdr3aqux2X2lhw75kSRhMgvbsGa5Ym/lUZdzJEczntHVpkBkRkqB1Jsj+F7VO2S56kz1Xx9qDEenB61L80yr/bDYvoMz+2gvw/FgpspktbKL88OW+uncwrLb/scl/XQKFjkWTC4BfUsi3rBXPg6n5CIoF/pb X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(376002)(346002)(39860400002)(136003)(451199021)(46966006)(36840700001)(40470700004)(83380400001)(36860700001)(426003)(336012)(2616005)(47076005)(186003)(26005)(82310400005)(70206006)(316002)(4326008)(70586007)(40460700003)(356005)(81166007)(2906002)(36756003)(478600001)(40480700001)(6666004)(8676002)(8936002)(41300700001)(110136005)(44832011)(5660300002)(16526019)(82740400003)(54906003)(86362001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:36:52.1900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d654db8-68ae-454a-c0fd-08db4b1249ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4440 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764791092502836774?= X-GMAIL-MSGID: =?utf-8?q?1764791092502836774?= From: Srinivas Neeli BTN_MISC looks like the most reasonable option for this button. Button is used by firmware to indicate (after reset, power up) that user wants to do firmware upgrade via firmware update utility. For bootloader or OS is this just user button which is worth to have it mapped. Also button can be used as a wakeup source and pressing it for more time can generate more chars that's why also adding wakeup-source and autorepeat properties. Signed-off-by: Srinivas Neeli Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 3862168fa026..340a5c43a8b6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -55,6 +55,9 @@ gpio-keys { key-fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + autorepeat; }; }; From patchwork Tue May 2 13:35:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89370 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp628698vqo; Tue, 2 May 2023 06:50:43 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5NlaejrAAif88WGepOYosxvA5BTiO/X6drkAq+Mcv9iSEVzGoveT7AOkl58z4tp/VGo/Kj X-Received: by 2002:a17:903:187:b0:1a2:8c7e:f301 with SMTP id z7-20020a170903018700b001a28c7ef301mr18028156plg.45.1683035443278; Tue, 02 May 2023 06:50:43 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035443; cv=pass; d=google.com; s=arc-20160816; b=FJ6gnEjnzYnN7WUC6EpPlntj8j6GyQfhYvfgnuBI9y84IAcm/qylrcihFH6Oyo2oa7 CvUHeZN2fP3/a+p3SIqrzYI6+ZczS/MH3tcPcy5uJ1QG9Jx2E89cfPTpEyhWqDH2GR2V 4ck+RSwNg4KnDH5i4DfdARxzh/Je4T7Vfd6qOu/xyR/3pJ5oI717FMtFQIhi04eNMMgi eFsbsOE+ynTQiHQSQ9xTywsZ3DjqRknSwXKM3fUcRzKc4SENkhQEYf8BncLqDL5F3cvk zIx/lLYu5xp8muphXiGJarALdspt6qvEJbpymQyIi0nLP2hgRcCWuxdQ3V07k/sG0z0M 74kg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2fofahKMjfO5rrYTTxVK0trn6gvPhnCOU0fr+xlH0Pg=; b=oB1tPuO1Kbs8iB/DxPOgs0rDm2+ck0DDwv5m1iAIdRMDhybgqe6ri2npnx4xH9q50H DFhk/BCnQ+2mTwrdupUL+ZNApQHMlXW40VfTy8wXUn9SHdw1VvwX4520S5uDJHQUZ9mH u90TXyaJVpvlETz3mZdug1qf+chojlNtJw/yhWPgOlbs509nX+IzZhaVJGdVougwPNw+ 7X+k5vU/S7XbkB4lkE8ZEJr4joqvJPJUi44/O2W0YG3VAj7tdkUga5HVjz9IoEkLTYAT gM+IWpNHfKjnbNJ/d5rcDpCkXBPg+d5SqTj4H6tn6aLvhB+Q9vTs7eh7lKgJsvYafQTw eyEQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=OPUHdnQQ; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:36:54 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , Andrew Davis , Ashok Reddy Soma , "Geert Uytterhoeven" , Krzysztof Kozlowski , Michael Tretter , Parth Gajjar , Rob Herring , Robert Hancock , "Srinivas Neeli" , Vishal Sagar , , Subject: [PATCH 11/23] arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM Date: Tue, 2 May 2023 15:35:39 +0200 Message-ID: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT115:EE_|DS0PR12MB6606:EE_ X-MS-Office365-Filtering-Correlation-Id: bda28322-b85c-478b-ee1f-08db4b12595c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: V1NMfNIs43JjILmw333IWdBWlwd3WLymJ4CReK6zBq3c33T9snjM76i/2FJzVo/Ochbhu5IaqFBJie+HVSEcPmu8ob/mcA+FuMqgYGVnSw7rhgJ1gn3FMWn6QriifcXcdQj4wIzRHjWVo6bIA9wzuf3f6xAzUg2HsJVqiGGuW2503IGUrK6sps+lMbohwOGR7DhZm4RCV/awkWGKWQMn745U6bNtpHyLgjlySXe8AKrWTIIs5epSYUEHohNBXUvglbKh5YzZkHHQBOFjagNpzktahkLB2jMl45sKwvH9CJu6R/Evgw4zJv7/5eQWDHxNNKc+cP14ibZLGzukE+bQOEIFkN76SPnxHPIrkKDGaGe+h7/8Enj1wjiwxRg6PdYXsslyrqix7YUM7tQWOavi1tK8DtsQ/GbXOak/YaTOyl2/25Uw3kWZTR6EA3KvdjeaPWPGm+jaeXpzmrsCGR6xFDj1eLk87ndcEKzk8iGq4ohQxxeMdgbzYKEjouNxoZuEe0maBXhITmSX/LAaGPPmwqQNuSxnzL5/SoquPvZn0OqHNQLunWwzVNM0V2aZeaNLVe+KN5AGFrdWiwGkZiZfcWdh0qpUe/B3gkq9xT5XMsUOZafTCF8x10vKiABP90aWZrphi44cAY1HQDds+rOAzWl1qMcQVVNDuQUdnyKyQEMuYl0TumnRkA9jFsml4kaGqOMrIQhfCA15pc89VuZsDpUzWVEHkNtAHIV2auaRYpj2YzkFK5ZX9W2K0PbcF1iW X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(396003)(39860400002)(136003)(451199021)(36840700001)(40470700004)(46966006)(4326008)(82740400003)(70206006)(70586007)(81166007)(356005)(316002)(2906002)(40480700001)(40460700003)(41300700001)(7416002)(44832011)(8936002)(8676002)(5660300002)(16526019)(26005)(186003)(6666004)(82310400005)(36860700001)(83380400001)(47076005)(336012)(426003)(36756003)(2616005)(478600001)(54906003)(110136005)(86362001)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:37:18.3032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bda28322-b85c-478b-ee1f-08db4b12595c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT115.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6606 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790573235173883?= X-GMAIL-MSGID: =?utf-8?q?1764790573235173883?= With limited low level configuration done via psu-init only IPs connected on SOM are initialized and configured. All IPs connected to carrier card are not initialized. There is a need to do proper reset, pin configuration and also clock setting. The patch targets the last part which is setting up proper clock for EMMC on production SOMs and SD on kv260-revB. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 5 ++++- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 1 + 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 5e7e1bf5b811..681885c9bcbb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -2,7 +2,8 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017 - 2021, Xilinx, Inc. + * (C) Copyright 2017 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -185,10 +186,12 @@ &sata { &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk SDIO0_REF>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk SDIO1_REF>; }; &spi0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 2f7a17ec58b4..cb4a5126c4ec 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -133,6 +133,7 @@ &sdhci1 { /* on CC with tuned parameters */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; + assigned-clock-rates = <187498123>; }; &gem3 { /* required by spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 4695e0e3714f..31bc120dee49 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -116,6 +116,7 @@ &sdhci1 { /* on CC with tuned parameters */ clk-phase-sd-hs = <126>, <60>; clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; + assigned-clock-rates = <187498123>; }; &gem3 { /* required by spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 340a5c43a8b6..d3c6a9feb114 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -178,6 +178,7 @@ &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; + assigned-clock-rates = <187498123>; }; &spi1 { /* MIO6, 9-11 */ From patchwork Tue May 2 13:35:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89364 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp625638vqo; Tue, 2 May 2023 06:45:59 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4OaTCkwsaqqvqOvXxErPHWlgu9aXLaVBPZKGrAFxoyd8OLj+YQ5948cQrKJKf3ctkDMZN9 X-Received: by 2002:a17:902:c942:b0:1a9:91a1:57bd with SMTP id i2-20020a170902c94200b001a991a157bdmr22139738pla.34.1683035158724; Tue, 02 May 2023 06:45:58 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035158; cv=pass; d=google.com; s=arc-20160816; b=VpNwWlcxIuJSlxVFmk+VYxWSTzQDrzm2alEsYbH6H2XB1kNw2mKV9GlGzJAX3EUV8M Pi/1ORSCSagMqE+UJxVcH1vRGXTIT2VNAI2tLroQKm29Rb7k/Tp5qmqQpoe6i3Utqgby VAjQghwHIoxCQ/QsYuV30MGw4Gt6xG7K8+gaB85L2taSnydJdU8xI8QO4kK44IvlHep3 /VAx6A3vVe7aBzrsLVCmniICvOEI5Miba+5vaUE39+HdVM7EosULgZ9yKHQntMApvV0c +rMCtqOd18tXmrb0b/vsyat0Tu0zjb8FIf0aDMXselZDnFpVoNINVszglKGYY+RJIXtA 9d4g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BC8/1UIWUCzF2+AMagPXK2xExd5k/3krlbzdrE323bg=; b=QtlTqgbVYDzSKov45dtTtICZ1oCtrlU3V+qY9Nm+gYu5sfwK0j52LqC6SX5N8cchiy +2hJWtbM8HoDYQ/b4ZBLnJzUjROfVwXx95aW3CLf/0un6WHk/LCoDWcJ1TGIrBNqAxli qDJvC+BdEhy90X0lgrTm4CxS/S2d3Ts8fUOoow1FLkTiY5XzrdW42eIWI2h+fhJ14ryh ZoBi/0hFWmymDW3tgYtRS4xoGoKJvsDt4DpB/0xAEpqRGVUGvWOhiEH63Am/AKJccI8K tda7QqPp1d4RoORfxppm6BVlDkyvYqzWNt0Y4WHAp2InrSv7dOZelLBn0l/KQvLC3ROj /88A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="t8b/+DUG"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:37:18 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , "Krzysztof Kozlowski" , Parth Gajjar , Rob Herring , Srinivas Neeli , Vishal Sagar , , Subject: [PATCH 12/23] arm64: zynqmp: Add mtd partition for secure OS storage area Date: Tue, 2 May 2023 15:35:40 +0200 Message-ID: <20dd23821118999c6fec2bad52ea446d1a66fefb.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT115:EE_|CY8PR12MB8361:EE_ X-MS-Office365-Filtering-Correlation-Id: b42be925-c572-4816-b325-08db4b125bd4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LeqCNtsR3EYNb52opJdLYWxSDIDFVBh6ybFdHbkjp41j23Lh91TNNzFA14agkhWJmfHWh4fAU6sLcS9TWd98aDhLXu9Aw9jbIP3FHC5rQpmy/emvilmn8VwSgAETA7v0fji9/c9bg02QlXZmxPI7JntlClQMTWp1jfQejhvNWt89yS/TYSNOjlaMvCEjLHHFU6xh1mLQs7oT8iecMt7i0+lP/zPGu50BE+QvdKoXNbhA5pfP6pD7qd5QVsOQx0fNsQUkcCkkXygqOcP/KUEejushH0RUr+sRPCWz2+vZLcxW6GB4DUg8x+IVH0roCIpJPMJlMp6cdYexgsbGD5uXk5oURASDwqqPFgkStMgYyn1WNOyxfHz+NslNqPxxRKvtyprufynR83YvyfmTd5GDaEWBEpw5fkwp/qb1mPM2OuIdZyZJMl62of3wHPH4qphO0z9HM1m+ImkWsAvcOGIZurk9zPCRFl7HLPRO81U557Elv1mFeCztnJ28n1Nqo8aUMEpdPeaPVK8yMxuDBB6W3AGXJsNBIJw+UyL87aNGASovRdCr951WG8l4xoYq0Fw+XaYRnKIEUB/Jfj65hdR/sh82Ho+Dx6zJQACee2nv82gX6fex1XPsuhou2QdCOOdG5ENE874nedivwe7JtrArYr/z4ZHLcz64Zik4CpV1MZ0BJtS8OSPLUkztqY1ZC6EQBcbvcseOpa6UBYfWviWjKf1lNjm14vabN3HGnqzAeyXHVHztrU1pMEjyvOcxyAHk X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199021)(36840700001)(40470700004)(46966006)(86362001)(40460700003)(8936002)(8676002)(4326008)(41300700001)(70206006)(70586007)(81166007)(316002)(82740400003)(356005)(5660300002)(44832011)(40480700001)(2906002)(16526019)(186003)(26005)(6666004)(47076005)(36860700001)(83380400001)(426003)(336012)(36756003)(2616005)(82310400005)(54906003)(110136005)(478600001)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:37:22.4436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b42be925-c572-4816-b325-08db4b125bd4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT115.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8361 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790274840061667?= X-GMAIL-MSGID: =?utf-8?q?1764790274840061667?= From: Amit Kumar Mahapatra Update MTD partitions of Kria device trees to allocate 128KB of QSPI memory for secure OS. Increased "SHA256" partition size & changed starting address of "User" partition to accommodate the new partition "Secure OS Storage" Signed-off-by: Amit Kumar Mahapatra Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index d3c6a9feb114..5fbc2fbd2638 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -83,7 +83,7 @@ &uart1 { /* MIO36/MIO37 */ &qspi { /* MIO 0-5 - U143 */ status = "okay"; - flash@0 { /* MT25QU512A */ + spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; @@ -161,13 +161,17 @@ partition@2220000 { }; partition@2240000 { label = "SHA256"; - reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; - partition@2250000 { + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22A0000 { label = "User"; - reg = <0x2250000 0x1db0000>; /* 29.5 MB */ + reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; From patchwork Tue May 2 13:35:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89373 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp628707vqo; Tue, 2 May 2023 06:50:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7lgLv3LMZZ5UEUxAFivaK09T5SG45cdmxT7YWpcFmQAcnxdd3GvolnbMY19hd86pGCJ0J7 X-Received: by 2002:a05:6a20:958a:b0:f2:bfe1:4867 with SMTP id iu10-20020a056a20958a00b000f2bfe14867mr17817696pzb.17.1683035444011; Tue, 02 May 2023 06:50:44 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035443; cv=pass; d=google.com; s=arc-20160816; b=BpHQ7JjBRPpga7/Br+kXrP1UmwjKr3FLajrM60BCU4iK1o/gfjvETrREO7SrAPnmZW WNO5fSq7n+Tw0KmzTzANMCx0sGJ13InjCCXgv3wrtDznWWAatTLB6xCXcCcVJuedmJ68 XKk7FdiQJmChtR0TErF8aYReuM8dyDwyup8QLoC1L8d3o1VvxqvBYpOI4/R7us4V8KCo 9fZKfh2Gwv+QBr5mY7p047ioaF47AlCCy9Vag4tIr9C5l6/bn7bAk3AYsVfhOkarRwDo c8ivCi7lv/5V5s8a/TzzX4XjwCCEXu/I4wteG/cQAJq29M8OWzWh6TDElcSwUzsL1rM8 9Xcg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rQFvyoPSgfYvPEEleHEK5se76uHOKDoGyolMGYoZdD0=; b=bw5d3u572ifOAWslerKLFo7i5MRxJ0kmx67l+fZo2HbxUc/SHO57ZWI0ymzrOYyng4 xBnS6WYxHHBi0srV3omNggfg5jKitJe/a2NPgZxbOi22ItSotutZfwMPQ8JhMH+WsUar yqn1VIFzOoGWzq4MiJAfg2voo068fArP/MNmHETpUOaJgNL4w4syQeTT3StEOIlei5D8 A8QK+aZZ5jB21BSBV30gOuIfzbnMCG2lhJIVyPp/djc7fCGNGh3pZFrrhw3QwVXRFXg3 kTgsrVbcriYHmoyID4TFVACxk6UitSqaZsT3+jhNeKrscirpcWRA2prrh8zc1r5wTJLs +mjw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=ncW2XnNe; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:37:22 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , "Krzysztof Kozlowski" , Parth Gajjar , Rob Herring , Srinivas Neeli , , Subject: [PATCH 13/23] arm64: zynqmp: Used fixed-partitions for QSPI in k26 Date: Tue, 2 May 2023 15:35:41 +0200 Message-ID: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT060:EE_|CYYPR12MB8962:EE_ X-MS-Office365-Filtering-Correlation-Id: 44dc5de4-6306-4fc4-2eeb-08db4b12608e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: INYOM7hDbW0pa3Q6GC2+/KLY99dhLlcap+Vq3NiUBoXmXlG2PlT492ut3z24jBeu2P6SnUcwwmFSq+G+FrqktGgbMs4T9ejPd2VBkvvlCZdqCZUJso+a9HhmY5ZnV1Bt01bgUQ6p1a4nu7aAs90jrBPNlt/vLK/HqBOnxQOobgVUgS63rT1zCb/wBBdQ/1Ziuegi7ib7vEs8DqinTtvFirVjtrG+GkawntvtOu34txQuDpSoQ66Rv5jFv9jgW2dBQjE0XpBvKetUTQWkMYCo5JRrEgR4PlEsuwYLHyFO8fW7q4M0XUXX0iznyXNeNtNfoOVzWVenzbluVtPik0deqXVQaAdRu7EVdB4CQgSLZa29lJdUFAAA9zIJMR8ZIQkIHRl453Gl0PU/Y2p073M0/iDMY/jxna504qz6wi7/PNFzKX03xcrYA15vAPDGvnBGPBUUe5kj4Id+84NrO6ufx0Z5o2bWyNrSMmmdeCuevgJmzI42Nfenkc97jOT0kyxfTP4LG/9MqJkpGzK7YOveBxeBeqM+T96HMlt/3dfa6QWyaja1E5gADdRnqa9QItErKfSnAXIIafp5h7Un07Fs4NkhiFQpSriKen6xKaFcUYHjAOnTi2PUDZzPUROu7LxGeB0FbmHxJU1uFapdvbd4aC+7O94xZ52t1DNCLmcGbrErwrmuySQMLk7e5yFI6DvLf+6ly8IAxgTbhahfFX5rV4Czyz56nXP4kXlqdknT7In/HHdHe531GTAKOP7nwtAY X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(39860400002)(136003)(376002)(346002)(451199021)(40470700004)(46966006)(36840700001)(81166007)(356005)(26005)(82740400003)(186003)(83380400001)(426003)(36860700001)(336012)(2616005)(47076005)(16526019)(36756003)(44832011)(2906002)(40460700003)(110136005)(40480700001)(86362001)(6666004)(54906003)(478600001)(70586007)(82310400005)(41300700001)(5660300002)(8936002)(70206006)(4326008)(8676002)(316002)(2101003)(36900700001);DIR:OUT;SFP:1101; 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Also add label for qspi flash memory to be able to reference it in future. Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 169 +++++++++--------- 1 file changed, 88 insertions(+), 81 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 5fbc2fbd2638..cb3e5c06fdc5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -91,87 +91,94 @@ spi_flash: flash@0 { /* MT25QU512A */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ - partition@0 { - label = "Image Selector"; - reg = <0x0 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@80000 { - label = "Image Selector Golden"; - reg = <0x80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@100000 { - label = "Persistent Register"; - reg = <0x100000 0x20000>; /* 128KB */ - }; - partition@120000 { - label = "Persistent Register Backup"; - reg = <0x120000 0x20000>; /* 128KB */ - }; - partition@140000 { - label = "Open_1"; - reg = <0x140000 0xC0000>; /* 768KB */ - }; - partition@200000 { - label = "Image A (FSBL, PMU, ATF, U-Boot)"; - reg = <0x200000 0xD00000>; /* 13MB */ - }; - partition@f00000 { - label = "ImgSel Image A Catch"; - reg = <0xF00000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@f80000 { - label = "Image B (FSBL, PMU, ATF, U-Boot)"; - reg = <0xF80000 0xD00000>; /* 13MB */ - }; - partition@1c80000 { - label = "ImgSel Image B Catch"; - reg = <0x1C80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@1d00000 { - label = "Open_2"; - reg = <0x1D00000 0x100000>; /* 1MB */ - }; - partition@1e00000 { - label = "Recovery Image"; - reg = <0x1E00000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2000000 { - label = "Recovery Image Backup"; - reg = <0x2000000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2200000 { - label = "U-Boot storage variables"; - reg = <0x2200000 0x20000>; /* 128KB */ - }; - partition@2220000 { - label = "U-Boot storage variables backup"; - reg = <0x2220000 0x20000>; /* 128KB */ - }; - partition@2240000 { - label = "SHA256"; - reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ - read-only; - lock; - }; - partition@2280000 { - label = "Secure OS Storage"; - reg = <0x2280000 0x20000>; /* 128KB */ - }; - partition@22A0000 { - label = "User"; - reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Image Selector"; + reg = <0x0 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@80000 { + label = "Image Selector Golden"; + reg = <0x80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@100000 { + label = "Persistent Register"; + reg = <0x100000 0x20000>; /* 128KB */ + }; + partition@120000 { + label = "Persistent Register Backup"; + reg = <0x120000 0x20000>; /* 128KB */ + }; + partition@140000 { + label = "Open_1"; + reg = <0x140000 0xC0000>; /* 768KB */ + }; + partition@200000 { + label = "Image A (FSBL, PMU, ATF, U-Boot)"; + reg = <0x200000 0xD00000>; /* 13MB */ + }; + partition@f00000 { + label = "ImgSel Image A Catch"; + reg = <0xF00000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@f80000 { + label = "Image B (FSBL, PMU, ATF, U-Boot)"; + reg = <0xF80000 0xD00000>; /* 13MB */ + }; + partition@1c80000 { + label = "ImgSel Image B Catch"; + reg = <0x1C80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@1d00000 { + label = "Open_2"; + reg = <0x1D00000 0x100000>; /* 1MB */ + }; + partition@1e00000 { + label = "Recovery Image"; + reg = <0x1E00000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2000000 { + label = "Recovery Image Backup"; + reg = <0x2000000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2200000 { + label = "U-Boot storage variables"; + reg = <0x2200000 0x20000>; /* 128KB */ + }; + partition@2220000 { + label = "U-Boot storage variables backup"; + reg = <0x2220000 0x20000>; /* 128KB */ + }; + partition@2240000 { + label = "SHA256"; + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ + read-only; + lock; + }; + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22A0000 { + label = "User"; + reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ + }; }; }; }; From patchwork Tue May 2 13:35:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89381 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp629634vqo; Tue, 2 May 2023 06:52:13 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ56Pq9MLBn/t2485iwgCAmfRf05uQ/6aoDoorJ7P+3V3vDcwowFun8xPm5b0zlSiCg/dOfF X-Received: by 2002:a05:6a20:1613:b0:e7:7844:903a with SMTP id l19-20020a056a20161300b000e77844903amr22850779pzj.53.1683035533243; Tue, 02 May 2023 06:52:13 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035533; cv=pass; d=google.com; s=arc-20160816; b=On8wVsyp71YCGi0sbM/3ciA0mEvCbwkwk4Onw2c4nwAinCl8elSUaUo5287I5WGTZp 0ZBQzl8K9GSrkx73F1cNreLxeH3RGFOQlYca4/bgyrd9kEmN192hu6Vj+OM8s0g2BLuJ uySZPB+tuaKt2sl9xGVnBTNLgIosaV/ttXrsG4JOVoE8FP3785bLNE6pb9ocTyCmnxL9 gfQnNe6wuVVocdSs0K4yb6mwbmLso8a2Fiac4v1BMQXWDItuBFAIUeHoPLGfit8ZDQL7 i+xQMuoMUHJuBZQZD9go+u20FdK3fMUxjDyluWInHo5BF5LroO9MQ7pyOApXatkseZI3 YWAw== ARC-Message-Signature: i=2; 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Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index cb3e5c06fdc5..c206021cccf7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -77,6 +77,10 @@ ds36-led { }; }; +&modepin_gpio { + label = "modepin"; +}; + &uart1 { /* MIO36/MIO37 */ status = "okay"; }; From patchwork Tue May 2 13:35:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89382 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp630054vqo; Tue, 2 May 2023 06:52:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7O+yxb0Z5cRnY/aO6wJGr0tUeJGWwtpAwtnra9Z/oPFiatM1GyegUq70vDzoTI4JTM5hhE X-Received: by 2002:a05:6a00:1ac6:b0:63d:6228:6893 with SMTP id f6-20020a056a001ac600b0063d62286893mr24002876pfv.3.1683035574376; Tue, 02 May 2023 06:52:54 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035574; cv=pass; d=google.com; s=arc-20160816; b=YpbfFxoO8nJoZlNkSmT1K96IIfIfqkSfVdGc6aCt1L00Y8PVJXZYIIxJRcOEyhGHCF /CDqcPSV8dn/CA+lTwJtlXV0ujlC1P/oWq9ijJUxiHjul3tsUuCJiSKNyInNBHeW8TT+ uD/GI26i1nJ/SkEUBA4iUUsoESzTRe7tbkT0oTn/+W1iBKMKyVY7K7HCu6rjHRX/RB4p 0RXP1S9exyDk0KkjFynPp7oN4xpYIYxZ+sMx2nZRIiH7ddLbNrE8S/ybJrY+yQLbt8m4 lEp2M6xqzTHMdItAVb5duTcsx8YgNHoelTTmMdnSWbLJe8MACtU48v0TMYWGekX49bba mnGw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=O9fxuTbh25Bu4TGMyD23EsbHaEiE9AJ9OnAOQ7gcDL0=; b=nIQwsHA9XWTPEUwgR8zc4jukNVqqzzF2A4l2rhwcogQpnuE9hd/7869Iezo/pnurQy I2E8bDRy1fZwEfR4gzlzQd9KvZ5TncV3w8v1ymt+yT4UDt5mi0+Hrvig/YHlLTEe5rV9 uaRys5KGFvnGrM8jCLXR2u/o2Gh1kdOe/S+ELt0eKg9+5oMFm0Mjvdzce8U+4sorFkkt YsGDc/1V8nZP7vnnGzaKg9BkwNnI3AILu2BD6bn7nXAXQtOuGN6RoJ88A4PlK1vYBlc+ D0gRzPQnLU/r0ACbZlyCwubirwXX8s56xXGHlk8IjuQNwGhKRQDL6r21QwUf73dLvXAT 3uOQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=ZO6N7emj; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:38:32 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , "Krzysztof Kozlowski" , Parth Gajjar , Rob Herring , Srinivas Neeli , Vishal Sagar , , Subject: [PATCH 15/23] arm64: zynqmp: Add pinctrl emmc description to SM-K26 Date: Tue, 2 May 2023 15:35:43 +0200 Message-ID: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT079:EE_|DM4PR12MB5216:EE_ X-MS-Office365-Filtering-Correlation-Id: 499de1c7-c06d-48e6-6962-08db4b1286c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UpQUeyYLQ7m3YTvx9e0zh6PK3HUf9bXfJSHmLB5y9NJDToMjPKhBBaodvr2hXlYQ/qEQeyIR7KIcKtBGIR9RLYxbWFNu5xgCgZIrNoKSfDX3ucNagYS9WUYfBAz4mcJVJ4FHvGWOT193ATRMxz+jfnqq0KOefu6Vp+bU4+ZNc7dyhwhCLyGisb9iY1Tiy4BLsR8pCy4A2tXiUkUkAhvcBxFDWyOI6oEkA/7aj6SHVbcJ0YwB6rlIXq1Hm+Gl0/WsWx/YEWXc/ccfZxngGFfZn3Ugjsvc3qv/h1ypGMWG0M15SNMOdSVWqe6VTGwU3e/lWbaS2ljp0yLd88q79jXZs2pI86K3keaaAtrm8cuXZdeUlB6kH6691wM19ARCzcmYMpwuqB+iXLJewPSQ8L2dm0elcVxismyfvnbEZEwEG24WhfxDmdnDvH2hN7mG1kKfScVdw7dYNFBdBtZzU4ENBTyzS2xQScweDgtPBSn1lB09f6cTJLGfmXWUm0JkM37yNPHeRvX1f5ZS2adOD3NNoNFKi5sJKHaXY2vIac3bHj4fVKXNf3wrVoe0l93gtK6cWDDgtMGVoCiYihw558YAI+vOgGXKGWdCrslcmVKosM55Tt6NlPTJO+4vufx5wUrPvrOz4YlX4OB9CkBLsE3BWw0fMaSj3+9ZNVMbQvliMSJmDmFPACI+tEaIe/336Nadd6JuKt8wheMp4PN84b2++43EGuUUgheLeTMCUKQvDIoayrEf2fO05u1oxkZ7lc8O X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(136003)(376002)(396003)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(70586007)(4326008)(70206006)(82740400003)(82310400005)(41300700001)(2906002)(36756003)(8676002)(8936002)(5660300002)(6666004)(478600001)(44832011)(316002)(40480700001)(110136005)(40460700003)(86362001)(54906003)(186003)(356005)(26005)(81166007)(16526019)(426003)(36860700001)(47076005)(2616005)(336012)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:38:34.4789 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 499de1c7-c06d-48e6-6962-08db4b1286c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5216 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790710668204404?= X-GMAIL-MSGID: =?utf-8?q?1764790710668204404?= Production SOM has emmc on it and make sense to describe pin description to be able use EMMC if it is not configured via psu_init. (Still some regs are not handled but this is one step in that direction) Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index c206021cccf7..e284979fd7b1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -14,6 +14,7 @@ #include #include #include +#include / { model = "ZynqMP SM-K26 Rev1/B/A"; @@ -85,6 +86,23 @@ &uart1 { /* MIO36/MIO37 */ status = "okay"; }; +&pinctrl0 { + status = "okay"; + pinctrl_sdhci0_default: sdhci0-default { + conf { + groups = "sdio0_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + }; + + mux { + groups = "sdio0_0_grp"; + function = "sdio0"; + }; + }; +}; + &qspi { /* MIO 0-5 - U143 */ status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ @@ -189,6 +207,8 @@ partition@22A0000 { &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; From patchwork Tue May 2 13:35:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89366 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp628000vqo; Tue, 2 May 2023 06:49:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5e0CA3G68wswlHa1gzrmTTpV33ZO9ruJopHwuae+99rBYvztuRLeEMkFPkaf+kmpFE4Cbv X-Received: by 2002:a17:90a:858b:b0:24d:f802:9172 with SMTP id m11-20020a17090a858b00b0024df8029172mr8245856pjn.19.1683035376856; Tue, 02 May 2023 06:49:36 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035376; cv=pass; d=google.com; s=arc-20160816; b=QDBB0pc2gwJgABG9Qrj6s/jdCPk+LfFiIxyt3Je7pM3Qcl/oELvOeeBuaBN2RJqDpt KaIFaRHf5gS6iofJwG36sWlNLtBK3FTJ9heTc6imSnVazRxIiyNLkEdY07hZjxza4eRX psCpwVCvDuj7f/UvWyMmC5Ks+0ldZLZGYJNL1/woOJop8nYqKhsIg+zDQ62Mxgw2fXRp IQ6/kAIhAlXeP8u9wHYmdzmexpULb84doprwh/5b5PUTwd2AEhVTcb3uZkPhOKEs6d8O 4ura3drDzrBZmb1dB+fp7qxt3AjYOdlngBIY7WNh9Doft/3hazgvzpXCmRpPGPlEFywI C28g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3EfsS/5i+Z1WpYHE6AGUyvlsJgPv2m+lL8IKcxVM/Ts=; b=fD20mi7XWt3sJX5EAtW+ahwT5Bkp5uzmjOLfqbKsMEmKQgWLhlUuelLWo7RaIO7IuH qYVNuZiKG/fNZbhahjsxWPP2UWb4AFnrJH+3Kj7hKkR3WdHBQOFpvB2+6yiBq8JNry8s HBBe6vBj6TPE7eUaWe/HHHLx4ZwsQXXqGC7tZBHxm54aagjPclfwZYhsiipl/LdAPWU7 EptNm2AohwyPESOF4sXmsf/8FnuiINROQIWS/t9KwpxcvcvyBW6b2mqYlLWQHzclFfYz /kgfDAiMLC5uaTjffVOT9J0guIve38oE5uk9IjaTbZciYJjEtm3AmdxYMO9vRgh0IB9y YXdQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=yLOxOef0; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:38:36 -0500 From: Michal Simek To: , , , CC: Piyush Mehta , Ashok Reddy Soma , Krzysztof Kozlowski , Rob Herring , , Subject: [PATCH 16/23] arm64: zynqmp: Disable USB3.0 for zc1751-xm016-dc2 Date: Tue, 2 May 2023 15:35:44 +0200 Message-ID: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT096:EE_|IA1PR12MB6185:EE_ X-MS-Office365-Filtering-Correlation-Id: 86c59c7a-65b6-419d-7393-08db4b128948 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4CfmdKuvMRcEndZ7qp0C2WxZEOcwhP1xeqbgQEMZ+e6WJN55YXgf3x0B1VAT4+IfG59rk43nf0zK7NCTzSiMaXeBUssZFFpdFTaMFmiV+Ev+SaRL+bqAcXv/ZV3c/nGYVe3YaosP/opRRwHXbZlwqQjnBzMlbwqVPpj1nyDCTPridX1TAm2cjUkRUa3HYb0tz6klWh9dd/7OVsYAGyhUI92fichpAF9X7KSfeK+zSeyc6wZbArL0OQahFUqqb/yYM15mKpAJhC2LhBRuFszx0bYoaV+f8IOi7j/N8VnOwj1Bo6G/qjlxUo7FHzy8aa3qHA0Bg0XgokIM/R4KKGsejALCSHxuxpfBsAtpA2E+xDeHCKKb0QSoBhVHsfTgMMoQ871QNNhPoaYfo3BPheS9u8zHw6gZjEpDuJaJuPhqPeLvC0Xa6BEQi7tb4vYWZqo5nSFHz+wwku4Vz2Bud8+pQ33/DMAGvUZVC6e5Tr7tH5GovmFnjfT9i+p0GoX8OUtHVGA5RunwIMTXga9PZ3jJ31I8dZb42EjFHkqZla4+wF5fZ6x5LuRaKcpg+w0BHYMufWkUjg4zqXSmwhVEBfvFWt7l8D4spX10I+EVLB91csttSA+x7CJbG7iWof3QCcNTyt06SE9kRQQMrRgEkZ6qL5qRDn2o0BHEd6suDirpPjcnPtfmXqR3i0OIUx3X4mj3WniZApDbW7uKTry3LF+PkLQkM2wghZ7KtiogfvfIr68P1lmm1BcSE6iWcIfF5xKv X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199021)(36840700001)(46966006)(40470700004)(36860700001)(82310400005)(83380400001)(47076005)(336012)(426003)(26005)(16526019)(6666004)(186003)(110136005)(86362001)(54906003)(36756003)(478600001)(2616005)(81166007)(70586007)(82740400003)(356005)(70206006)(316002)(41300700001)(4326008)(8676002)(8936002)(5660300002)(44832011)(40460700003)(2906002)(4744005)(40480700001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:38:38.6997 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86c59c7a-65b6-419d-7393-08db4b128948 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6185 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790503255934059?= X-GMAIL-MSGID: =?utf-8?q?1764790503255934059?= From: Piyush Mehta The board zynqmp-zc1751-xm016-dc2 support only USB2.0 that's why remove USB3.0 DT configuration. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index a2031187d9b3..9e7564235b69 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -489,8 +489,6 @@ &usb1 { &dwc3_1 { status = "okay"; dr_mode = "host"; - snps,usb3_lpm_capable; - maximum-speed = "super-speed"; }; &uart0 { From patchwork Tue May 2 13:35:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89376 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp629083vqo; Tue, 2 May 2023 06:51:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ73UNKoIGk3HvHkgPehqWiDy8JR+CC8MAe3ia+hzxbZTjXLEzJUDOoLPVCR2La9rmPtuAHZ X-Received: by 2002:a05:6a00:c8e:b0:63b:8da4:352e with SMTP id a14-20020a056a000c8e00b0063b8da4352emr32069577pfv.1.1683035481774; Tue, 02 May 2023 06:51:21 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035481; cv=pass; d=google.com; s=arc-20160816; b=sYqhyf/W1PfwQcVyQE+ieoBrbuH97sM4pdy04Nvxn/C0AM/FqS/iUIsI8v1gJtFyRB d4ovEZ/Pcd0lP6ZKgHwU9PujWuYxwcoO54Xpo2kY6wstnGyWxItpUOcFSdtELxjltlYa VAsbdIjPWcwZVvUY0LEWVTBQ4RPYgsd2bBtck3dEH4+qlNoHmbzfhZhsrkm3e1wC1hDM Z3VeoxQpS99EuaI8BXMdDm07935Z3e9YY94b2OI9JOSO+wrWxqdzC1YpSpk8LYU3sQ7P y1pCXCMVCa/pR7owTQMP2NXJCW+hhYw71rTioWWRXWiViK+YLqKvwYva9+UHIK+mPWFB X1Mw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aNLGlWrtSEfeDZzc0T9mpV3XrkBdor9YMe01kTZX3Kc=; b=QZl+pLY8js3bedgz7BvXDBiExT/3yke3my0yg2cwD5xHUi6Uw6NIP1AvvoL7HYqYf6 eiJipvILl/9TZfWrVL0r1fgy6xBSdweWBdT+YxyCiSgtVlcVpolj7gXoMvW1MvTvrdnp WYoFZQehTdvLf5Q9s84kTLxK/71Kn2TO8/eIEx//+O8O+IX8kFv370nqn5+qY7q0fZmA /yuFfn/F6Z/z2OwRGiYViyHtebwKMq4WD7hAgGN5ygkghbsYyw3xXQPLr2XXuk/ZUXMS 3Z3RAxViHOmKWTYzE9A88JskyVWwR4X8WZCggIk2tbNFJsnvDh7PG0BGEmWwC7gvn0oD RF4g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=RXS25biU; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:38:40 -0500 From: Michal Simek To: , , , CC: Andrew Davis , Ashok Reddy Soma , Geert Uytterhoeven , Krzysztof Kozlowski , Rob Herring , , Subject: [PATCH 17/23] arm64: zynqmp: Switch to ethernet-phy-id in kv260 Date: Tue, 2 May 2023 15:35:45 +0200 Message-ID: <4b139e942c2a808eecbb30226b6ea5303348390a.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT011:EE_|DM4PR12MB7645:EE_ X-MS-Office365-Filtering-Correlation-Id: c5128070-48d2-4402-d92f-08db4b128b7b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IQz2M3OVHGgPOHiXTOy+pQaY12UvhKYHGq49Wu5+bVg4nPPRStGyj/0RoxwZA1FXJGaljLIN9UVO9p6856pQm+2gcMFVGljMJBv/1wj521xiZld0AdPTJBD3xHrqDtkEeaaFshMi8xIeb6pIfVRNORUAQRQa/Aihdng+dWLdzOwQWstN3ZGdgA7dcxWnVtu0CDgtDvB2+fPnfAdmGOfS+P9l+y2MzKCjDnfV1bwiIj+hCrLKjk+YiyhRHYDQH1UrlqhC9JdtzbnafEbeYXpM4y+bDqOCgFtH73rz8EW4wXFGSiEobvP5qoUZOTbMON//WgpaJKGSmXumE+YSXqVeAIivQPR2FdIo1S91jxKhI+DdlYexF4N5TUVuW+NqWyw5NWsVZsYhzyT5i+spjrRf4K4R+fIQ0d3FkAjLJfr7OwCh4UdVUXdg0SpCsrTKFyrfUPAcG8ZlZ3briz/7wadOIQAHl5AelSPvggoq4Xzs5gV7BYVOWO64w4LQIY4nWfDsJ2m6sYhtJA6J7vVs3sZvTm8WNL/scfD83FECf8ZKAufCBv2/K47+iNXh6XBToi/XnO72tSIDp4ZDMthaBRmWlfgqZZJrD5Y6cRvIYm2ea9zKWOe7s3Zg7E66z0U27VYmyaEag2QLSw8DrPj4gDhdrY3wGhhBq37FtRJoKp67iRr4GHo6cDWuAnQlpoSmSx1XkTgD+LD80ZpzmDiMaqMU4+jTQiHT4rGLAxAkGjKP4EDGsn68myjLawIJFB7ldHaG X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(396003)(136003)(376002)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(70206006)(70586007)(2906002)(44832011)(336012)(86362001)(2616005)(426003)(82310400005)(7416002)(5660300002)(8936002)(8676002)(40460700003)(36756003)(41300700001)(316002)(4326008)(54906003)(110136005)(478600001)(40480700001)(186003)(16526019)(82740400003)(356005)(81166007)(26005)(36860700001)(83380400001)(47076005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:38:42.3920 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c5128070-48d2-4402-d92f-08db4b128b7b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7645 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790613379609938?= X-GMAIL-MSGID: =?utf-8?q?1764790613379609938?= Use ethernet-phy-id compatible string to properly describe phy reset on kv260 boards. Previous description wasn't correct because reset was done for mdio bus to operate and it was in this case used for different purpose which was eth phy reset. With ethernet-phy-id phy reset happens only for the phy via phy framework. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 6 ++++-- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index cb4a5126c4ec..817d756142ab 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -146,16 +146,18 @@ &gem3 { /* required by spec */ mdio: mdio { #address-cells = <1>; #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; + compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 31bc120dee49..e07cec231ee0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -129,16 +129,18 @@ &gem3 { /* required by spec */ mdio: mdio { #address-cells = <1>; #size-cells = <0>; - reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; + compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; }; }; }; From patchwork Tue May 2 13:35:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89379 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp629359vqo; Tue, 2 May 2023 06:51:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6NKOOaplAAc9N6Bk3fMY1DT5LnpgfZNb5LDb/QrsGLhzdK7l9ALhmObDQLvjkaSfEyFerh X-Received: by 2002:a17:90a:a89:b0:249:7224:41bf with SMTP id 9-20020a17090a0a8900b00249722441bfmr18104506pjw.47.1683035507645; Tue, 02 May 2023 06:51:47 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035507; cv=pass; d=google.com; s=arc-20160816; b=I97g9AAaHzCEbE79/9vjAOprC70AjGpYczQuIMJLpqhXBYKXJZDzjIRklpCas1/gX4 qPVOgLUQdWh7Hg3E/OUAdMH5hifZLGWkB7Ma7maTK+aw9+z6j6pcbYKg0MCftJD0jsve ZQNOH5D3x/0nI4uAI7e6w/Hk1F3qhzR71LXTvEl6SzCJkveN0Ed3EVhg42OFJS6wwSQB JW87sImWeuEI/p5ImA+5OuG2sQBVBN+z2KHdUJZnsENY71VR0qbaceuaZ5KEQ3hHYQsn 0XtnEnyX/lSFz5MtGHsYW8mQ/LnEKPLgotTFVsds/vUVeIHiDugwqyeLXX1vyJrXPNnm S1gA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fNiveV60GuuaJ0XYxjjVasyQZ671WbS96Ms8V5ryStE=; b=J378EJnOS/iESdaX009bO/s1PEMHg0VUuYZiVdDS/YSsU5mIo5jMChrkzeOADuvCi3 dkn9iswnX42qjSRsnjC1VxZ2T7Duc8z1KJz7ILzch+s9o1BtiGsIjzxF8sgJS9extMKU SV2aUVxy2Z9PMJSzLdZ7+6DVNWeBg64IRR0iFpX3q4LUXdzeX8BY63RbqzH2y3DI7by3 wP3LXFrJntqZV8nNhR/HKP2709xdLp5EV4CDlzqBYw7tIWwFT49caGyMNNnbE+5qKuRp +HwPRspjlCrkZABtl0MDGjvcAKF1L5XDwbC7akGMZIc9vxfADW9LcdhNM4VqyaPu2jah gPGA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=r91CXhNX; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:38:44 -0500 From: Michal Simek To: , , , CC: Andrew Davis , Ashok Reddy Soma , Geert Uytterhoeven , Krzysztof Kozlowski , Michael Tretter , Parth Gajjar , Rob Herring , Robert Hancock , "Vishal Sagar" , , Subject: [PATCH 18/23] arm64: zynqmp: Setup clock for DP and DPDMA Date: Tue, 2 May 2023 15:35:46 +0200 Message-ID: <807e22371394222f728ff7d6b190a96a12145439.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT075:EE_|MN2PR12MB4485:EE_ X-MS-Office365-Filtering-Correlation-Id: 77e02d32-4c35-4f63-dba1-08db4b129151 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7O9q3E25MMZp6VdWd8ozuBIFi6r8yTnTYKOYInXj6c8rcyyp/bG9wOZPGmBLnAANh/vptUS4Fdx5SurtXtTYdKWuvjdocRsy1oWsCO6rKDmStjtX3Iq7v9g4A8XcixMOOy4xKltIUByOkGL2PMU8L1dyqlWvrTvT8CydcqWn32tE7LgAur3PkyxElpovv8h79AaiZ8NWSAcNHcxpA71BqiRn9bUosbSpuL5sA5uI2Die3azYlqqOogDWm6LQhFRjmYN0epxHDEmLWDgQWYz1I0ttOWuMd+bMZIrw36tBfUKqhPRni+XGOC6FqJ+PQIW2sUJP+pDbSAnlRaK14XGhF3wyHbZZzSQfU9RQ0skAc9crGT5ZYNcPq+sbs9Ydnu6KbEnfy4jC6ZTilgNVvSX3Qa10Ss4kPMofD8ghxOZjjUP+UvHoBiiXNhh5M+kTvtkL8VJY+w1w37J0rxrxGwDDQ/gOdYkzECRsC6JZf9li/RQMj3mYl3JQdaAM9IzjUld4hOW0LOuh5O/RMO6jPehic5o0m/shhpNHXuTTzeVwb53lCaQL/EzYiPMAO1ZJxm3rghgFecNJ6NeThNCQ1etOUO2RlviJs3vmHjQomXU1Kdp8u4+jMvnhb5C0+ycXp9hO8LjQljit93252eBFww/m9GccbxoKMMWpleCsi5DYcXjlkc4QwZnkRmrTX+RbtT9SD6EqqPCw56zoGNdeTGCpGtAHiSLg/ofDqF2BCpB0mwGces7e0+JNIxCu9U7myo+w X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(346002)(39860400002)(376002)(451199021)(46966006)(40470700004)(36840700001)(44832011)(7416002)(2906002)(40460700003)(86362001)(82310400005)(41300700001)(4326008)(70586007)(70206006)(478600001)(316002)(5660300002)(110136005)(40480700001)(8676002)(8936002)(54906003)(82740400003)(36756003)(81166007)(356005)(26005)(16526019)(186003)(2616005)(83380400001)(47076005)(336012)(36860700001)(426003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:38:52.1831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77e02d32-4c35-4f63-dba1-08db4b129151 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT075.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4485 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790640484601554?= X-GMAIL-MSGID: =?utf-8?q?1764790640484601554?= Clocks are coming from shared HW design where these frequencies should be aligned with PLL setup. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 681885c9bcbb..581221fdadf1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -248,10 +248,14 @@ &xilinx_ams { &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; + assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&zynqmp_clk TOPSW_LSBUS>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; + assigned-clocks = <&zynqmp_clk DP_STC_REF>, + <&zynqmp_clk DP_AUDIO_REF>, + <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 817d756142ab..4f18b3efcced 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -99,10 +99,12 @@ &zynqmp_dpsub { status = "disabled"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index e07cec231ee0..77bc806b15a1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -80,10 +80,12 @@ &zynqmp_dpsub { status = "disabled"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { From patchwork Tue May 2 13:35:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89368 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp628607vqo; Tue, 2 May 2023 06:50:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6NK+ZPxyrKJxCDAfavyYNjBbHGrexHxMZ3iGZe0nSA2RW02ah4CQsulvT5bxGUiri7LkPL X-Received: by 2002:a05:6a00:1493:b0:63d:3411:f9e3 with SMTP id v19-20020a056a00149300b0063d3411f9e3mr26095151pfu.19.1683035434904; Tue, 02 May 2023 06:50:34 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035434; cv=pass; d=google.com; s=arc-20160816; b=jWHIzYJVp5MaLJ9taxhTUSkhz5cR2BQs3KblNFcReOj8q6eSeM0oxi/f6wgYsc8+PB N658o5Dnu4vnwbrSNIPZCw9kSpIph8DS0V3vSCmaz7+Q02K9r6J0Aw/vf3GExV4sgYON nLyuzbVCuAHMMC5nl9Ife4wJPAB2a2CVk+pzMHbCc/XLy3FxipzwxN4orEyOrwHmVCHp 56aFRr+5qIlHPaNr9yCm6du78lEDYAWZWfDMnJA8AW/6GQjMQEZgC+E9gVVshXlslmck BvBMBrJCVG/lPKKG/gbR8QM+CoPUg3zi6K+26kH0oXsk55W/NwdaydBFpZ0EQB+bQR9Q ByEw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6d7SN8DlIxoIw8h6ZkSGJGoGFY1TvwO1W0w0thzW8eE=; b=j4z4H36P/AP6TFxPFerCWmm+tIhrneBQ/DvPNcrMzfcaRnirFRRNhkugyZ4owi5ZFp FRAuSVtCH5erBsknpqML2IMY9nvztnO0Q82i8o4TOSnhQw3GpnBguEqvJnZOi1DHZQy9 RWKfJWJSwEV9HlSWLu7J4c/cGfkO5k6wPzDpjb1M3jMzOLZMcWKWu2ktDZLS7SwcbJwm OKp5F/k/sKlIL5rClxZsHQ6Qu31008SCc3lJ7FD/YwOJvivUZLVrBAw65EfHmuRbge5x eQagX4eS0BfFLvERziJgY9z/BLty8orr2iy/yWyl7A2W1PV2cYyhBLJ2uFTLBmTHNzJr zxmQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=XQlXcFYO; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:38:48 -0500 From: Michal Simek To: , , , CC: Andrew Davis , Ashok Reddy Soma , Geert Uytterhoeven , Krzysztof Kozlowski , Rob Herring , , Subject: [PATCH 19/23] arm64: zynqmp: Enable DP driver for SOMs Date: Tue, 2 May 2023 15:35:47 +0200 Message-ID: <15d16b4de933bfae108df6ca368eb2cdf916aa02.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT091:EE_|DM6PR12MB4482:EE_ X-MS-Office365-Filtering-Correlation-Id: 26fb8484-1436-41f7-b12c-08db4b129267 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xzMCtRhsCBp+u00CSekKkb9CcLfLerU2ApoFRNv8h0burdWBT/tbODWj5jDoy71qPLJ5c00Ntt5cCEIl2Ai5o90HIxGnkVOjsqjZCeX7zI1fKK+BpQ8OPtF0aQZEalcuTriM7jmU64IQomAO+N2Mcki4rBMFTeUY8vKy8BT/jqlKJL6PFYEjwd6Y5nGclWKDjwggWLfV3vI88RarueKVPbHHT58SNynsObzCvrtVP6dEIRpK3G7Ayyh0WYADhFgCHOOLJ+drp7Tuoszv67u1AryD4OZ7pIPkYw0Nml71IU8sofL4i6jXXBxgSOwLfxqv7c5/3t1j0daNsRAYVVO4g1wLnKWoDjrShd1KB6UrbeiDjQY0uR0TY/XeQ2uNOE4WuNh/0s+KazziOKg6cKMC3mWd9Alkttut0te1sBvhIVkV+KnQssIr3OHl6WrBsvfkyrj+zr5YLhsM16PDQNdbInwvyzu5Uigi/No4u7tnBl/BjK9dG8Qg/6zJo89+MUcIUvQBQwnVXuDyMVTHneOB957C0FH187yIjAb+W3vHSPaFgDHS3Jz4/MuNfKkFJSNcCQUSxxFg73pNgqH3i4mKw1zLR3LHf1vJK8H0DdnxGovyXYIOCiIanyIwlKpafElBa1rhnewkCPfvNhGIVPXQ2JR3ZDu4yoas1rYSIrhaJQxcrbGf4nnvH+tj5N3fiQWpuXMJKQyYQ/TR2HYbz52xwNcG8wGMFElRI2pFFcoySZwkbxPs7Uoh0/3rH2CUnXei X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199021)(40470700004)(46966006)(36840700001)(426003)(336012)(2616005)(26005)(41300700001)(70206006)(70586007)(36860700001)(81166007)(83380400001)(47076005)(16526019)(186003)(40460700003)(478600001)(54906003)(110136005)(82310400005)(44832011)(40480700001)(4326008)(316002)(82740400003)(356005)(2906002)(5660300002)(8676002)(7416002)(36756003)(86362001)(8936002)(36900700001)(2101003);DIR:OUT;SFP:1101; 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Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 4f18b3efcced..776444714fad 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -96,7 +96,7 @@ &sata { }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 77bc806b15a1..78d082a11492 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -77,7 +77,7 @@ &psgtr { }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; From patchwork Tue May 2 13:35:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89365 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp626941vqo; Tue, 2 May 2023 06:47:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7EnWq+ERBDZI1tnzBTIGc8u6c0ViG8XmLOfcW+5a1dbcqu8FfVk2V0ct8IGleMQxO9ydEb X-Received: by 2002:a05:6a00:1950:b0:63d:2911:3683 with SMTP id s16-20020a056a00195000b0063d29113683mr26724447pfk.17.1683035275795; Tue, 02 May 2023 06:47:55 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035275; cv=pass; d=google.com; s=arc-20160816; b=cBT8KIm67vpdYxS7HWdlXXHusM4/XQK/p1drRP1lxFurVgrBx5XQZPteucLyK6Pm2u gkXM5SqBg4JzXCpI6euLcuF+aI3syoq0Ohs4Jhu3/Gn/ELArXgZ7wnmFu0J+Kwkj0OoL hMCJijSZQCUucbqN6a68FxmvFAFM2VuEqRW7uL5G+xOSUTTGCSR6MqkVjKtT7yuXongG fBR5MzqjxAmpgebg3F82v+fkGZZLI0Uksl0Hf+HR9W50DTjsRGzi7AQvwdkRgVzPZc4r 156S3+Mz5pRIBzzOo9LhyWI0LpUhGkFQuj2SLgnTHhlAiF67BR+s9KvNIK5+7mR2WSEy UUhw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JlKA4lzSHjnUC0y7zo8ZQ6TN9spPSCrk4L2XerL+xI4=; b=yJ9h6v3sXlmpr7WjiqsQXl4sJLGvBQk57RcgNB3TOyTKBuwVxShvacDIAHuR8NTJ3a dT6KYJiiETzo9fMEi+YVrBXAm6eu9DcZ1cKX3ye78qNuYJUOTndv3oYdox32uGXehpYy q4xuI30P33bYDvD5idgMLeA4/EtTJX8+Ybgchyl4gm78cg+8fIL4lXsmfdHMAy4cB0dF iPNY/QcsNJh4sksWIMvGFPGccT2PGXCCoJYn+t738zYsWGlzXMWkydO9v0aiEaKio6an 3YyXJ06jjWfmk3O01A6UvaiWSP+A6+M/1E7abQwk+bDAqXmvDfGLlxWJW9jaejxYaMc9 ZynA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=O4e2gmGO; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Michal Simek Reviewed-by: Laurent Pinchart --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 7bd3e816226a..d01d4334c95f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -955,13 +955,13 @@ xilinx_ams: ams@ffa50000 { #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>; - ams_ps: ams_ps@0 { + ams_ps: ams-ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; }; - ams_pl: ams_pl@400 { + ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; From patchwork Tue May 2 13:35:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89374 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp628847vqo; Tue, 2 May 2023 06:50:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7gIfSksaVZlvM5Z02EbHuSuuSsazXiKN1Xy2N2Ap7BLAoA5cagxvH047VyUr9oD1cxojTW X-Received: by 2002:a05:6a20:938e:b0:f8:8879:747e with SMTP id x14-20020a056a20938e00b000f88879747emr23107365pzh.59.1683035458457; Tue, 02 May 2023 06:50:58 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035458; cv=pass; d=google.com; s=arc-20160816; b=hJQiHTjWNDAjYB652hvfzPaa9zGPEK9HIorYL5l6a8PiGg730RMQ8KqQUksEfhFhpl pD6RWONNRrwLZTpa7DK/cJsJl4oyN824t2k2vZQI8hvqYNH6qgOIY93MMCV2S0hsi8R5 CbovF4cUrsGPn2ioJ3UFdLpu2ckAhnDmB4/mDqr913MEkwQo7ylOEii29doXcbgpIPR6 qwyl/VqBQyBXYZ6HIwAtcOjHtOGzR6NZxZ9aQ9TfToCzVWyCjGmtjXywNEMe2HBjptAJ XXk3ciaszfVTyv7wBnX8Xq5Ou3QoHJQK3ckUMaQa8cdK8uws5wluL1K8+V3W55ZfGme9 x71Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=I66oDhtjnBAbpFeLWcmzAVm3wHlrwZ9f/pG3f+xCC0o=; b=jAUuhlp9hQ5aH0eG+KcYeMv4NuWeLPKti9h90lPm+1zxLY7O/g+5YslW8pBb35cRh2 DiBn2DDnlzqYLKL/hjzMcQKBWsgf/QWE1yZTJChfw86lyWhxhljmnMVOjg7n4CC2lijK JwTGO1PvGu7fjHNjd/25IA9cTAmAUcK6yNNeYPTO0XQPm9/9J7SOVn2Z0LYs5ix7MAnY 4hNkr00q8BBsGr2+3RZGpiLAk/zlY595x2m3afiB6QAlJSQcT00QQoabMrkGr6s8fuBl veMwzTLPLSN41s86fg7aGAAonZH02/Zjv0oHrl1+5mYBfdCgYI7xPa/n4PCe8PY1hf/5 BBnA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=1nKDoTQW; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:38:58.8834 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: badf0151-5cf8-4b1a-dca0-08db4b12954d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8146 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790588671763256?= X-GMAIL-MSGID: =?utf-8?q?1764790588671763256?= AMS is used for monitoring system. Used for measuring voltages and especially temperatures. Origin interface is IIO but via iio-hwmon it can be moved to hwmon framework too (done for SOM and zcu100). Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 26 +++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 17 ++++++++++++ .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 12 +++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 12 +++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 12 +++++++++ 5 files changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index e284979fd7b1..78ff6a9b3144 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -76,6 +76,20 @@ ds36-led { default-state = "on"; }; }; + + ams { + compatible = "iio-hwmon"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, + <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, + <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, + <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, + <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, + <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, + <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; + }; }; &modepin_gpio { @@ -327,6 +341,18 @@ &gpio { "", "", "", ""; /* 170 - 173 */ }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpsub { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index c99abb99efcb..c8be41d77cb9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -59,6 +59,15 @@ switch-4 { }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, + <&xilinx_ams 11>, <&xilinx_ams 12>; + }; + leds { compatible = "gpio-leds"; led-ds2 { @@ -581,6 +590,14 @@ &watchdog0 { status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 5b6403865541..b2e1f3581f6b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -1027,6 +1027,18 @@ &watchdog0 { status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index a74a2061431a..1f30c37c2e03 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -511,6 +511,18 @@ &watchdog0 { status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 73972d83ed4d..474744278b97 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -523,6 +523,18 @@ &watchdog0 { status = "okay"; }; +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; + &zynqmp_dpdma { status = "okay"; }; From patchwork Tue May 2 13:35:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89372 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp628810vqo; Tue, 2 May 2023 06:50:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5ImCK7YGXql2+EMFrHVUT3H3PhUlCu95P2FqQcNcnlhp9ACw1tHlpbcKRWHzwp7eMwAByz X-Received: by 2002:a05:6a20:914c:b0:f2:c2a3:39a with SMTP id x12-20020a056a20914c00b000f2c2a3039amr20635990pzc.61.1683035454470; Tue, 02 May 2023 06:50:54 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035454; cv=pass; d=google.com; s=arc-20160816; b=naj/9QaP/UeUC3Ml6/XMoesdMtTa2BWgTvXXV35JnxJ/mgfdHbNiGIstQEXVxZWFYi drN/gMiHLuWPG3kK1hbVP6L179m3uAYCciV7Omaf9YqYS75VlTd8t7ylAE5NcPazY0Od XHUCsM89UTX4pMmgiVpcdCi2dUkxk9R8CJNfN85sJeUzrU1lYqQ/93/NxBmEnphoAfhf rJIDKYs4+SwYaygVj72IbWtGD9xfo+NTNc0o3rmBQ8BiO0GgTBGYMKdZXyLGJI/A5Gfi ec6v6kUWbiobpday6dmIj4DUI8qmZn5mIZgiVwPG1U94WOc88Wkwh3Bvjo2xwfo5l9Cx aedA== ARC-Message-Signature: i=2; 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Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 776444714fad..dcc51b3adab0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -136,6 +136,7 @@ &sdhci1 { /* on CC with tuned parameters */ disable-wp; xlnx,mio-bank = <1>; assigned-clock-rates = <187498123>; + bus-width = <4>; }; &gem3 { /* required by spec */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 78d082a11492..3384df3d5920 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -119,6 +119,7 @@ &sdhci1 { /* on CC with tuned parameters */ clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; assigned-clock-rates = <187498123>; + bus-width = <4>; }; &gem3 { /* required by spec */ From patchwork Tue May 2 13:35:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 89367 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp628125vqo; Tue, 2 May 2023 06:49:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4zlKWsHOuc2On6CNCMxdMuWGbhqpjoEnZut0lT0p30HZGbRo08dwkJGN4NEdGgMewxKSid X-Received: by 2002:a05:6a20:8403:b0:f2:c1a9:ba2f with SMTP id c3-20020a056a20840300b000f2c1a9ba2fmr24424027pzd.25.1683035389272; Tue, 02 May 2023 06:49:49 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1683035389; cv=pass; d=google.com; s=arc-20160816; b=mBl2n46MWpw+inHAGF3vuAaQDwHCahERS8Y9IQlNhwKUKIwtxjZKXwRe/D5jNjyV5S 125odSEcOFNqSepXTn3/Z4wyVc2feCq2/mKoCJ1CoJbghRlEpdxyDEqB0kiCOp174bcX zbIzNvjAmoj9nODpmL9m76o7LDBzLI/7Cv14AKU/xlXkHHkqmWdxS1c+XZNjv7q6T5H1 WCjHMtYYndpl1pRpddhXSEZu/6sWoVdWYR6bUxABIUNh+4bKwqmncPDYE+WVGSTy56qi e1Gj28pfWmxUCxid2+klDWfDivaAKm6bYiT4J7eS6ecWpdzBvdgkAKTHAtP+1bj4CJwo 5BXQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nDyOsaEKWMexbMyEOdfZ3fg075U0MSF6yVl5CtldHHY=; b=02L3S8xWkazUWtgWPQrPZgPH8Uxy0BWZ2qDdiH5GIuyEzH+F/UtC1eaUcvv8hfcfrE LGb0HZQSP7M49ddU2oxuV1ECDYK6vTkvsW32MuJQktUQ3Dcdw5XCabXMzGE6eXsHXODh BdsIjQolYJ3kickThLf9aANql5uaaKB1AXEQdJQJgwhrA19LXJyIZoICwgfnkHKyYEWo 5A7tT4wyErZhVRcJQVLHktNNY0bGpIw1ckyOEIlCYbb9GRr0fwfQeprnLXROOhcOgYD2 tSsiVw8GwoSZf9PkMd0NexeVjEOjxmn+qBWIyjwgik5boU4MJ0jVVcD2bJonQHyrbGxs CNGw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=cmDGxzIA; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Tue, 2 May 2023 08:39:04 -0500 From: Michal Simek To: , , , CC: Amit Kumar Mahapatra , Harini Katakam , Krzysztof Kozlowski , Laurent Pinchart , Michael Grzeschik , Michael Tretter , Parth Gajjar , Piyush Mehta , Radhey Shyam Pandey , Rob Herring , Robert Hancock , "Sai Krishna Potthuri" , Srinivas Neeli , Tanmay Shah , Vishal Sagar , , Subject: [PATCH 23/23] arm64: zynqmp: Add phase tags marking Date: Tue, 2 May 2023 15:35:51 +0200 Message-ID: <48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT014:EE_|PH8PR12MB6697:EE_ X-MS-Office365-Filtering-Correlation-Id: 25618646-c487-4d76-9338-08db4b12a724 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 13:39:28.7962 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25618646-c487-4d76-9338-08db4b12a724 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6697 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764790516284898650?= X-GMAIL-MSGID: =?utf-8?q?1764790516284898650?= bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. Signed-off-by: Michal Simek --- --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 +++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 581221fdadf1..719ea5d5ae88 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -11,30 +11,35 @@ #include / { pss_ref_clk: pss_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -43,6 +48,7 @@ aux_ref_clk: aux_ref_clk { &zynqmp_firmware { zynqmp_clk: clock-controller { + bootph-all; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 78ff6a9b3144..8afdf4408a78 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -243,17 +243,20 @@ tpm@0 { /* slm9670 - U144 */ &i2c1 { status = "okay"; + bootph-all; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index d01d4334c95f..51b8349dcacd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -127,6 +127,7 @@ rproc_1_fw_image: memory@3ef00000 { }; zynqmp_ipi: zynqmp_ipi { + bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -136,6 +137,7 @@ zynqmp_ipi: zynqmp_ipi { ranges; ipi_mailbox_pmu1: mailbox@ff9905c0 { + bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, @@ -152,6 +154,7 @@ ipi_mailbox_pmu1: mailbox@ff9905c0 { dcc: dcc { compatible = "arm,dcc"; status = "disabled"; + bootph-all; }; pmu { @@ -177,8 +180,10 @@ zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; method = "smc"; + bootph-all; zynqmp_power: zynqmp-power { + bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -258,6 +263,7 @@ r5f-1 { amba: axi { compatible = "simple-bus"; + bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; @@ -699,6 +705,7 @@ pcie_intc: legacy-interrupt-controller { }; qspi: spi@ff0f0000 { + bootph-all; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; @@ -745,6 +752,7 @@ sata: ahci@fd0c0000 { }; sdhci0: mmc@ff160000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -759,6 +767,7 @@ sdhci0: mmc@ff160000 { }; sdhci1: mmc@ff170000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -851,6 +860,7 @@ ttc3: timer@ff140000 { }; uart0: serial@ff000000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -861,6 +871,7 @@ uart0: serial@ff000000 { }; uart1: serial@ff010000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -982,6 +993,7 @@ zynqmp_dpdma: dma-controller@fd4c0000 { }; zynqmp_dpsub: display@fd4a0000 { + bootph-all; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>,