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Peter Anvin" Subject: [PATCH v6 01/16] x86/mtrr: remove physical address size calculation Date: Tue, 2 May 2023 14:09:16 +0200 Message-Id: <20230502120931.20719-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785258659514726?= X-GMAIL-MSGID: =?utf-8?q?1764785258659514726?= The physical address width calculation in mtrr_bp_init() can easily be replaced with using the already available value x86_phys_bits from struct cpuinfo_x86. The same information source can be used in mtrr/cleanup.c, removing the need to pass that value on to mtrr_cleanup(). In print_mtrr_state() use x86_phys_bits instead of recalculating it from size_or_mask. Move setting of size_or_mask and size_and_mask into a dedicated new function in mtrr/generic.c, enabling to make those 2 variables static, as they are used in generic.c only now. Signed-off-by: Juergen Gross --- V6: - new patch, replacing former patches 1+2 --- arch/x86/kernel/cpu/mtrr/cleanup.c | 16 ++++---- arch/x86/kernel/cpu/mtrr/generic.c | 12 +++++- arch/x86/kernel/cpu/mtrr/mtrr.c | 61 ++++-------------------------- arch/x86/kernel/cpu/mtrr/mtrr.h | 4 +- 4 files changed, 29 insertions(+), 64 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c index b5f43049fa5f..70314093bb9b 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -173,7 +173,7 @@ early_param("mtrr_cleanup_debug", mtrr_cleanup_debug_setup); static void __init set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, - unsigned char type, unsigned int address_bits) + unsigned char type) { u32 base_lo, base_hi, mask_lo, mask_hi; u64 base, mask; @@ -183,7 +183,7 @@ set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, return; } - mask = (1ULL << address_bits) - 1; + mask = (1ULL << boot_cpu_data.x86_phys_bits) - 1; mask &= ~((((u64)sizek) << 10) - 1); base = ((u64)basek) << 10; @@ -209,7 +209,7 @@ save_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, range_state[reg].type = type; } -static void __init set_var_mtrr_all(unsigned int address_bits) +static void __init set_var_mtrr_all(void) { unsigned long basek, sizek; unsigned char type; @@ -220,7 +220,7 @@ static void __init set_var_mtrr_all(unsigned int address_bits) sizek = range_state[reg].size_pfn << (PAGE_SHIFT - 10); type = range_state[reg].type; - set_var_mtrr(reg, basek, sizek, type, address_bits); + set_var_mtrr(reg, basek, sizek, type); } } @@ -680,7 +680,7 @@ static int __init mtrr_search_optimal_index(void) return index_good; } -int __init mtrr_cleanup(unsigned address_bits) +int __init mtrr_cleanup(void) { unsigned long x_remove_base, x_remove_size; unsigned long base, size, def, dummy; @@ -742,7 +742,7 @@ int __init mtrr_cleanup(unsigned address_bits) mtrr_print_out_one_result(i); if (!result[i].bad) { - set_var_mtrr_all(address_bits); + set_var_mtrr_all(); pr_debug("New variable MTRRs\n"); print_out_mtrr_range_state(); return 1; @@ -786,7 +786,7 @@ int __init mtrr_cleanup(unsigned address_bits) gran_size = result[i].gran_sizek; gran_size <<= 10; x86_setup_var_mtrrs(range, nr_range, chunk_size, gran_size); - set_var_mtrr_all(address_bits); + set_var_mtrr_all(); pr_debug("New variable MTRRs\n"); print_out_mtrr_range_state(); return 1; @@ -802,7 +802,7 @@ int __init mtrr_cleanup(unsigned address_bits) return 0; } #else -int __init mtrr_cleanup(unsigned address_bits) +int __init mtrr_cleanup(void) { return 0; } diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index ee09d359e08f..3922552340b1 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -38,6 +38,16 @@ u64 mtrr_tom2; struct mtrr_state_type mtrr_state; EXPORT_SYMBOL_GPL(mtrr_state); +static u64 size_or_mask, size_and_mask; + +void __init mtrr_set_mask(void) +{ + unsigned int phys_addr = boot_cpu_data.x86_phys_bits; + + size_or_mask = ~GENMASK_ULL(phys_addr - PAGE_SHIFT - 1, 0); + size_and_mask = ~size_or_mask & GENMASK_ULL(39, 20); +} + /* * BIOS is expected to clear MtrrFixDramModEn bit, see for example * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD @@ -422,7 +432,7 @@ static void __init print_mtrr_state(void) } pr_debug("MTRR variable ranges %sabled:\n", mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); - high_width = (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4; + high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; for (i = 0; i < num_var_ranges; ++i) { if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 783f3210d582..1bdab16f16bd 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -67,8 +67,6 @@ static bool mtrr_enabled(void) unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; static DEFINE_MUTEX(mtrr_mutex); -u64 size_or_mask, size_and_mask; - const struct mtrr_ops *mtrr_if; /* Returns non-zero if we have the write-combining memory type */ @@ -619,77 +617,34 @@ static struct syscore_ops mtrr_syscore_ops = { int __initdata changed_by_mtrr_cleanup; -#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) /** - * mtrr_bp_init - initialize mtrrs on the boot CPU + * mtrr_bp_init - initialize MTRRs on the boot CPU * * This needs to be called early; before any of the other CPUs are * initialized (i.e. before smp_init()). - * */ void __init mtrr_bp_init(void) { const char *why = "(not available)"; - u32 phys_addr; - phys_addr = 32; + mtrr_set_mask(); - if (boot_cpu_has(X86_FEATURE_MTRR)) { + if (cpu_feature_enabled(X86_FEATURE_MTRR)) { mtrr_if = &generic_mtrr_ops; - size_or_mask = SIZE_OR_MASK_BITS(36); - size_and_mask = 0x00f00000; - phys_addr = 36; - - /* - * This is an AMD specific MSR, but we assume(hope?) that - * Intel will implement it too when they extend the address - * bus of the Xeon. - */ - if (cpuid_eax(0x80000000) >= 0x80000008) { - phys_addr = cpuid_eax(0x80000008) & 0xff; - /* CPUID workaround for Intel 0F33/0F34 CPU */ - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && - boot_cpu_data.x86 == 0xF && - boot_cpu_data.x86_model == 0x3 && - (boot_cpu_data.x86_stepping == 0x3 || - boot_cpu_data.x86_stepping == 0x4)) - phys_addr = 36; - - size_or_mask = SIZE_OR_MASK_BITS(phys_addr); - size_and_mask = ~size_or_mask & 0xfffff00000ULL; - } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && - boot_cpu_data.x86 == 6) { - /* - * VIA C* family have Intel style MTRRs, - * but don't support PAE - */ - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; - phys_addr = 32; - } } else { switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) { - /* Pre-Athlon (K6) AMD CPU MTRRs */ + /* Pre-Athlon (K6) AMD CPU MTRRs */ + if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) mtrr_if = &amd_mtrr_ops; - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; - } break; case X86_VENDOR_CENTAUR: - if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) { + if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) mtrr_if = ¢aur_mtrr_ops; - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; - } break; case X86_VENDOR_CYRIX: - if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) { + if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) mtrr_if = &cyrix_mtrr_ops; - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; - } break; default: break; @@ -703,7 +658,7 @@ void __init mtrr_bp_init(void) /* BIOS may override */ if (get_mtrr_state()) { memory_caching_control |= CACHE_MTRR; - changed_by_mtrr_cleanup = mtrr_cleanup(phys_addr); + changed_by_mtrr_cleanup = mtrr_cleanup(); } else { mtrr_if = NULL; why = "by BIOS"; diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h index 02eb5871492d..a00987e6cc1c 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -51,7 +51,6 @@ void fill_mtrr_var_range(unsigned int index, u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi); bool get_mtrr_state(void); -extern u64 size_or_mask, size_and_mask; extern const struct mtrr_ops *mtrr_if; #define is_cpu(vnd) (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd) @@ -60,6 +59,7 @@ extern unsigned int num_var_ranges; extern u64 mtrr_tom2; extern struct mtrr_state_type mtrr_state; +void mtrr_set_mask(void); void mtrr_state_warn(void); const char *mtrr_attrib_to_str(int x); void mtrr_wrmsr(unsigned, unsigned, unsigned); @@ -70,4 +70,4 @@ extern const struct mtrr_ops cyrix_mtrr_ops; extern const struct mtrr_ops centaur_mtrr_ops; extern int changed_by_mtrr_cleanup; -extern int mtrr_cleanup(unsigned address_bits); +extern int mtrr_cleanup(void); From patchwork Tue May 2 12:09:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89342 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp569283vqo; Tue, 2 May 2023 05:27:02 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6nGshIphpDbx/T0u37wiKbEW2QMzZs1VFP3iccqA1Si1P4VShyO6ylfZ5oRtDwKk0rQiC/ X-Received: by 2002:a17:90b:1c06:b0:24b:3295:3e23 with SMTP id oc6-20020a17090b1c0600b0024b32953e23mr17704955pjb.19.1683030422114; Tue, 02 May 2023 05:27:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030422; cv=none; d=google.com; s=arc-20160816; b=1JazQlJ2c+38MfoQqRanP+BsixhKOPBi1kvLgwtxujmKFANHOq06AMN/hHURo/S6o7 VS2Yb4zc+/b//TGlQf5kr/vRo7G9RyeNlKnZzdqh8dJVYJG8UKMFSlEn0pHraID9IeiD AwJ9qBaba+l/pnjJpvMZy4FmNG9pgr5KtCReSi7WdQNwQ2sw57L5OVl7fKOrnV3B35C4 +9rfrKjAXy3W9Y6pi7xJqlOsQSHh7PgAGebsURzZnvDir1QcZUrbT4geOqsCPo1qOeVq UCIpx3t45BYgP5mxXoT8NG4dqPTzHC35OpOvEKE0mcExxSZA8X4bQmOdpOvRLYyW2UBj +NTA== ARC-Message-Signature: i=1; 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Peter Anvin" Subject: [PATCH v6 02/16] x86/mtrr: replace some constants with defines Date: Tue, 2 May 2023 14:09:17 +0200 Message-Id: <20230502120931.20719-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785307961465103?= X-GMAIL-MSGID: =?utf-8?q?1764785307961465103?= Instead of using constants in MTRR code, use some new #defines. Replace size_or_mask and size_and_mask with the much easier concept of high reserved bits. Signed-off-by: Juergen Gross --- V5: - new patch (inspired by a request of Boris Petkov) V6: - switch macro names to match SDM nomenclature of MSRs (Boris Petkov) - replace size_or_mask and size_and_mask (Boris Petkov) --- arch/x86/include/asm/mtrr.h | 24 ++++++++++- arch/x86/kernel/cpu/mtrr/cleanup.c | 2 +- arch/x86/kernel/cpu/mtrr/generic.c | 68 +++++++++++++++--------------- arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +- 4 files changed, 59 insertions(+), 37 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index f0eeaf6e5f5f..15379aa41edc 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -23,8 +23,27 @@ #ifndef _ASM_X86_MTRR_H #define _ASM_X86_MTRR_H +#include #include +/* Defines for hardware MTRR registers. */ +#define MTRR_CAP_VCNT GENMASK(7, 0) +#define MTRR_CAP_FIX BIT_MASK(8) +#define MTRR_CAP_WC BIT_MASK(10) + +#define MTRR_DEF_TYPE_TYPE GENMASK(7, 0) +#define MTRR_DEF_TYPE_FE BIT_MASK(10) +#define MTRR_DEF_TYPE_E BIT_MASK(11) + +#define MTRR_DEF_TYPE_ENABLE (MTRR_DEF_TYPE_FE | MTRR_DEF_TYPE_E) +#define MTRR_DEF_TYPE_DISABLE ~(MTRR_DEF_TYPE_TYPE | MTRR_DEF_TYPE_ENABLE) + +#define MTRR_PHYSBASE_TYPE GENMASK(7, 0) +#define MTRR_PHYSBASE_RSVD GENMASK(11, 8) + +#define MTRR_PHYSMASK_RSVD GENMASK(10, 0) +#define MTRR_PHYSMASK_V BIT_MASK(11) + /* * The following functions are for use by other drivers that cannot use * arch_phys_wc_add and arch_phys_wc_del. @@ -121,7 +140,8 @@ struct mtrr_gentry32 { #endif /* CONFIG_COMPAT */ /* Bit fields for enabled in struct mtrr_state_type */ -#define MTRR_STATE_MTRR_FIXED_ENABLED 0x01 -#define MTRR_STATE_MTRR_ENABLED 0x02 +#define MTRR_STATE_SHIFT 10 +#define MTRR_STATE_MTRR_FIXED_ENABLED (MTRR_DEF_TYPE_FE >> MTRR_STATE_SHIFT) +#define MTRR_STATE_MTRR_ENABLED (MTRR_DEF_TYPE_E >> MTRR_STATE_SHIFT) #endif /* _ASM_X86_MTRR_H */ diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c index 70314093bb9b..ca2d567e729e 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -890,7 +890,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn) return 0; rdmsr(MSR_MTRRdefType, def, dummy); - def &= 0xff; + def &= MTRR_DEF_TYPE_TYPE; if (def != MTRR_TYPE_UNCACHABLE) return 0; diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 3922552340b1..ad2a396233c1 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -38,14 +38,13 @@ u64 mtrr_tom2; struct mtrr_state_type mtrr_state; EXPORT_SYMBOL_GPL(mtrr_state); -static u64 size_or_mask, size_and_mask; +static u32 phys_hi_rsvd; void __init mtrr_set_mask(void) { unsigned int phys_addr = boot_cpu_data.x86_phys_bits; - size_or_mask = ~GENMASK_ULL(phys_addr - PAGE_SHIFT - 1, 0); - size_and_mask = ~size_or_mask & GENMASK_ULL(39, 20); + phys_hi_rsvd = GENMASK(31, phys_addr - 32); } /* @@ -79,10 +78,9 @@ static u64 get_mtrr_size(u64 mask) { u64 size; - mask >>= PAGE_SHIFT; - mask |= size_or_mask; + mask |= (u64)phys_hi_rsvd << 32; size = -mask; - size <<= PAGE_SHIFT; + return size; } @@ -181,7 +179,7 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, for (i = 0; i < num_var_ranges; ++i) { unsigned short start_state, end_state, inclusive; - if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11))) + if (!(mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V)) continue; base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + @@ -233,7 +231,8 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, if ((start & mask) != (base & mask)) continue; - curr_match = mtrr_state.var_ranges[i].base_lo & 0xff; + curr_match = mtrr_state.var_ranges[i].base_lo & + MTRR_PHYSBASE_TYPE; if (prev_match == MTRR_TYPE_INVALID) { prev_match = curr_match; continue; @@ -435,7 +434,7 @@ static void __init print_mtrr_state(void) high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; for (i = 0; i < num_var_ranges; ++i) { - if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) + if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V) pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", i, high_width, @@ -444,7 +443,8 @@ static void __init print_mtrr_state(void) high_width, mtrr_state.var_ranges[i].mask_hi, mtrr_state.var_ranges[i].mask_lo >> 12, - mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff)); + mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & + MTRR_PHYSBASE_TYPE)); else pr_debug(" %u disabled\n", i); } @@ -462,7 +462,7 @@ bool __init get_mtrr_state(void) vrs = mtrr_state.var_ranges; rdmsr(MSR_MTRRcap, lo, dummy); - mtrr_state.have_fixed = (lo >> 8) & 1; + mtrr_state.have_fixed = !!(lo & MTRR_CAP_FIX); for (i = 0; i < num_var_ranges; i++) get_mtrr_var_range(i, &vrs[i]); @@ -470,8 +470,9 @@ bool __init get_mtrr_state(void) get_fixed_ranges(mtrr_state.fixed_ranges); rdmsr(MSR_MTRRdefType, lo, dummy); - mtrr_state.def_type = (lo & 0xff); - mtrr_state.enabled = (lo & 0xc00) >> 10; + mtrr_state.def_type = lo & MTRR_DEF_TYPE_TYPE; + mtrr_state.enabled = (lo & MTRR_DEF_TYPE_ENABLE) >> + MTRR_STATE_SHIFT; if (amd_special_default_mtrr()) { unsigned low, high; @@ -584,7 +585,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base, rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); - if ((mask_lo & 0x800) == 0) { + if ((mask_lo & MTRR_PHYSMASK_V) == 0) { /* Invalid (i.e. free) range */ *base = 0; *size = 0; @@ -595,8 +596,8 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base, rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); /* Work out the shifted address mask: */ - tmp = (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT; - mask = size_or_mask | tmp; + tmp = (u64)mask_hi << 32 | (mask_lo & PAGE_MASK); + mask = (u64)phys_hi_rsvd << 32 | tmp; /* Expand tmp with high bits to all 1s: */ hi = fls64(tmp); @@ -614,9 +615,9 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base, * This works correctly if size is a power of two, i.e. a * contiguous range: */ - *size = -mask; + *size = -mask >> PAGE_SHIFT; *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; - *type = base_lo & 0xff; + *type = base_lo & MTRR_PHYSBASE_TYPE; out_put_cpu: put_cpu(); @@ -654,9 +655,8 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) bool changed = false; rdmsr(MTRRphysBase_MSR(index), lo, hi); - if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL) - || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != - (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { + if ((vr->base_lo & MTRR_PHYSBASE_RSVD) != (lo & MTRR_PHYSBASE_RSVD) + || (vr->base_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) { mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); changed = true; @@ -664,9 +664,8 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) rdmsr(MTRRphysMask_MSR(index), lo, hi); - if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL) - || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != - (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { + if ((vr->mask_lo & MTRR_PHYSMASK_RSVD) != (lo & MTRR_PHYSMASK_RSVD) + || (vr->mask_hi & ~phys_hi_rsvd) != (hi & ~phys_hi_rsvd)) { mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); changed = true; } @@ -701,11 +700,13 @@ static unsigned long set_mtrr_state(void) * Set_mtrr_restore restores the old value of MTRRdefType, * so to set it we fiddle with the saved value: */ - if ((deftype_lo & 0xff) != mtrr_state.def_type - || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) { + if ((deftype_lo & MTRR_DEF_TYPE_TYPE) != mtrr_state.def_type + || ((deftype_lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) != + mtrr_state.enabled) { - deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type | - (mtrr_state.enabled << 10); + deftype_lo = (deftype_lo & MTRR_DEF_TYPE_DISABLE) | + mtrr_state.def_type | + (mtrr_state.enabled << MTRR_STATE_SHIFT); change_mask |= MTRR_CHANGE_MASK_DEFTYPE; } @@ -718,7 +719,8 @@ void mtrr_disable(void) rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); /* Disable MTRRs, and set the default type to uncached */ - mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); + mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, + deftype_hi); } void mtrr_enable(void) @@ -772,9 +774,9 @@ static void generic_set_mtrr(unsigned int reg, unsigned long base, memset(vr, 0, sizeof(struct mtrr_var_range)); } else { vr->base_lo = base << PAGE_SHIFT | type; - vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); - vr->mask_lo = -size << PAGE_SHIFT | 0x800; - vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT); + vr->base_hi = (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; + vr->mask_lo = -size << PAGE_SHIFT | MTRR_PHYSMASK_V; + vr->mask_hi = (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); @@ -827,7 +829,7 @@ static int generic_have_wrcomb(void) { unsigned long config, dummy; rdmsr(MSR_MTRRcap, config, dummy); - return config & (1 << 10); + return config & MTRR_CAP_WC; } int positive_have_wrcomb(void) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 1bdab16f16bd..fddc4e0c6626 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -115,7 +115,7 @@ static void __init set_num_var_ranges(bool use_generic) else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) config = 8; - num_var_ranges = config & 0xff; + num_var_ranges = config & MTRR_CAP_VCNT; } static void __init init_table(void) From patchwork Tue May 2 12:09:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89325 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp565854vqo; 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Peter Anvin" Subject: [PATCH v6 03/16] x86/mtrr: support setting MTRR state for software defined MTRRs Date: Tue, 2 May 2023 14:09:18 +0200 Message-Id: <20230502120931.20719-4-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764784966824313938?= X-GMAIL-MSGID: =?utf-8?q?1764784966824313938?= When running virtualized, MTRR access can be reduced (e.g. in Xen PV guests or when running as a SEV-SNP guest under Hyper-V). Typically the hypervisor will reset the MTRR feature in CPUID data, resulting in no MTRR memory type information being available for the kernel. This has turned out to result in problems: - Hyper-V SEV-SNP guests using uncached mappings where they shouldn't - Xen PV dom0 mapping memory as WB which should be UC- instead Solve those problems allowing an MTRR static state override, overwriting the empty state used today. In case such a state has been set, don't call get_mtrr_state() in mtrr_bp_init(). The set state will only be used by mtrr_type_lookup(), as in all other cases mtrr_enabled() is being checked, which will return false. Accept the overwrite call only for selected cases when running as a guest. Disable X86_FEATURE_MTRR in order to avoid any MTRR modifications by just refusing them. Link: https://lore.kernel.org/lkml/BYAPR21MB16883ABC186566BD4D2A1451D7FE9@BYAPR21MB1688.namprd21.prod.outlook.com/ Link: https://lore.kernel.org/all/4fe9541e-4d4c-2b2a-f8c8-2d34a7284930@nerdbynature.de/ Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch V3: - omit fixed MTRRs, as those are currently not needed - disable X86_FEATURE_MTRR instead of testing it - provide a stub for !CONFIG_MTRR (Michael Kelley) - use cpu_feature_enabled() (Boris Petkov) - add tests for mtrr_overwrite_state() being allowed (Boris Petkov) V4: - add test for hv_is_isolation_supported() (Michael Kelley) V5: - drop test for running as native (Boris Petkov) - split large complex test into multiple simple ones (Boris Petkov) - enhance test in mtrr_bp_init() (Boris Petkov) V6: - expand comments (Kai Huang) - add links to commit message (Boris Petkov) --- arch/x86/include/asm/mtrr.h | 8 ++++ arch/x86/kernel/cpu/mtrr/generic.c | 60 +++++++++++++++++++++++++++++- arch/x86/kernel/cpu/mtrr/mtrr.c | 14 ++++++- arch/x86/kernel/setup.c | 2 + 4 files changed, 82 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 15379aa41edc..9837fe34e58b 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -50,6 +50,8 @@ */ # ifdef CONFIG_MTRR void mtrr_bp_init(void); +void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, + mtrr_type def_type); extern u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform); extern void mtrr_save_fixed_ranges(void *); extern void mtrr_save_state(void); @@ -67,6 +69,12 @@ void mtrr_disable(void); void mtrr_enable(void); void mtrr_generic_set_state(void); # else +static inline void mtrr_overwrite_state(struct mtrr_var_range *var, + unsigned int num_var, + mtrr_type def_type) +{ +} + static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform) { /* diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index ad2a396233c1..29e3bf921f26 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -8,10 +8,12 @@ #include #include #include - +#include #include #include #include +#include +#include #include #include #include @@ -249,6 +251,62 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, return mtrr_state.def_type; } +/** + * mtrr_overwrite_state - set static MTRR state + * + * Used to set MTRR state via different means (e.g. with data obtained from + * a hypervisor). + * Is allowed only for special cases when running virtualized. Must be called + * from the x86_init.hyper.init_platform() hook. It can be called only once. + * The MTRR state can't be changed afterwards. To ensure that, X86_FEATURE_MTRR + * is cleared. + */ +void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, + mtrr_type def_type) +{ + unsigned int i; + + /* Only allowed to be called once before mtrr_bp_init(). */ + if (WARN_ON(mtrr_state_set)) + return; + + /* Only allowed when running virtualized. */ + if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) + return; + + /* + * Only allowed for special virtualization cases: + * - when running as Hyper-V, SEV-SNP guest using vTOM + * - when running as Xen PV guest + * - when running as SEV-SNP or TDX guest to avoid unnecessary + * VMM communication/Virtualization exceptions (#VC, #VE) + */ + if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && + !hv_is_isolation_supported() && + !cpu_feature_enabled(X86_FEATURE_XENPV) && + !cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return; + + /* Disable MTRR in order to disable MTRR modifications. */ + setup_clear_cpu_cap(X86_FEATURE_MTRR); + + if (var) { + if (num_var > MTRR_MAX_VAR_RANGES) { + pr_warn("Trying to overwrite MTRR state with %u variable entries\n", + num_var); + num_var = MTRR_MAX_VAR_RANGES; + } + for (i = 0; i < num_var; i++) + mtrr_state.var_ranges[i] = var[i]; + num_var_ranges = num_var; + } + + mtrr_state.def_type = def_type; + mtrr_state.enabled |= MTRR_STATE_MTRR_ENABLED; + + mtrr_state_set = 1; +} + /** * mtrr_type_lookup - look up memory type in MTRR * diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index fddc4e0c6626..9173ed396508 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -625,11 +625,23 @@ int __initdata changed_by_mtrr_cleanup; */ void __init mtrr_bp_init(void) { + bool generic_mtrrs = cpu_feature_enabled(X86_FEATURE_MTRR); const char *why = "(not available)"; mtrr_set_mask(); - if (cpu_feature_enabled(X86_FEATURE_MTRR)) { + if (!generic_mtrrs && mtrr_state.enabled) { + /* + * Software overwrite of MTRR state, only for generic case. + * Note that X86_FEATURE_MTRR has been reset in this case. + */ + init_table(); + pr_info("MTRRs set to read-only\n"); + + return; + } + + if (generic_mtrrs) { mtrr_if = &generic_mtrr_ops; } else { switch (boot_cpu_data.x86_vendor) { diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 16babff771bd..0cccfeb67c3a 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1037,6 +1037,8 @@ void __init setup_arch(char **cmdline_p) /* * VMware detection requires dmi to be available, so this * needs to be done after dmi_setup(), for the boot CPU. + * For some guest types (Xen PV, SEV-SNP, TDX) it is required to be + * called before cache_bp_init() for setting up MTRR state. */ init_hypervisor_platform(); From patchwork Tue May 2 12:09:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89335 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp568448vqo; Tue, 2 May 2023 05:25:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7u+gB3Ghj4kKTmc2X53lOZKat8ejYU/Avq/Fm/quyZcyRLIBzE4f6EtbopICP30LuXiVdR X-Received: by 2002:a05:6a20:244c:b0:f5:9f72:1aaa with SMTP id t12-20020a056a20244c00b000f59f721aaamr22982497pzc.19.1683030334752; Tue, 02 May 2023 05:25:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030334; cv=none; d=google.com; s=arc-20160816; b=Rsuk+wI9lSGqFvVzCCLA6sP+OJIZXCfB9x5Q4763jgHFLlh7lZCQkhf2K+uyCCVdFB f8f6EzbdbXFEV0XuEU9Opv72EPKYjsrUC+LIYn4R0YgWaNVVhFO6UA+AJl7muMmTV+JQ vFwvyzccoUKfE3yJxZDJxHmKrnl37d2Nd3x9SYZ6vRgLSoTz+9bSujJxgne9QtViSdYw wkE7Xc70cSrHKeiuF0B9sSJgEblljC6hINXW+JIt/gzJv9d/gwypPvn70SvNNbGh85Zg I2OERPY9aNXFxaq70oqx1LcDITVVEqISddDNokX79aCB0HeMv/GCfmSIpZIP/BJzh5SM HG8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=x+93RA8T9/i6FC7Kr/U0Px8+1fxaBL/HiuMzaqxIQlk=; b=J/Ul3XPHPbhtmXtSuEkezOwnbe5GPAfzojOUyg8KF7uFNhhCMIFKqEysxecxbolE+w h0RNbv9FAeA42srX91KKTwkntClVp/NlY9Tp4wetJd6LcEdKW+J7KG86ZqilR1PFqLRf UhtM6mI2Kv1J27UjRdzAChshWV/G3ValJJMwHRG4xZLIN80McLvpTlZM2R2CYejSpwkn 1/ba7X2oekbdccG+IkEyglpsLHyowh3TdJit1vMSeXsdFzz+boM7MOXb+fzZa9pxTx44 R/LcYcOyrUKDchTtsSFYYBSFkl5tymrdoTe9jABWnFnIIM9Vm2LunbfxDkQy6rcafaaT 718g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=l9zLqPfr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v6 04/16] x86/hyperv: set MTRR state when running as SEV-SNP Hyper-V guest Date: Tue, 2 May 2023 14:09:19 +0200 Message-Id: <20230502120931.20719-5-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785216457862238?= X-GMAIL-MSGID: =?utf-8?q?1764785216457862238?= In order to avoid mappings using the UC- cache attribute, set the MTRR state to use WB caching as the default. This is needed in order to cope with the fact that PAT is enabled, while MTRRs are not supported by the hypervisor. Fixes: 90b926e68f50 ("x86/pat: Fix pat_x_mtrr_type() for MTRR disabled case") Signed-off-by: Juergen Gross --- V2: - new patch V6: - rebase to tip/master, move code to hv_vtom_init() (Michael Kelley) --- arch/x86/hyperv/ivm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index cc92388b7a99..6f7c1b5606ad 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -17,6 +17,7 @@ #include #include #include +#include #ifdef CONFIG_AMD_MEM_ENCRYPT @@ -372,6 +373,9 @@ void __init hv_vtom_init(void) x86_platform.guest.enc_cache_flush_required = hv_vtom_cache_flush_required; x86_platform.guest.enc_tlb_flush_required = hv_vtom_tlb_flush_required; x86_platform.guest.enc_status_change_finish = hv_vtom_set_host_visibility; + + /* Set WB as the default cache mode. */ + mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK); } #endif /* CONFIG_AMD_MEM_ENCRYPT */ From patchwork Tue May 2 12:09:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89334 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp568056vqo; Tue, 2 May 2023 05:24:57 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7v4xhpEVm9rLGiyISmdcGH+isG6nY3kwLM6VR8GQ6HNh3ncNtN+hglOlhcw6i5HAwUwaqN X-Received: by 2002:a05:6a20:c892:b0:ef:ef3d:6166 with SMTP id hb18-20020a056a20c89200b000efef3d6166mr17394329pzb.32.1683030297140; Tue, 02 May 2023 05:24:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030297; cv=none; d=google.com; s=arc-20160816; b=Krzan4T2SY+BVPWl7w2Vyd2arYpYI8TeIxTZzmwI8vkQkl/6e/lPoDL2LoZUG0/g0n tEq+k6ObId08w7i3dYuQd3MZ/GghIGaMiI3PL/WKAcoMp6+HR3CVUsNYbQJ5sWBIijip Nw5XL7up4qwxHaQ7rYzVk/V7lqf+4OFLsWkQis2Nu0EBCXa55Vv7bevs0TauE13s59yM rAqg463UpF1NlTI2lnN7lSUrcv8Ey/qffx6yMqASR0CDeFi8vzzDhRYLjPT74LNx7GxS aosf9dzzSn9+qhQUQkank0Bb2RU0GzL0+5US23yfVbY5DtE5flPKPoIsGwvfP5fV4YUy vosA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RMQn8Yiv0jCwQnecK3T9cC+8gstSs8Pnq7WDZyHBVNw=; b=jNZ0UEehYYPHqPktBeYdzi1d9zFbcnM/v2nAEHQYXHTbIBuREg/ye4VAWXW0jNLfSz 91P/PbPdzVyTFUEN+mOsMNxdqBV6UmGwGDOsjVsSSjdILwpt/G2O8AOII32OlCm0/mzG 5Ypb7Xqx1M9okgtWYyU1idQ0u9EJqY2vqzV4CwiHaOrG0uzfGb/T4lv72P5G4nBm2X2m ZC6Le8lN4hMKbq4VTJfbh1rBcjoUIoZdpoXWuvam29hMlB6HZKpDds2DXPEoeMclXJtM VS4gAwIhiPra8ZHmF+rhqGmtAtCdOFEjITQ8URNUtY/aVFhaDiwSs1rzrbZBsNQAlT30 l9TA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=UthapKSl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , xen-devel@lists.xenproject.org Subject: [PATCH v6 05/16] x86/xen: set MTRR state when running as Xen PV initial domain Date: Tue, 2 May 2023 14:09:20 +0200 Message-Id: <20230502120931.20719-6-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785177193448892?= X-GMAIL-MSGID: =?utf-8?q?1764785177193448892?= When running as Xen PV initial domain (aka dom0), MTRRs are disabled by the hypervisor, but the system should nevertheless use correct cache memory types. This has always kind of worked, as disabled MTRRs resulted in disabled PAT, too, so that the kernel avoided code paths resulting in inconsistencies. This bypassed all of the sanity checks the kernel is doing with enabled MTRRs in order to avoid memory mappings with conflicting memory types. This has been changed recently, leading to PAT being accepted to be enabled, while MTRRs stayed disabled. The result is that mtrr_type_lookup() no longer is accepting all memory type requests, but started to return WB even if UC- was requested. This led to driver failures during initialization of some devices. In reality MTRRs are still in effect, but they are under complete control of the Xen hypervisor. It is possible, however, to retrieve the MTRR settings from the hypervisor. In order to fix those problems, overwrite the MTRR state via mtrr_overwrite_state() with the MTRR data from the hypervisor, if the system is running as a Xen dom0. Fixes: 72cbc8f04fe2 ("x86/PAT: Have pat_enabled() properly reflect state when running on Xen") Signed-off-by: Juergen Gross Reviewed-by: Boris Ostrovsky --- V2: - new patch V3: - move the call of mtrr_overwrite_state() to xen_pv_init_platform() V4: - only call mtrr_overwrite_state() if any MTRR got from Xen (Boris Ostrovsky) --- arch/x86/xen/enlighten_pv.c | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 093b78c8bbec..8732b85d5650 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -68,6 +68,7 @@ #include #include #include +#include #include #include #include @@ -119,6 +120,54 @@ static int __init parse_xen_msr_safe(char *str) } early_param("xen_msr_safe", parse_xen_msr_safe); +/* Get MTRR settings from Xen and put them into mtrr_state. */ +static void __init xen_set_mtrr_data(void) +{ +#ifdef CONFIG_MTRR + struct xen_platform_op op = { + .cmd = XENPF_read_memtype, + .interface_version = XENPF_INTERFACE_VERSION, + }; + unsigned int reg; + unsigned long mask; + uint32_t eax, width; + static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata; + + /* Get physical address width (only 64-bit cpus supported). */ + width = 36; + eax = cpuid_eax(0x80000000); + if ((eax >> 16) == 0x8000 && eax >= 0x80000008) { + eax = cpuid_eax(0x80000008); + width = eax & 0xff; + } + + for (reg = 0; reg < MTRR_MAX_VAR_RANGES; reg++) { + op.u.read_memtype.reg = reg; + if (HYPERVISOR_platform_op(&op)) + break; + + /* + * Only called in dom0, which has all RAM PFNs mapped at + * RAM MFNs, and all PCI space etc. is identity mapped. + * This means we can treat MFN == PFN regarding MTRR settings. + */ + var[reg].base_lo = op.u.read_memtype.type; + var[reg].base_lo |= op.u.read_memtype.mfn << PAGE_SHIFT; + var[reg].base_hi = op.u.read_memtype.mfn >> (32 - PAGE_SHIFT); + mask = ~((op.u.read_memtype.nr_mfns << PAGE_SHIFT) - 1); + mask &= (1UL << width) - 1; + if (mask) + mask |= MTRR_PHYSMASK_V; + var[reg].mask_lo = mask; + var[reg].mask_hi = mask >> 32; + } + + /* Only overwrite MTRR state if any MTRR could be got from Xen. */ + if (reg) + mtrr_overwrite_state(var, reg, MTRR_TYPE_UNCACHABLE); +#endif +} + static void __init xen_pv_init_platform(void) { /* PV guests can't operate virtio devices without grants. */ @@ -135,6 +184,9 @@ static void __init xen_pv_init_platform(void) /* pvclock is in shared info area */ xen_init_time_ops(); + + if (xen_initial_domain()) + xen_set_mtrr_data(); } static void __init xen_pv_guest_late_init(void) From patchwork Tue May 2 12:09:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89341 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp568984vqo; Tue, 2 May 2023 05:26:30 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ44V+9iRhDbYZVht4aom0M9YRDlClvtWL73dVO83ST754LWeQxacOO8CcG/6ZXQ7T3Yk2Yu X-Received: by 2002:a17:902:db09:b0:1a6:8405:f709 with SMTP id m9-20020a170902db0900b001a68405f709mr22409708plx.20.1683030390197; Tue, 02 May 2023 05:26:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030390; cv=none; d=google.com; s=arc-20160816; b=tipi2L+ze6I834vUKIBYgJLq1UsIikjs+u3jsUMRE2he26Bjn9eH91xgMwLCSdLw4a KbaJjEcysRftYCDPQLGFA705n/MnHg7zPMJRRWpxV0VmAr9cbFhf/y4JOpxJu3Ivwjur 9D803/B6Ea/BUBH9AcfHX9uS5hF6Oc3I9ZxXdLhay4GTYKpDz3IFHKEWRk+6YAUR8wAY hoZ7ydcHYCekBvNEcgjRYifyrj6wNOmPifAIDNV84/tVuIvjPz9GQHArFCMtZZ2jTCwA 3WJ0JAxF+zWirDk8+H9O2+E8J6mAAvGsvIwf/q1kgKWq1G0H+VHXaOUS99KgEo/dixDR B45Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+octWkaBW/Cq5hvCrSMdqrEz1zk0Nu2faf89YlvGji4=; b=fPyggIEyUq/Bpcs9BcE0iHwTPrxHiZ+/V2EvUFDuFmlvhuZnsGu0rGX9DeNcZptoI8 wwvfo7lF4oKFdsDxpwY75+bs71wctVArwdG906aRwkjsFL6MD+Z1EtQzYJTbJHl9pR0M 3Lto/SVZya3Jnj4lIr+H7lySDb2i9spaDfRVpwo4je/NfSXvS7MurfTFTfLB7Nq90hDw E6J2uAHTbb0lGTm/ONvPArg/daWb0LnVDLSV67ovR3ETCC4E28D1maaLmX1sjl1Fv5/y p69yLRrlRg/u8xOu2XnWlOAtYBQxyGdAuIPYIFiScI2BjcafDl6D4ft5rGfeQ8E12Nb3 7IRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=IR+CoEls; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v6 06/16] x86/mtrr: replace vendor tests in MTRR code Date: Tue, 2 May 2023 14:09:21 +0200 Message-Id: <20230502120931.20719-7-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785274229596518?= X-GMAIL-MSGID: =?utf-8?q?1764785274229596518?= Modern CPUs all share the same MTRR interface implemented via generic_mtrr_ops. At several places in MTRR code this generic interface is deduced via is_cpu(INTEL) tests, which is only working due to X86_VENDOR_INTEL being 0 (the is_cpu() macro is testing mtrr_if->vendor, which isn't explicitly set in generic_mtrr_ops). Test the generic CPU feature X86_FEATURE_MTRR instead. The only other place where the .vendor member of struct mtrr_ops is being used is in set_num_var_ranges(), where depending on the vendor the number of MTRR registers is determined. This can easily be changed by replacing .vendor with the static number of MTRR registers. It should be noted that the test "is_cpu(HYGON)" wasn't ever returning true, as there is no struct mtrr_ops with that vendor information. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V4: - use cpu_feature_enabled(X86_FEATURE_MTRR) for testing generic MTRRs (Boris Petkov) V6: - eliminate set_num_var_ranges() (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/amd.c | 2 +- arch/x86/kernel/cpu/mtrr/centaur.c | 2 +- arch/x86/kernel/cpu/mtrr/cleanup.c | 4 ++-- arch/x86/kernel/cpu/mtrr/cyrix.c | 2 +- arch/x86/kernel/cpu/mtrr/generic.c | 2 +- arch/x86/kernel/cpu/mtrr/mtrr.c | 24 ++++++++---------------- arch/x86/kernel/cpu/mtrr/mtrr.h | 4 +--- 7 files changed, 15 insertions(+), 25 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c index eff6ac62c0ff..ef3e8e42b782 100644 --- a/arch/x86/kernel/cpu/mtrr/amd.c +++ b/arch/x86/kernel/cpu/mtrr/amd.c @@ -110,7 +110,7 @@ amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type) } const struct mtrr_ops amd_mtrr_ops = { - .vendor = X86_VENDOR_AMD, + .var_regs = 2, .set = amd_set_mtrr, .get = amd_get_mtrr, .get_free_region = generic_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/centaur.c index b8a74eddde83..4466ddeb0125 100644 --- a/arch/x86/kernel/cpu/mtrr/centaur.c +++ b/arch/x86/kernel/cpu/mtrr/centaur.c @@ -112,7 +112,7 @@ centaur_validate_add_page(unsigned long base, unsigned long size, unsigned int t } const struct mtrr_ops centaur_mtrr_ops = { - .vendor = X86_VENDOR_CENTAUR, + .var_regs = 8, .set = centaur_set_mcr, .get = centaur_get_mcr, .get_free_region = centaur_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c index ca2d567e729e..4a979086f00e 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -689,7 +689,7 @@ int __init mtrr_cleanup(void) int index_good; int i; - if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1) + if (!cpu_feature_enabled(X86_FEATURE_MTRR) || enable_mtrr_cleanup < 1) return 0; rdmsr(MSR_MTRRdefType, def, dummy); @@ -886,7 +886,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn) * Make sure we only trim uncachable memory on machines that * support the Intel MTRR architecture: */ - if (!is_cpu(INTEL) || disable_mtrr_trim) + if (!cpu_feature_enabled(X86_FEATURE_MTRR) || disable_mtrr_trim) return 0; rdmsr(MSR_MTRRdefType, def, dummy); diff --git a/arch/x86/kernel/cpu/mtrr/cyrix.c b/arch/x86/kernel/cpu/mtrr/cyrix.c index 173b9e01e623..238dad57d4d6 100644 --- a/arch/x86/kernel/cpu/mtrr/cyrix.c +++ b/arch/x86/kernel/cpu/mtrr/cyrix.c @@ -235,7 +235,7 @@ static void cyrix_set_arr(unsigned int reg, unsigned long base, } const struct mtrr_ops cyrix_mtrr_ops = { - .vendor = X86_VENDOR_CYRIX, + .var_regs = 8, .set = cyrix_set_arr, .get = cyrix_get_arr, .get_free_region = cyrix_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 29e3bf921f26..cd887327ba3a 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -853,7 +853,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size, * For Intel PPro stepping <= 7 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF */ - if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 && + if (mtrr_if == &generic_mtrr_ops && boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 1 && boot_cpu_data.x86_stepping <= 7) { if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 9173ed396508..3351730447e1 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -103,21 +103,6 @@ static int have_wrcomb(void) return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0; } -/* This function returns the number of variable MTRRs */ -static void __init set_num_var_ranges(bool use_generic) -{ - unsigned long config = 0, dummy; - - if (use_generic) - rdmsr(MSR_MTRRcap, config, dummy); - else if (is_cpu(AMD) || is_cpu(HYGON)) - config = 2; - else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) - config = 8; - - num_var_ranges = config & MTRR_CAP_VCNT; -} - static void __init init_table(void) { int i, max; @@ -627,6 +612,7 @@ void __init mtrr_bp_init(void) { bool generic_mtrrs = cpu_feature_enabled(X86_FEATURE_MTRR); const char *why = "(not available)"; + unsigned long config, dummy; mtrr_set_mask(); @@ -664,7 +650,13 @@ void __init mtrr_bp_init(void) } if (mtrr_enabled()) { - set_num_var_ranges(mtrr_if == &generic_mtrr_ops); + /* Get the number of variable MTRR ranges. */ + if (mtrr_if == &generic_mtrr_ops) + rdmsr(MSR_MTRRcap, config, dummy); + else + config = mtrr_if->var_regs; + num_var_ranges = config & MTRR_CAP_VCNT; + init_table(); if (mtrr_if == &generic_mtrr_ops) { /* BIOS may override */ diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h index a00987e6cc1c..0dd11e41baa6 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -13,7 +13,7 @@ extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; struct mtrr_ops { - u32 vendor; + u32 var_regs; void (*set)(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type); void (*get)(unsigned int reg, unsigned long *base, @@ -53,8 +53,6 @@ bool get_mtrr_state(void); extern const struct mtrr_ops *mtrr_if; -#define is_cpu(vnd) (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd) - extern unsigned int num_var_ranges; extern u64 mtrr_tom2; extern struct mtrr_state_type mtrr_state; From patchwork Tue May 2 12:09:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89333 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp567892vqo; Tue, 2 May 2023 05:24:41 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5C1xBtznomSAp1yHto1pSM9gPVW5tvnRGojdsMF03CbDSpVVxvdjDahiFnQF7X3j2SEXV4 X-Received: by 2002:a05:6a20:d709:b0:f2:4c39:8031 with SMTP id iz9-20020a056a20d70900b000f24c398031mr17836619pzb.34.1683030281370; Tue, 02 May 2023 05:24:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030281; cv=none; d=google.com; s=arc-20160816; b=XG6gvYrLxIJFYIy9KBf5gD6JlF1fshIWfUAhu1OnWl7Il38dYqhIWoraREE6pT0bnK edNIFuLPn+jrZCNSswBALt8txhMqMD2EY0fd6OhA1QmlRWMtiTcYDfMNekMGy/LMrEpg gLEMrrNQyCrCr8Sagfw4hu79fiVn9bdk+nRTEmWxvADIAkoPmn3qkBBs8LTqwiTyTeXB RRBNCKXa2ya4wj9TnvXVtqxltCSZ4XAHHnwN1YVXA6H9lVmjHwseZwl86yUhsjm6FuWE YT1t43/UiHh/wFByRTDbKaaRkAOjDcVVBv16iTSx6QTAwK6FPGGyMr3n32xDkbn7Lr7S 24Nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DgCRNXz0bs0WvceUdREg7f7DvaWPhgAqi3kLd7uuhq0=; b=yQ6VfiryFr95EeEh9mbI3vwOdje/cBM1wyo0kl5OMb94F0w/UZ/h/BQESNQ+1Y4REC cU6eGSaTFU1fisGzDqN71WnV8yh/bZebO07pS/qoLV7YOUm1iIdPh0NMG8Mi+L7uDfqB k2SqwIfGkSk7E7adzfQYzZs+Li4fcyiSZyHZancKd91BX4jSomy0qYpSZqLzvVUrK+6M eZ+R4Yi1GCM1m+8Usj/iguaAlvP/NQF81CUyowyU4Sselg94TjY7yX5OOqfBXRcuJQPI x9SQsEkwxNON36D54JDNrCFex6EZ0k0WIprgTdudIyPuwRl5AvJyUKQ+cSDHpAibqzke +lrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b="lq/JU9s3"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v6 07/16] x86/mtrr: have only one set_mtrr() variant Date: Tue, 2 May 2023 14:09:22 +0200 Message-Id: <20230502120931.20719-8-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785160659681819?= X-GMAIL-MSGID: =?utf-8?q?1764785160659681819?= Today there are two variants of set_mtrr(): one calling stop_machine() and one calling stop_machine_cpuslocked(). The first one (set_mtrr()) has only one caller, and this caller is running only when resuming from suspend when the interrupts are still off and only one CPU is active. Additionally this code is used only on rather old 32-bit CPUs not supporting SMP. For this reasons the first variant can be replaced by a simple call of mtrr_if->set(). Rename the second variant set_mtrr_cpuslocked() to set_mtrr() now that there is only one variant left, in order to have a shorter function name. Signed-off-by: Juergen Gross --- V5: - new patch --- arch/x86/kernel/cpu/mtrr/mtrr.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 3351730447e1..3a38f34bf289 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -177,20 +177,8 @@ static inline int types_compatible(mtrr_type type1, mtrr_type type2) * Note that the mechanism is the same for UP systems, too; all the SMP stuff * becomes nops. */ -static void -set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) -{ - struct set_mtrr_data data = { .smp_reg = reg, - .smp_base = base, - .smp_size = size, - .smp_type = type - }; - - stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask); -} - -static void set_mtrr_cpuslocked(unsigned int reg, unsigned long base, - unsigned long size, mtrr_type type) +static void set_mtrr(unsigned int reg, unsigned long base, unsigned long size, + mtrr_type type) { struct set_mtrr_data data = { .smp_reg = reg, .smp_base = base, @@ -320,7 +308,7 @@ int mtrr_add_page(unsigned long base, unsigned long size, /* Search for an empty MTRR */ i = mtrr_if->get_free_region(base, size, replace); if (i >= 0) { - set_mtrr_cpuslocked(i, base, size, type); + set_mtrr(i, base, size, type); if (likely(replace < 0)) { mtrr_usage_table[i] = 1; } else { @@ -328,7 +316,7 @@ int mtrr_add_page(unsigned long base, unsigned long size, if (increment) mtrr_usage_table[i]++; if (unlikely(replace != i)) { - set_mtrr_cpuslocked(replace, 0, 0, 0); + set_mtrr(replace, 0, 0, 0); mtrr_usage_table[replace] = 0; } } @@ -456,7 +444,7 @@ int mtrr_del_page(int reg, unsigned long base, unsigned long size) goto out; } if (--mtrr_usage_table[reg] < 1) - set_mtrr_cpuslocked(reg, 0, 0, 0); + set_mtrr(reg, 0, 0, 0); error = reg; out: mutex_unlock(&mtrr_mutex); @@ -586,9 +574,9 @@ static void mtrr_restore(void) for (i = 0; i < num_var_ranges; i++) { if (mtrr_value[i].lsize) { - set_mtrr(i, mtrr_value[i].lbase, - mtrr_value[i].lsize, - mtrr_value[i].ltype); + mtrr_if->set(i, mtrr_value[i].lbase, + mtrr_value[i].lsize, + mtrr_value[i].ltype); } } } From patchwork Tue May 2 12:09:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89336 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp568449vqo; Tue, 2 May 2023 05:25:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5DyRXKDwyuMAeHFr0Xxx9LjvACpg6xy0A4EHKA4VsSvi3gDxmrF0cdvq6qCOvhMjkRoXjL X-Received: by 2002:a05:6a20:160e:b0:ee:f5a4:c072 with SMTP id l14-20020a056a20160e00b000eef5a4c072mr22357910pzj.46.1683030334791; Tue, 02 May 2023 05:25:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030334; cv=none; d=google.com; s=arc-20160816; b=c6UepFrME2yD4Q5uo83+6amRcypuLb6sfKNtClMW5aktgkW9s5hLRrswSgp2H0CP6q KbhB2KEPVQJbBUmcn7aPf6YlGyJgSlYqeWZQhrPOniVl6uA0gpQqQURSw6VL0iR3lYDA uRYyJu+l2dkFeCDpq0lAzJGUtwYI5g4F08U+yGttvDxj2jhzxhujF7nblxn/nZSOCnHO pJLO/7L0G9nW2clknUPYp9l2hBkI0l3k3y5FZVWtYb6SB9uC0am/xWkbSeL0kJgms5AY wc8XkG67fR8sjDUGTRDmRVGwg9Jus3u3bvClA4ihhiI0G3kPs/7sAD0Yy7O8eRO+TEPu YKYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=68HytYcZlZwUKMdmIm0HdW7MUHwu5UcVeNGcmReZa2g=; b=jYa1vKE8FMX6otZuf6IGpEcmvee9BZE8YBR+6Xhu8SJz+XPJ/qRcmVKQYugUxYEdLX WXgkKw5oZuQlJF5ddjBlEfYIz+d/sCFd0gh1ODJuX7ciANy5yZwR3ipcIAqpbrzlquFq fgFoDfw2XTcNv1tFpmdxmrN15MziyyyBSWqOp33RsU5UfzQwwdLKl9N96jAtH50do6iL qWLyvFU9ErVmLeACF/YgmTLsHl3U8RWhBgft6BeQBXx5ZQ57KSW2d+WW4puMAPhPyGSU chAu0cCQywjLaacjQTeevFpXMuKmqFvWJ7W8ah6tqsfHpUB3DFHkj+kSFbpmDa2iqY7J ki+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=umF1t+y1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v6 08/16] x86/mtrr: move 32-bit code from mtrr.c to legacy.c Date: Tue, 2 May 2023 14:09:23 +0200 Message-Id: <20230502120931.20719-9-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785216415461947?= X-GMAIL-MSGID: =?utf-8?q?1764785216415461947?= There is some code in mtrr.c which is relevant for old 32-bit CPUs only. Move it to a new source legacy.c. While modifying mtrr_init_finalize() fix spelling of its name. Suggested-by: Borislav Petkov Signed-off-by: Juergen Gross --- V6: - new patch --- arch/x86/kernel/cpu/mtrr/Makefile | 2 +- arch/x86/kernel/cpu/mtrr/legacy.c | 84 +++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mtrr/mtrr.c | 80 +++-------------------------- arch/x86/kernel/cpu/mtrr/mtrr.h | 7 +++ 4 files changed, 98 insertions(+), 75 deletions(-) create mode 100644 arch/x86/kernel/cpu/mtrr/legacy.c diff --git a/arch/x86/kernel/cpu/mtrr/Makefile b/arch/x86/kernel/cpu/mtrr/Makefile index cc4f9f1cb94c..aee4bc5ad496 100644 --- a/arch/x86/kernel/cpu/mtrr/Makefile +++ b/arch/x86/kernel/cpu/mtrr/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y := mtrr.o if.o generic.o cleanup.o -obj-$(CONFIG_X86_32) += amd.o cyrix.o centaur.o +obj-$(CONFIG_X86_32) += amd.o cyrix.o centaur.o legacy.o diff --git a/arch/x86/kernel/cpu/mtrr/legacy.c b/arch/x86/kernel/cpu/mtrr/legacy.c new file mode 100644 index 000000000000..7d379fb26cce --- /dev/null +++ b/arch/x86/kernel/cpu/mtrr/legacy.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include "mtrr.h" + +void mtrr_set_if(void) +{ + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_AMD: + /* Pre-Athlon (K6) AMD CPU MTRRs */ + if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) + mtrr_if = &amd_mtrr_ops; + break; + case X86_VENDOR_CENTAUR: + if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) + mtrr_if = ¢aur_mtrr_ops; + break; + case X86_VENDOR_CYRIX: + if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) + mtrr_if = &cyrix_mtrr_ops; + break; + default: + break; + } +} + +/* + * The suspend/resume methods are only for CPUs without MTRR. CPUs using generic + * MTRR driver don't require this. + */ +struct mtrr_value { + mtrr_type ltype; + unsigned long lbase; + unsigned long lsize; +}; + +static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; + +static int mtrr_save(void) +{ + int i; + + for (i = 0; i < num_var_ranges; i++) { + mtrr_if->get(i, &mtrr_value[i].lbase, + &mtrr_value[i].lsize, + &mtrr_value[i].ltype); + } + return 0; +} + +static void mtrr_restore(void) +{ + int i; + + for (i = 0; i < num_var_ranges; i++) { + if (mtrr_value[i].lsize) { + mtrr_if->set(i, mtrr_value[i].lbase, + mtrr_value[i].lsize, + mtrr_value[i].ltype); + } + } +} + +static struct syscore_ops mtrr_syscore_ops = { + .suspend = mtrr_save, + .resume = mtrr_restore, +}; + +void mtrr_register_syscore(void) +{ + /* + * The CPU has no MTRR and seems to not support SMP. They have + * specific drivers, we use a tricky method to support + * suspend/resume for them. + * + * TBD: is there any system with such CPU which supports + * suspend/resume? If no, we should remove the code. + */ + register_syscore_ops(&mtrr_syscore_ops); +} diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 3a38f34bf289..0eeb03d92d8c 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -545,49 +545,6 @@ int arch_phys_wc_index(int handle) } EXPORT_SYMBOL_GPL(arch_phys_wc_index); -/* The suspend/resume methods are only for CPU without MTRR. CPU using generic - * MTRR driver doesn't require this - */ -struct mtrr_value { - mtrr_type ltype; - unsigned long lbase; - unsigned long lsize; -}; - -static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; - -static int mtrr_save(void) -{ - int i; - - for (i = 0; i < num_var_ranges; i++) { - mtrr_if->get(i, &mtrr_value[i].lbase, - &mtrr_value[i].lsize, - &mtrr_value[i].ltype); - } - return 0; -} - -static void mtrr_restore(void) -{ - int i; - - for (i = 0; i < num_var_ranges; i++) { - if (mtrr_value[i].lsize) { - mtrr_if->set(i, mtrr_value[i].lbase, - mtrr_value[i].lsize, - mtrr_value[i].ltype); - } - } -} - - - -static struct syscore_ops mtrr_syscore_ops = { - .suspend = mtrr_save, - .resume = mtrr_restore, -}; - int __initdata changed_by_mtrr_cleanup; /** @@ -615,27 +572,10 @@ void __init mtrr_bp_init(void) return; } - if (generic_mtrrs) { + if (generic_mtrrs) mtrr_if = &generic_mtrr_ops; - } else { - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_AMD: - /* Pre-Athlon (K6) AMD CPU MTRRs */ - if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) - mtrr_if = &amd_mtrr_ops; - break; - case X86_VENDOR_CENTAUR: - if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) - mtrr_if = ¢aur_mtrr_ops; - break; - case X86_VENDOR_CYRIX: - if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) - mtrr_if = &cyrix_mtrr_ops; - break; - default: - break; - } - } + else + mtrr_set_if(); if (mtrr_enabled()) { /* Get the number of variable MTRR ranges. */ @@ -677,7 +617,7 @@ void mtrr_save_state(void) smp_call_function_single(first_cpu, mtrr_save_fixed_ranges, NULL, 1); } -static int __init mtrr_init_finialize(void) +static int __init mtrr_init_finalize(void) { if (!mtrr_enabled()) return 0; @@ -688,16 +628,8 @@ static int __init mtrr_init_finialize(void) return 0; } - /* - * The CPU has no MTRR and seems to not support SMP. They have - * specific drivers, we use a tricky method to support - * suspend/resume for them. - * - * TBD: is there any system with such CPU which supports - * suspend/resume? If no, we should remove the code. - */ - register_syscore_ops(&mtrr_syscore_ops); + mtrr_register_syscore(); return 0; } -subsys_initcall(mtrr_init_finialize); +subsys_initcall(mtrr_init_finalize); diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h index 0dd11e41baa6..f626febeb545 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -61,6 +61,13 @@ void mtrr_set_mask(void); void mtrr_state_warn(void); const char *mtrr_attrib_to_str(int x); void mtrr_wrmsr(unsigned, unsigned, unsigned); +#ifdef CONFIG_X86_32 +void mtrr_set_if(void); +void mtrr_register_syscore(void); +#else +static inline void mtrr_set_if(void) { } +static inline void mtrr_register_syscore(void) { } +#endif /* CPU specific mtrr_ops vectors. */ extern const struct mtrr_ops amd_mtrr_ops; From patchwork Tue May 2 12:09:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89340 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp568937vqo; Tue, 2 May 2023 05:26:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5UBRg6C8oh2cJap9sAgLeGmRNzNqwY5VqdWNxhvKIE26tNLgN9z6vqwQEdJ6ZGBWi0bzfG X-Received: by 2002:a17:902:b585:b0:1a9:58d7:356f with SMTP id a5-20020a170902b58500b001a958d7356fmr14820954pls.9.1683030385032; Tue, 02 May 2023 05:26:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030385; cv=none; d=google.com; s=arc-20160816; b=B5R5csNYN1rWPYyfW1/8dd4l8EMA/UBHMD77bo+CUbDnkhey2fLIyTCYOF0uI+RN6G OczjFa7/wnQv9DPOAtVGI8EbR7PnZrekGeeu+K5y1B0fRp+4+50AR9afFTv8D+Y88Sk2 +SjdIm1HV5DxLHEhuVfKN9U9lva/5+TOyqDb3kOdMUL1DtQRE80BugtIgTi2HfVcF0IS x5JXpdez9W0ew+p64jvfiYvFpXwwyJlqPvWicbhURVn4WKojTKXuYilb166dXVluL/iw 0PUmm4QqcAaZa6XW/Fr6aTV9abEOiHXRGUZdiiitoYKUg63LCZAJoBK9cyEb0bTBSW+J 08og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bZxyQRt/yrkvsCuSBp3GRmGhot3fCxU/5bmk8IYlVXE=; b=xVNff1N7qHxAnK4zePKF4AskHiVfDoxYsq+ArF+DoKwiZ2uBIpJMhjvpo71Yu9Amjn dkEFFI0W8YmObdJZFOwHsbsk7kzTrOB1Oipi0/BNaP/mwabRSWxqAzRmvxPnUg6frL9H ru7R2fbbZRE/na1b/I2MdW+jTiEaDn8pjM2VUedLCDzrXdThUk46VOk4ck2yNPZC1hfZ Y+WYxpai0YyASLgAknROYIwiYRVf0of0yqwArqAUxrzjYNmMQ65403sGE86GWbLkyHjH 6XLonbHw9vigzE3DjH5rcWY6O5gWBE72at9KHcRmO4BBGKC5dGgJxROrdNzZb2sW++Zu MsvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=h4ig5p68; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v6 09/16] x86/mtrr: allocate mtrr_value array dynamically Date: Tue, 2 May 2023 14:09:24 +0200 Message-Id: <20230502120931.20719-10-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785269034212108?= X-GMAIL-MSGID: =?utf-8?q?1764785269034212108?= The mtrr_value[] array is a static variable, which is used only in a few configurations. Consuming 6kB is ridiculous for this case, especially as the array doesn't need to be that large and it can easily be allocated dynamically. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V5: - check for allocation failure (Kai Huang, Boris Petkov) - add #ifdef V6: - rebase --- arch/x86/kernel/cpu/mtrr/legacy.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mtrr/legacy.c b/arch/x86/kernel/cpu/mtrr/legacy.c index 7d379fb26cce..d25882fcf181 100644 --- a/arch/x86/kernel/cpu/mtrr/legacy.c +++ b/arch/x86/kernel/cpu/mtrr/legacy.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only #include +#include #include #include #include @@ -38,12 +39,15 @@ struct mtrr_value { unsigned long lsize; }; -static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; +static struct mtrr_value *mtrr_value; static int mtrr_save(void) { int i; + if (!mtrr_value) + return -ENOMEM; + for (i = 0; i < num_var_ranges; i++) { mtrr_if->get(i, &mtrr_value[i].lbase, &mtrr_value[i].lsize, @@ -72,6 +76,8 @@ static struct syscore_ops mtrr_syscore_ops = { void mtrr_register_syscore(void) { + mtrr_value = kcalloc(num_var_ranges, sizeof(*mtrr_value), GFP_KERNEL); + /* * The CPU has no MTRR and seems to not support SMP. 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Peter Anvin" Subject: [PATCH v6 10/16] x86/mtrr: add get_effective_type() service function Date: Tue, 2 May 2023 14:09:25 +0200 Message-Id: <20230502120931.20719-11-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764784978234541993?= X-GMAIL-MSGID: =?utf-8?q?1764784978234541993?= Add a service function for obtaining the effective cache mode of overlapping MTRR registers. Make use of that function in check_type_overlap(). Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch --- arch/x86/kernel/cpu/mtrr/generic.c | 39 +++++++++++++++--------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index cd887327ba3a..44e035a8e9fb 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -86,31 +86,30 @@ static u64 get_mtrr_size(u64 mask) return size; } +static u8 get_effective_type(u8 type1, u8 type2) +{ + if (type1 == MTRR_TYPE_UNCACHABLE || type2 == MTRR_TYPE_UNCACHABLE) + return MTRR_TYPE_UNCACHABLE; + + if ((type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH) || + (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK)) + return MTRR_TYPE_WRTHROUGH; + + if (type1 != type2) + return MTRR_TYPE_UNCACHABLE; + + return type1; +} + /* * Check and return the effective type for MTRR-MTRR type overlap. - * Returns 1 if the effective type is UNCACHEABLE, else returns 0 + * Returns true if the effective type is UNCACHEABLE, else returns false */ -static int check_type_overlap(u8 *prev, u8 *curr) +static bool check_type_overlap(u8 *prev, u8 *curr) { - if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) { - *prev = MTRR_TYPE_UNCACHABLE; - *curr = MTRR_TYPE_UNCACHABLE; - return 1; - } - - if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) || - (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) { - *prev = MTRR_TYPE_WRTHROUGH; - *curr = MTRR_TYPE_WRTHROUGH; - } + *prev = *curr = get_effective_type(*curr, *prev); - if (*prev != *curr) { - *prev = MTRR_TYPE_UNCACHABLE; - *curr = MTRR_TYPE_UNCACHABLE; - return 1; - } - - return 0; + return *prev == MTRR_TYPE_UNCACHABLE; } /** From patchwork Tue May 2 12:09:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89332 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp567450vqo; Tue, 2 May 2023 05:24:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7+QgO5jovtra8WrGk5K5ZHd+lRQ0/nizSrzOxnIfCoQ4fJW7hHDEnkqzBQjMYf+4Q1F2Ls X-Received: by 2002:a05:6a20:43ac:b0:f0:3e78:715b with SMTP id i44-20020a056a2043ac00b000f03e78715bmr18976369pzl.40.1683030245446; Tue, 02 May 2023 05:24:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030245; cv=none; d=google.com; s=arc-20160816; b=M/OWoerhihCyvs2rSX4ro4PBRnZCqoN9m7GmYxlxHSBbAJXCikNl1l+KU+da5M9taI 5DJu+y0O/bjiDt59vOdMRMPlhyZ4uHmDeuN5wm1dS9KyTw32RhtWx++4THMNiCGqxJYh f2O9hUyRFzL9/V6T+GvyU42RMrXeWrzSL8+ccCdCwk7VkpAkXM4+kiQP1otMH4R105ud 7abnteRSgCtKD2OCcERNQMzBU6RP1aCN3mKmyNLijbIgwh5c8NBmpyOXxI7IChGQZi3p V34uEpD/mlba69c6sAgh75eEtc8jmylzv9e9CRizcgXYR+Mw3OPkyy7M06VejSjJYqZG l+gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NQsbhe24VGyqOwRLrkzmuRDIYmio0BvErgoPF3HlFlQ=; b=M+fCAABa1qD73triBN1D62FQ5cr4oQukL2ab/K7KhHlS2EqcGCJ7MmckHFehas6Y/q MVtROsDMLkMb/vj17tDR7XrCoXXHbbnycgyjZ9qsaStLPfGra87pmf0WMNTbyjK/28E6 U33TdI2uRRYqEslme2+c/4cZxpdMSosrf/qbrHdbw/aN1qbMXOqH7pwDKYqj8pAoEQMh CMOVOfS61Epx2BdYmUSF7LvwTUejEqcMywvJASd1DfeeQV+eLIkM1dJHXcM1Zv7fwcdp bdqShGgTDNwGcSejIVVdanEvloNg1hP30+v+wc8E8/dVs43uoQjUMcU5ZZYM0Wwn07af kX9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=WNEeYr+q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v6 11/16] x86/mtrr: construct a memory map with cache modes Date: Tue, 2 May 2023 14:09:26 +0200 Message-Id: <20230502120931.20719-12-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785122605595119?= X-GMAIL-MSGID: =?utf-8?q?1764785122605595119?= After MTRR initialization construct a memory map with cache modes from MTRR values. This will speed up lookups via mtrr_lookup_type() especially in case of overlapping MTRRs. This will be needed when switching the semantics of the "uniform" parameter of mtrr_lookup_type() from "only covered by one MTRR" to "memory range has a uniform cache mode", which is the data the callers really want to know. Today this information is not easily available, in case MTRRs are not well sorted regarding base address. The map will be built in __initdata. When memory management is up, the map will be moved to dynamically allocated memory, in order to avoid the need of an overly large array. The size of this array is calculated using the number of variable MTRR registers and the needed size for fixed entries. Only add the map creation and expansion for now. The lookup will be added later. When writing new MTRR entries in the running system rebuild the map inside the call from mtrr_rendezvous_handler() in order to avoid nasty race conditions with concurrent lookups. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V5: - fix setting of mtrr_tom2 - change cache_map .type and .fixed to bitfields (Boris Petkov) - use memmove() (Boris Petkov) - a lot of comments (Boris Petkov) - rewrite setting of merge bools (Boris Petkov) - mark mtrr_build_map() as __init - add pr_info() (Boris Petkov) V6: - handle allocation failure for map - remove check in mtrr_build_map() (Boris Petkov) - add more comments (Boris Petkov) - avoid calling memmove() with zero size (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/generic.c | 300 +++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mtrr/mtrr.c | 10 +- arch/x86/kernel/cpu/mtrr/mtrr.h | 3 + 3 files changed, 312 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 44e035a8e9fb..a6dd240a09cb 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -33,6 +33,38 @@ static struct fixed_range_block fixed_range_blocks[] = { {} }; +struct cache_map { + u64 start; + u64 end; + u64 flags; + u64 type:8; + u64 fixed:1; +}; + +/* + * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where + * no 2 adjacent ranges have the same cache mode (those would be merged). + * The number is based on the worst case: + * - no two adjacent fixed MTRRs share the same cache mode + * - one variable MTRR is spanning a huge area with mode WB + * - 255 variable MTRRs with mode UC all overlap with the WB MTRR, creating 2 + * additional ranges each (result like "ababababa...aba" with a = WB, b = UC), + * accounting for MTRR_MAX_VAR_RANGES * 2 - 1 range entries + * - a TOP_MEM2 area (even with overlapping an UC MTRR can't add 2 range entries + * to the possible maximum, as it always starts at 4GB, thus it can't be in + * the middle of that MTRR, unless that MTRR starts at 0, which would remove + * the initial "a" from the "abababa" pattern above) + * The map won't contain ranges with no matching MTRR (those fall back to the + * default cache mode). + */ +#define CACHE_MAP_MAX (MTRR_NUM_FIXED_RANGES + MTRR_MAX_VAR_RANGES * 2) + +static struct cache_map init_cache_map[CACHE_MAP_MAX] __initdata; +static struct cache_map *cache_map __refdata = init_cache_map; +static unsigned int cache_map_size = CACHE_MAP_MAX; +static unsigned int cache_map_n; +static unsigned int cache_map_fixed; + static unsigned long smp_changes_mask; static int mtrr_state_set; u64 mtrr_tom2; @@ -86,6 +118,20 @@ static u64 get_mtrr_size(u64 mask) return size; } +static u8 get_var_mtrr_state(unsigned int reg, u64 *start, u64 *size) +{ + struct mtrr_var_range *mtrr = mtrr_state.var_ranges + reg; + + if (!(mtrr->mask_lo & MTRR_PHYSMASK_V)) + return MTRR_TYPE_INVALID; + + *start = (((u64)mtrr->base_hi) << 32) + (mtrr->base_lo & PAGE_MASK); + *size = get_mtrr_size((((u64)mtrr->mask_hi) << 32) + + (mtrr->mask_lo & PAGE_MASK)); + + return mtrr->base_lo & MTRR_PHYSBASE_TYPE; +} + static u8 get_effective_type(u8 type1, u8 type2) { if (type1 == MTRR_TYPE_UNCACHABLE || type2 == MTRR_TYPE_UNCACHABLE) @@ -250,6 +296,256 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, return mtrr_state.def_type; } +static void rm_map_entry_at(int idx) +{ + cache_map_n--; + if (cache_map_n > idx) { + memmove(cache_map + idx, cache_map + idx + 1, + sizeof(*cache_map) * (cache_map_n - idx)); + } +} + +/* + * Add an entry into cache_map at a specific index. Merges adjacent entries if + * appropriate. Return the number of merges for correcting the scan index + * (this is needed as merging will reduce the number of entries, which will + * result in skipping entries in future iterations if the scan index isn't + * corrected). + * Note that the corrected index can never go below -1 (resulting in being 0 in + * the next scan iteration), as "2" is returned only if the current index is + * larger than zero. + */ +static int add_map_entry_at(u64 start, u64 end, u8 type, int idx) +{ + bool merge_prev = false, merge_next = false; + + if (start >= end) + return 0; + + if (idx > 0) { + struct cache_map *prev = cache_map + idx - 1; + + if (!prev->fixed && start == prev->end && type == prev->type) + merge_prev = true; + } + + if (idx < cache_map_n) { + struct cache_map *next = cache_map + idx; + + if (!next->fixed && end == next->start && type == next->type) + merge_next = true; + } + + if (merge_prev && merge_next) { + cache_map[idx - 1].end = cache_map[idx].end; + rm_map_entry_at(idx); + return 2; + } + if (merge_prev) { + cache_map[idx - 1].end = end; + return 1; + } + if (merge_next) { + cache_map[idx].start = start; + return 1; + } + + /* Sanity check: the array should NEVER be too small! */ + if (cache_map_n == cache_map_size) { + WARN(1, "MTRR cache mode memory map exhausted!\n"); + cache_map_n = cache_map_fixed; + return 0; + } + + if (cache_map_n > idx) { + memmove(cache_map + idx + 1, cache_map + idx, + sizeof(*cache_map) * (cache_map_n - idx)); + } + + cache_map[idx].start = start; + cache_map[idx].end = end; + cache_map[idx].type = type; + cache_map[idx].fixed = 0; + cache_map_n++; + + return 0; +} + +/* Clear a part of an entry. Return 1 if start of entry is still valid. */ +static int clr_map_range_at(u64 start, u64 end, int idx) +{ + int ret = start != cache_map[idx].start; + u64 tmp; + + if (start == cache_map[idx].start && end == cache_map[idx].end) { + rm_map_entry_at(idx); + } else if (start == cache_map[idx].start) { + cache_map[idx].start = end; + } else if (end == cache_map[idx].end) { + cache_map[idx].end = start; + } else { + tmp = cache_map[idx].end; + cache_map[idx].end = start; + add_map_entry_at(end, tmp, cache_map[idx].type, idx + 1); + } + + return ret; +} + +/* + * Add MTRR to the map. The current map is scanned and each part of the MTRR + * either overlapping with an existing entry or with a hole in the map is + * handled separately. + */ +static void add_map_entry(u64 start, u64 end, u8 type) +{ + u8 new_type, old_type; + u64 tmp; + int i; + + for (i = 0; i < cache_map_n && start < end; i++) { + if (start >= cache_map[i].end) + continue; + + if (start < cache_map[i].start) { + /* Region start has no overlap. */ + tmp = min(end, cache_map[i].start); + i -= add_map_entry_at(start, tmp, type, i); + start = tmp; + continue; + } + + new_type = get_effective_type(type, cache_map[i].type); + old_type = cache_map[i].type; + + if (cache_map[i].fixed || new_type == old_type) { + /* Cut off start of new entry. */ + start = cache_map[i].end; + continue; + } + + /* Handle only overlapping part of region. */ + tmp = min(end, cache_map[i].end); + i += clr_map_range_at(start, tmp, i); + i -= add_map_entry_at(start, tmp, new_type, i); + start = tmp; + } + + /* Add rest of region after last map entry (rest might be empty). */ + add_map_entry_at(start, end, type, i); +} + +/* Add variable MTRRs to cache map. */ +static void map_add_var(void) +{ + u64 start, size; + unsigned int i; + u8 type; + + /* + * Add AMD TOP_MEM2 area. Can't be added in mtrr_build_map(), as it + * needs to be added again when rebuilding the map due to potentially + * having moved as a result of variable MTRRs for memory below 4GB. + */ + if (mtrr_tom2) { + add_map_entry(BIT_ULL(32), mtrr_tom2, MTRR_TYPE_WRBACK); + cache_map[cache_map_n - 1].fixed = 1; + } + + for (i = 0; i < num_var_ranges; i++) { + type = get_var_mtrr_state(i, &start, &size); + if (type != MTRR_TYPE_INVALID) + add_map_entry(start, start + size, type); + } +} + +/* + * Rebuild map by replacing variable entries. Needs to be called when MTRR + * registers are being changed after boot, as such changes could include + * removals of registers, which are complicated to handle without rebuild of + * the map. + */ +static void rebuild_map(void) +{ + cache_map_n = cache_map_fixed; + + map_add_var(); +} + +static unsigned int __init get_cache_map_size(void) +{ + return cache_map_fixed + 2 * num_var_ranges + (mtrr_tom2 != 0); +} + +/* Build the cache_map containing the cache modes per memory range. */ +void __init mtrr_build_map(void) +{ + u64 start, end, size; + unsigned int i; + u8 type; + + /* Add fixed MTRRs, optimize for adjacent entries with same type. */ + if (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED) { + /* + * Start with 64k size fixed entries, preset 1st one (hence the + * loop below is starting with index 1). + */ + start = 0; + end = size = 0x10000; + type = mtrr_state.fixed_ranges[0]; + + for (i = 1; i < MTRR_NUM_FIXED_RANGES; i++) { + /* 8 64k entries, then 16 16k ones, rest 4k. */ + if (i == 8 || i == 24) + size >>= 2; + + if (mtrr_state.fixed_ranges[i] != type) { + add_map_entry(start, end, type); + start = end; + type = mtrr_state.fixed_ranges[i]; + } + end += size; + } + add_map_entry(start, end, type); + } + + /* Mark fixed, they take precedence. */ + for (i = 0; i < cache_map_n; i++) + cache_map[i].fixed = 1; + cache_map_fixed = cache_map_n; + + map_add_var(); + + pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built from %u variable MTRRs\n", + cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed, + get_cache_map_size(), num_var_ranges + (mtrr_tom2 != 0)); +} + +/* Copy the cache_map from __initdata memory to dynamically allocated one. */ +void __init mtrr_copy_map(void) +{ + unsigned int new_size = get_cache_map_size(); + + if (!mtrr_state.enabled || !new_size) { + cache_map = NULL; + return; + } + + mutex_lock(&mtrr_mutex); + + cache_map = kcalloc(new_size, sizeof(*cache_map), GFP_KERNEL); + if (cache_map) { + memmove(cache_map, init_cache_map, + cache_map_n * sizeof(*cache_map)); + cache_map_size = new_size; + } else { + mtrr_state.enabled = 0; + pr_err("MTRRs disabled due to allocation failure for lookup map.\n"); + } + + mutex_unlock(&mtrr_mutex); +} + /** * mtrr_overwrite_state - set static MTRR state * @@ -841,6 +1137,10 @@ static void generic_set_mtrr(unsigned int reg, unsigned long base, cache_enable(); local_irq_restore(flags); + + /* On the first CPU rebuild the cache mode memory map. */ + if (smp_processor_id() == cpumask_first(cpu_online_mask)) + rebuild_map(); } int generic_validate_add_page(unsigned long base, unsigned long size, diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 0eeb03d92d8c..441e3f9d64f7 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -65,7 +65,7 @@ static bool mtrr_enabled(void) } unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; -static DEFINE_MUTEX(mtrr_mutex); +DEFINE_MUTEX(mtrr_mutex); const struct mtrr_ops *mtrr_if; @@ -567,6 +567,7 @@ void __init mtrr_bp_init(void) * Note that X86_FEATURE_MTRR has been reset in this case. */ init_table(); + mtrr_build_map(); pr_info("MTRRs set to read-only\n"); return; @@ -591,6 +592,7 @@ void __init mtrr_bp_init(void) if (get_mtrr_state()) { memory_caching_control |= CACHE_MTRR; changed_by_mtrr_cleanup = mtrr_cleanup(); + mtrr_build_map(); } else { mtrr_if = NULL; why = "by BIOS"; @@ -619,6 +621,12 @@ void mtrr_save_state(void) static int __init mtrr_init_finalize(void) { + /* + * Map might exist if mtrr_overwrite_state() has been called or if + * mtrr_enabled() returns true. + */ + mtrr_copy_map(); + if (!mtrr_enabled()) return 0; diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h index f626febeb545..5c690175580a 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -52,6 +52,7 @@ void fill_mtrr_var_range(unsigned int index, bool get_mtrr_state(void); extern const struct mtrr_ops *mtrr_if; +extern struct mutex mtrr_mutex; extern unsigned int num_var_ranges; extern u64 mtrr_tom2; @@ -68,6 +69,8 @@ void mtrr_register_syscore(void); static inline void mtrr_set_if(void) { } static inline void mtrr_register_syscore(void) { } #endif +void mtrr_build_map(void); +void mtrr_copy_map(void); /* CPU specific mtrr_ops vectors. */ extern const struct mtrr_ops amd_mtrr_ops; From patchwork Tue May 2 12:09:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89328 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp565989vqo; Tue, 2 May 2023 05:21:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ44XF7OimvEONVy0sgO2HCy02Vlp71uUthFOlRbUUy5J+A+WvMPxdK3BUcFH3abkmlK2pIl X-Received: by 2002:a17:902:d510:b0:1a9:631b:7d68 with SMTP id b16-20020a170902d51000b001a9631b7d68mr21338135plg.8.1683030109094; Tue, 02 May 2023 05:21:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030109; cv=none; d=google.com; s=arc-20160816; b=xTZ/U9ytOWOhZV4m+bjInB0rzhBLVPIwDPtGBVY3fAbUpGUDAcXolofof1KwL2zNPx bW9X1GmBzm26++GcaDcr9Jbb3lkd4S+8DpQwXyxBN4AzLIXVz0EguFDt5+WCEP5AIuB2 EFtV/IIK6gPnytT2povX/bIevNIZgFgVfFgEblpDCkahLJHEUsEflOQxuL4OEkllNH6W WpJmSeSd3pgqxtZOcNg7nOLeo1xLH8mzCBejLDnuecczog7+XfEGTsfSF2sdZac2vKzB fbqE+4p+k/fHsjPaNPDY20U9bWtMPbjV767kHEY2jAKBAVwFUhEkxhVwbXx6/wdSLLfE OgFA== ARC-Message-Signature: i=1; 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Peter Anvin" Subject: [PATCH v6 12/16] x86/mtrr: add mtrr=debug command line option Date: Tue, 2 May 2023 14:09:27 +0200 Message-Id: <20230502120931.20719-13-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764784979487010272?= X-GMAIL-MSGID: =?utf-8?q?1764784979487010272?= Add a new command line option "mtrr=debug" for getting debug output after building the new cache mode map. The output will include MTRR register values and the resulting map. For printing the MTRR register values print_mtrr_state() can be used. Just change it to use pr_info() instead of pr_debug() and call it only if mtrr=debug was specified. Signed-off-by: Juergen Gross --- V6: - new patch (Boris Petkov) --- .../admin-guide/kernel-parameters.txt | 4 ++ arch/x86/kernel/cpu/mtrr/generic.c | 64 +++++++++++++------ 2 files changed, 49 insertions(+), 19 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 9e5bab29685f..44a87ada7145 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3423,6 +3423,10 @@ [HW] Make the MicroTouch USB driver use raw coordinates ('y', default) or cooked coordinates ('n') + mtrr=debug [X86] + Enable printing debug information related to MTRR + registers at boot time. + mtrr_chunk_size=nn[KMG] [X86] used for mtrr cleanup. It is largest continuous chunk that could hold holes aka. UC entries. diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index a6dd240a09cb..e002856a5f4e 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -41,6 +41,23 @@ struct cache_map { u64 fixed:1; }; +static bool mtrr_debug; + +static int __init mtrr_param_setup(char *str) +{ + int rc = 0; + + if (!str) + return -EINVAL; + if (!strcmp(str, "debug")) + mtrr_debug = true; + else + rc = -EINVAL; + + return rc; +} +early_param("mtrr", mtrr_param_setup); + /* * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where * no 2 adjacent ranges have the same cache mode (those would be merged). @@ -519,6 +536,14 @@ void __init mtrr_build_map(void) pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built from %u variable MTRRs\n", cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed, get_cache_map_size(), num_var_ranges + (mtrr_tom2 != 0)); + + if (mtrr_debug) { + for (i = 0; i < cache_map_n; i++) { + pr_info("%3u: %016llx-%016llx %s\n", i, + cache_map[i].start, cache_map[i].end - 1, + mtrr_attrib_to_str(cache_map[i].type)); + } + } } /* Copy the cache_map from __initdata memory to dynamically allocated one. */ @@ -725,8 +750,8 @@ static void __init print_fixed_last(void) if (!last_fixed_end) return; - pr_debug(" %05X-%05X %s\n", last_fixed_start, - last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); + pr_info(" %05X-%05X %s\n", last_fixed_start, + last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); last_fixed_end = 0; } @@ -764,10 +789,10 @@ static void __init print_mtrr_state(void) unsigned int i; int high_width; - pr_debug("MTRR default type: %s\n", - mtrr_attrib_to_str(mtrr_state.def_type)); + pr_info("MTRR default type: %s\n", + mtrr_attrib_to_str(mtrr_state.def_type)); if (mtrr_state.have_fixed) { - pr_debug("MTRR fixed ranges %sabled:\n", + pr_info("MTRR fixed ranges %sabled:\n", ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) && (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ? "en" : "dis"); @@ -782,27 +807,27 @@ static void __init print_mtrr_state(void) /* tail */ print_fixed_last(); } - pr_debug("MTRR variable ranges %sabled:\n", - mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); + pr_info("MTRR variable ranges %sabled:\n", + mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); high_width = (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; for (i = 0; i < num_var_ranges; ++i) { if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V) - pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", - i, - high_width, - mtrr_state.var_ranges[i].base_hi, - mtrr_state.var_ranges[i].base_lo >> 12, - high_width, - mtrr_state.var_ranges[i].mask_hi, - mtrr_state.var_ranges[i].mask_lo >> 12, - mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & + pr_info(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", + i, + high_width, + mtrr_state.var_ranges[i].base_hi, + mtrr_state.var_ranges[i].base_lo >> 12, + high_width, + mtrr_state.var_ranges[i].mask_hi, + mtrr_state.var_ranges[i].mask_lo >> 12, + mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & MTRR_PHYSBASE_TYPE)); else - pr_debug(" %u disabled\n", i); + pr_info(" %u disabled\n", i); } if (mtrr_tom2) - pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); + pr_info("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); } /* Grab all of the MTRR state for this CPU into *state */ @@ -838,7 +863,8 @@ bool __init get_mtrr_state(void) mtrr_tom2 &= 0xffffff800000ULL; } - print_mtrr_state(); + if (mtrr_debug) + print_mtrr_state(); mtrr_state_set = 1; From patchwork Tue May 2 12:09:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89337 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp568567vqo; Tue, 2 May 2023 05:25:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4mniotZzXkACTzjPyMAVWJ4OsUIvogv1sWgN+B1kpUJvW+tNo02JrI6cESl/fUChCLjPs3 X-Received: by 2002:a17:902:d492:b0:1aa:e0e4:eca with SMTP id c18-20020a170902d49200b001aae0e40ecamr11303569plg.18.1683030343893; Tue, 02 May 2023 05:25:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030343; cv=none; d=google.com; s=arc-20160816; b=zjohi5Z/FEjPub5OEbj6cLwpyJT+lgwvtF3cEwkrBiQQ3cAtQdtCOwfp4UEGDRcFkL HLTSE9FRuhSUoeADnBF7WHasSn3awsj9elbwDiEucXoKoGJ6mepT9RD3kun6eXSLKqas 6VLFacgJsij1J2uLtiyn82SLUvWUi2GgDQCTYlo/iyrpPXWaJ2KanjzROsTZfDIeuhEa 7fyB550Kd4rVfikz8eiY21NGO/I3Ln/2cQSoLGHXfsLBvyuEuDItGDxuXxooRaGzkGli MeE9HCu4J06NtzQ22UPrlczblE40fxBVExl8a7upn6as93iXTrerJIvSzyw/B2vD2gTy 8UBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kLyu6/uv5d/3LqBfrrlbCUTHIoraeKrUgkjBlegFIpI=; b=YVGmBYn5LqT0dMwIaCGuyDCjRnZos1vpuRDbKhN7KAhx9L//KiqAWYV2c0fvap3otn ouGqWmWOn/seSFQKiw5p7hC5X0J7iTcPa4+7+lvo73JXTjje4WyQHwOhuhMCyIYKoQca 0YyGQm8XYJBy3ztpQPv11/bxRbNUnycNn19pyT9Osc3twFh+uS8388TWALfwVXmARU7T /uWGP4n1QnozRPz8MazwASkXtqLPzqrcTQPnR/xtcNRVlHxtlfNm3j3ww0jmLQ1ILjs3 6kr4W2xxBoklheRjmCQuWAStx0DcdYeZ8wfcuziVv5XzX8UnJBfv4/IflWect9ToscxN Hrnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=nQKnqH8T; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v6 13/16] x86/mtrr: use new cache_map in mtrr_type_lookup() Date: Tue, 2 May 2023 14:09:28 +0200 Message-Id: <20230502120931.20719-14-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785225787075697?= X-GMAIL-MSGID: =?utf-8?q?1764785225787075697?= Instead of crawling through the MTRR register state, use the new cache_map for looking up the cache type(s) of a memory region. This allows now to set the uniform parameter according to the uniformity of the cache mode of the region, instead of setting it only if the complete region is mapped by a single MTRR. This now includes even the region covered by the fixed MTRR registers. Make sure uniform is always set. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V3.1: - fix type_merge() (Michael Kelley) V4: - fix type_merge() again (Michael Kelley) --- arch/x86/kernel/cpu/mtrr/generic.c | 228 ++++------------------------- 1 file changed, 32 insertions(+), 196 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index e002856a5f4e..2197e835e98c 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -164,155 +164,6 @@ static u8 get_effective_type(u8 type1, u8 type2) return type1; } -/* - * Check and return the effective type for MTRR-MTRR type overlap. - * Returns true if the effective type is UNCACHEABLE, else returns false - */ -static bool check_type_overlap(u8 *prev, u8 *curr) -{ - *prev = *curr = get_effective_type(*curr, *prev); - - return *prev == MTRR_TYPE_UNCACHABLE; -} - -/** - * mtrr_type_lookup_fixed - look up memory type in MTRR fixed entries - * - * Return the MTRR fixed memory type of 'start'. - * - * MTRR fixed entries are divided into the following ways: - * 0x00000 - 0x7FFFF : This range is divided into eight 64KB sub-ranges - * 0x80000 - 0xBFFFF : This range is divided into sixteen 16KB sub-ranges - * 0xC0000 - 0xFFFFF : This range is divided into sixty-four 4KB sub-ranges - * - * Return Values: - * MTRR_TYPE_(type) - Matched memory type - * MTRR_TYPE_INVALID - Unmatched - */ -static u8 mtrr_type_lookup_fixed(u64 start, u64 end) -{ - int idx; - - if (start >= 0x100000) - return MTRR_TYPE_INVALID; - - /* 0x0 - 0x7FFFF */ - if (start < 0x80000) { - idx = 0; - idx += (start >> 16); - return mtrr_state.fixed_ranges[idx]; - /* 0x80000 - 0xBFFFF */ - } else if (start < 0xC0000) { - idx = 1 * 8; - idx += ((start - 0x80000) >> 14); - return mtrr_state.fixed_ranges[idx]; - } - - /* 0xC0000 - 0xFFFFF */ - idx = 3 * 8; - idx += ((start - 0xC0000) >> 12); - return mtrr_state.fixed_ranges[idx]; -} - -/** - * mtrr_type_lookup_variable - look up memory type in MTRR variable entries - * - * Return Value: - * MTRR_TYPE_(type) - Matched memory type or default memory type (unmatched) - * - * Output Arguments: - * repeat - Set to 1 when [start:end] spanned across MTRR range and type - * returned corresponds only to [start:*partial_end]. Caller has - * to lookup again for [*partial_end:end]. - * - * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the - * region is fully covered by a single MTRR entry or the default - * type. - */ -static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, - int *repeat, u8 *uniform) -{ - int i; - u64 base, mask; - u8 prev_match, curr_match; - - *repeat = 0; - *uniform = 1; - - prev_match = MTRR_TYPE_INVALID; - for (i = 0; i < num_var_ranges; ++i) { - unsigned short start_state, end_state, inclusive; - - if (!(mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V)) - continue; - - base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + - (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); - mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + - (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); - - start_state = ((start & mask) == (base & mask)); - end_state = ((end & mask) == (base & mask)); - inclusive = ((start < base) && (end > base)); - - if ((start_state != end_state) || inclusive) { - /* - * We have start:end spanning across an MTRR. - * We split the region into either - * - * - start_state:1 - * (start:mtrr_end)(mtrr_end:end) - * - end_state:1 - * (start:mtrr_start)(mtrr_start:end) - * - inclusive:1 - * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end) - * - * depending on kind of overlap. - * - * Return the type of the first region and a pointer - * to the start of next region so that caller will be - * advised to lookup again after having adjusted start - * and end. - * - * Note: This way we handle overlaps with multiple - * entries and the default type properly. - */ - if (start_state) - *partial_end = base + get_mtrr_size(mask); - else - *partial_end = base; - - if (unlikely(*partial_end <= start)) { - WARN_ON(1); - *partial_end = start + PAGE_SIZE; - } - - end = *partial_end - 1; /* end is inclusive */ - *repeat = 1; - *uniform = 0; - } - - if ((start & mask) != (base & mask)) - continue; - - curr_match = mtrr_state.var_ranges[i].base_lo & - MTRR_PHYSBASE_TYPE; - if (prev_match == MTRR_TYPE_INVALID) { - prev_match = curr_match; - continue; - } - - *uniform = 0; - if (check_type_overlap(&prev_match, &curr_match)) - return curr_match; - } - - if (prev_match != MTRR_TYPE_INVALID) - return prev_match; - - return mtrr_state.def_type; -} - static void rm_map_entry_at(int idx) { cache_map_n--; @@ -627,6 +478,20 @@ void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, mtrr_state_set = 1; } +static u8 type_merge(u8 type, u8 new_type, u8 *uniform) +{ + u8 effective_type; + + if (type == MTRR_TYPE_INVALID) + return new_type; + + effective_type = get_effective_type(type, new_type); + if (type != effective_type) + *uniform = 0; + + return effective_type; +} + /** * mtrr_type_lookup - look up memory type in MTRR * @@ -635,66 +500,37 @@ void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, * MTRR_TYPE_INVALID - MTRR is disabled * * Output Argument: - * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the - * region is fully covered by a single MTRR entry or the default - * type. + * uniform - Set to 1 when the returned MTRR type is valid for the whole + * region, set to 0 else. */ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) { - u8 type, prev_type, is_uniform = 1, dummy; - int repeat; - u64 partial_end; - - /* Make end inclusive instead of exclusive */ - end--; + u8 type = MTRR_TYPE_INVALID; + unsigned int i; - if (!mtrr_state_set) + if (!mtrr_state_set) { + *uniform = 0; /* Uniformity is unknown. */ return MTRR_TYPE_INVALID; + } + + *uniform = 1; if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) return MTRR_TYPE_INVALID; - /* - * Look up the fixed ranges first, which take priority over - * the variable ranges. - */ - if ((start < 0x100000) && - (mtrr_state.have_fixed) && - (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) { - is_uniform = 0; - type = mtrr_type_lookup_fixed(start, end); - goto out; - } - - /* - * Look up the variable ranges. Look of multiple ranges matching - * this address and pick type as per MTRR precedence. - */ - type = mtrr_type_lookup_variable(start, end, &partial_end, - &repeat, &is_uniform); + for (i = 0; i < cache_map_n && start < end; i++) { + if (start >= cache_map[i].end) + continue; + if (start < cache_map[i].start) + type = type_merge(type, mtrr_state.def_type, uniform); + type = type_merge(type, cache_map[i].type, uniform); - /* - * Common path is with repeat = 0. - * However, we can have cases where [start:end] spans across some - * MTRR ranges and/or the default type. Do repeated lookups for - * that case here. - */ - while (repeat) { - prev_type = type; - start = partial_end; - is_uniform = 0; - type = mtrr_type_lookup_variable(start, end, &partial_end, - &repeat, &dummy); - - if (check_type_overlap(&prev_type, &type)) - goto out; + start = cache_map[i].end; } - if (mtrr_tom2 && (start >= (1ULL<<32)) && (end < mtrr_tom2)) - type = MTRR_TYPE_WRBACK; + if (start < end) + type = type_merge(type, mtrr_state.def_type, uniform); -out: - *uniform = is_uniform; return type; } From patchwork Tue May 2 12:09:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89338 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp568734vqo; Tue, 2 May 2023 05:26:01 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7P3UPDipIDloqSCiKwYMRmWDMJDaMI9h6bvGJfTgjnsCalqqVcN4wGD0BBGJ9wMDCzdZik X-Received: by 2002:a05:6a20:d90b:b0:f0:7b96:b1a4 with SMTP id jd11-20020a056a20d90b00b000f07b96b1a4mr19568701pzb.27.1683030361592; Tue, 02 May 2023 05:26:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030361; cv=none; d=google.com; s=arc-20160816; b=ONlNSEY9HJ9nwvUjlkByx7OgtPdfYyh1iduZLlvLxNq7vtN6Tec2phBICm2Dy4UjsR i5/GHp9MJPzGzQkzgTNRmDnFW7ybYzuTyopWcL4JFrpMPTpVjxqDKIHumlmNcux4lhbT NJACHpzRFS6tqafNarG9TjYOrvYZxPTedv0P7hB3MhnSL7a7vx6+KuboWmKP29ot1pZS osVqffvbdgv5fbzDYKoDd3Zzm7OQIMFuO/8huYdRc3pKpYg77ORITbx7okDlJTleQyfw 4ENIOZBRzrFTen6cHd1ro4EkcwH5T0ns6ncG/a3CW4ddc8n8MHVE++BBdI/kSP3X8VId w/5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0Fxlor4ogQZhTZdSwvbNUbceLjLoQ8QlMss7trdhHE0=; b=F9Ni6g/+0miLIzpx4hOFBYB9lqcFpwtkmu4mRNcMhxIv3JIOmgBTJHjzpdVqy1rfDv W2KjK/g+D9rge8eooUh7HiLNfSTQxSrwOoHjfUEp/GoSEfVq0zmZJFOeN1HitAxSHLF5 0gE1FiFmkk/VHpVNbcE4z8qTaeZmADwUdm9IR3rAXhH5ODs4sCmk/X5gNwPSFiFtaPlU jTC7KKzPuMU8d7Muk6n41m/mutd3BdvwxKL3R+ZZ0iJLqJZGsPOxLf5GsuFXgYIv5d1H n6hwcXU7nErJnUq3iU+5zJ97pgEsT7GmbJOVCUhWyXDzG1bun0yX/Y5ijFYz8Jbs1Erb CI6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=rpJgFiKs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Linus Torvalds Subject: [PATCH v6 14/16] x86/mtrr: don't let mtrr_type_lookup() return MTRR_TYPE_INVALID Date: Tue, 2 May 2023 14:09:29 +0200 Message-Id: <20230502120931.20719-15-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764785244380715947?= X-GMAIL-MSGID: =?utf-8?q?1764785244380715947?= mtrr_type_lookup() should always return a valid memory type. In case there is no information available, it should return the default UC. This will remove the last case where mtrr_type_lookup() can return MTRR_TYPE_INVALID, so adjust the comment in include/uapi/asm/mtrr.h. Note that removing the MTRR_TYPE_INVALID #define from that header could break user code, so it has to stay. At the same time the mtrr_type_lookup() stub for the !CONFIG_MTRR case should set uniform to 1, as if the memory range would be covered by no MTRR at all. Suggested-by: Linus Torvalds Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - always set uniform - set uniform to 1 in case of disabled MTRRs (Linus Torvalds) V3: - adjust include/uapi/asm/mtrr.h comment --- arch/x86/include/asm/mtrr.h | 7 +++++-- arch/x86/include/uapi/asm/mtrr.h | 6 +++--- arch/x86/kernel/cpu/mtrr/generic.c | 4 ++-- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 9837fe34e58b..9776a4d576f8 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -78,9 +78,12 @@ static inline void mtrr_overwrite_state(struct mtrr_var_range *var, static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform) { /* - * Return no-MTRRs: + * Return the default MTRR type, without any known other types in + * that range. */ - return MTRR_TYPE_INVALID; + *uniform = 1; + + return MTRR_TYPE_UNCACHABLE; } #define mtrr_save_fixed_ranges(arg) do {} while (0) #define mtrr_save_state() do {} while (0) diff --git a/arch/x86/include/uapi/asm/mtrr.h b/arch/x86/include/uapi/asm/mtrr.h index 376563f2bac1..4aa05c2ffa78 100644 --- a/arch/x86/include/uapi/asm/mtrr.h +++ b/arch/x86/include/uapi/asm/mtrr.h @@ -115,9 +115,9 @@ struct mtrr_state_type { #define MTRR_NUM_TYPES 7 /* - * Invalid MTRR memory type. mtrr_type_lookup() returns this value when - * MTRRs are disabled. Note, this value is allocated from the reserved - * values (0x7-0xff) of the MTRR memory types. + * Invalid MTRR memory type. No longer used outside of MTRR code. + * Note, this value is allocated from the reserved values (0x7-0xff) of + * the MTRR memory types. */ #define MTRR_TYPE_INVALID 0xff diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 2197e835e98c..bb124f16f88c 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -510,13 +510,13 @@ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) if (!mtrr_state_set) { *uniform = 0; /* Uniformity is unknown. */ - return MTRR_TYPE_INVALID; + return MTRR_TYPE_UNCACHABLE; } *uniform = 1; if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) - return MTRR_TYPE_INVALID; + return MTRR_TYPE_UNCACHABLE; for (i = 0; i < cache_map_n && start < end; i++) { if (start >= cache_map[i].end) From patchwork Tue May 2 12:09:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89324 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp561724vqo; Tue, 2 May 2023 05:15:40 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5QK+DDQGkiOzJpB8tAayz+6Gel+z1brlBkoAiMGknqL4JO7VWMB/OWWgfuPC3NgcPkfgdw X-Received: by 2002:a05:6a20:7d97:b0:f8:c1a:b2f6 with SMTP id v23-20020a056a207d9700b000f80c1ab2f6mr22821375pzj.49.1683029739840; Tue, 02 May 2023 05:15:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683029739; cv=none; d=google.com; s=arc-20160816; b=tTtTiTUm77QQpCkilbH4SNzBNp6cQhrX/9aw0zXfTgQrWW+szCaYDCC+bAD1NnRuvZ cktY5D6PwkzCZV++iUmipMBVWWKAqWDj4R9OkeQb2C/VeRlAtQsD4WH6D5BPIN2TNpL9 xWnokRfmfZrrEs8xwBZa5tTHbbgml+BNcl5D4bTTjfeX8vHSro6l8pfgRRs4yx/C2oSv JBIU0Tzc+zAYr3WpBhZBJ3Zh9nKfeb56R8cp7dNHd3CP7XvjrAQMT2zbat+bCqsM48Hl hVyFoaWxgbzvCw5qWLEtIJRvB7T7VQx6IVsw1OaLvr3sccBRNC1vPG7HVxtH9jLHWOKm 7IRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PLhZnRzaTF/w19VvaTwREzeMUwLtgou6VVO1Iy9aXOI=; b=0xJzzN7AHfcZllHuAD2TTYU1VNlHv16Ax0lST3M2YXV7OhQeb3oKofXMIVZUlEXUhx 0kJCxLl9i4U+HTes6bG1wRBoh5xMywfYSvvDZmOF+AU7F033Dlvuo2EeKXlHbmUxPHn5 FK+gvF31Wqp8AxIpyMSsIMefm0KC4vR7OIP3H6wmDsgzUKa8VP7RZooN0726FAsyI9JL ILpHIyvnVtHOLXAfAuNHPC4SI+9loPOQzI0SexICgDHf3HTHkOl7pXlee4Bil4omqm5F Ih3UGtDCkukIryZeI8P4kLs903z320WqJVA8uEpiAal9FdHKiuAlqZdOSuf5dlBAnbEt wCRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=uJipgjVS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Linus Torvalds Subject: [PATCH v6 15/16] x86/mm: only check uniform after calling mtrr_type_lookup() Date: Tue, 2 May 2023 14:09:30 +0200 Message-Id: <20230502120931.20719-16-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764784592639109368?= X-GMAIL-MSGID: =?utf-8?q?1764784592639109368?= Today pud_set_huge() and pmd_set_huge() test for the MTRR type to be WB or INVALID after calling mtrr_type_lookup(). Those tests can be dropped, as the only reason to not use a large mapping would be uniform being 0. Any MTRR type can be accepted as long as it applies to the whole memory range covered by the mapping, as the alternative would only be to map the same region with smaller pages instead, using the same PAT type as for the large mapping. Suggested-by: Linus Torvalds Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - adapt comment for pud_set_huge() --- arch/x86/mm/pgtable.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index e4f499eb0f29..15a8009a4480 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -702,14 +702,8 @@ void p4d_clear_huge(p4d_t *p4d) * pud_set_huge - setup kernel PUD mapping * * MTRRs can override PAT memory types with 4KiB granularity. Therefore, this - * function sets up a huge page only if any of the following conditions are met: - * - * - MTRRs are disabled, or - * - * - MTRRs are enabled and the range is completely covered by a single MTRR, or - * - * - MTRRs are enabled and the corresponding MTRR memory type is WB, which - * has no effect on the requested PAT memory type. + * function sets up a huge page only if the complete range has the same MTRR + * caching mode. * * Callers should try to decrease page size (1GB -> 2MB -> 4K) if the bigger * page mapping attempt fails. @@ -718,11 +712,10 @@ void p4d_clear_huge(p4d_t *p4d) */ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) { - u8 mtrr, uniform; + u8 uniform; - mtrr = mtrr_type_lookup(addr, addr + PUD_SIZE, &uniform); - if ((mtrr != MTRR_TYPE_INVALID) && (!uniform) && - (mtrr != MTRR_TYPE_WRBACK)) + mtrr_type_lookup(addr, addr + PUD_SIZE, &uniform); + if (!uniform) return 0; /* Bail out if we are we on a populated non-leaf entry: */ @@ -745,11 +738,10 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) */ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) { - u8 mtrr, uniform; + u8 uniform; - mtrr = mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform); - if ((mtrr != MTRR_TYPE_INVALID) && (!uniform) && - (mtrr != MTRR_TYPE_WRBACK)) { + mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform); + if (!uniform) { pr_warn_once("%s: Cannot satisfy [mem %#010llx-%#010llx] with a huge-page mapping due to MTRR override.\n", __func__, addr, addr + PMD_SIZE); return 0; From patchwork Tue May 2 12:09:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Juergen Gross X-Patchwork-Id: 89327 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp565986vqo; Tue, 2 May 2023 05:21:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ41GkfIhR0T3mroSlfnyGkiwfeQhpx/C29iCrpxTq/LV+FUBPu5eI5M7J8nlxmoEO49Kpj0 X-Received: by 2002:a17:902:e747:b0:1aa:e938:3ddf with SMTP id p7-20020a170902e74700b001aae9383ddfmr8921249plf.7.1683030109108; Tue, 02 May 2023 05:21:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683030109; cv=none; d=google.com; s=arc-20160816; b=wzFoB+lXHQnqzHjrVTqHC5gMcJ2HywN/8Rcobxso9ZrOQESCwN25pxFU5Z8z63vRWX skaFQcT2KO306OORr27JX4HoZCglrlUREXkDyKiJdN6/zbetKxk7rwfGK437Qr3HpR1c WZsCjxpFm1k2B5oalcEoSl6oQOIDNW6xGYF9mPDeZn+HsiqxiwdBnVpdUiAXQ66jQhGK LdwXV+b8+xEKRogl2bry3UBCvyH7K32MmsN44Lxc0RspUjwkEvgR3OVyO7xkThZILurH vKAKmiA7d7SufTF4t8YZknUFph20KTyA/Ahm8zhzBy7e2XgzcmrIrEFesQO4JMpXCbHv XtAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yE3GJ8XlMqvTVg/rE4n5W1aKtBvva0asDK+aR3lyADA=; b=HnrCm34VdrB7HrbzhQzoKefp8w0vYwJ1gFcHZy2RHmsd+FOEDG2vgd9Qbnt8d+z85o DfUupZWw1TocvVN0BDCLTpESv0v4h9hF9YHzlpTG0IWuA8xg6ZbFh2vl6mq4Tj8qxpqn rr4R6BctpEn8ZflWx7wYbCUtls1muBhkNn7C5GVng5aivbjCraB99RfoSQAfYAz+SrH0 ZkO3RA/+Mhf9fw16NDkjz7xHyXzd39L2c4/bfsnvuwW99myApZfc0ameCI6aBJ9FWDyx utDl5EYmbCVhEQR9dn8wbpt+OSSffcRnaedLES1fJovF8J3wjMf+33yCAbFY4lau1xj+ 08GQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=cW7kpLLB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=suse.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" Subject: [PATCH v6 16/16] x86/mtrr: remove unused code Date: Tue, 2 May 2023 14:09:31 +0200 Message-Id: <20230502120931.20719-17-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764784979418623471?= X-GMAIL-MSGID: =?utf-8?q?1764784979418623471?= mtrr_centaur_report_mcr() isn't used by anyone, so it can be removed. Signed-off-by: Juergen Gross --- V5: - new patch --- arch/x86/include/asm/mtrr.h | 4 ---- arch/x86/kernel/cpu/mtrr/centaur.c | 9 --------- 2 files changed, 13 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 9776a4d576f8..2185a292a50f 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -61,7 +61,6 @@ extern int mtrr_add_page(unsigned long base, unsigned long size, unsigned int type, bool increment); extern int mtrr_del(int reg, unsigned long base, unsigned long size); extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); -extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); extern void mtrr_bp_restore(void); extern int mtrr_trim_uncached_memory(unsigned long end_pfn); extern int amd_special_default_mtrr(void); @@ -109,9 +108,6 @@ static inline int mtrr_trim_uncached_memory(unsigned long end_pfn) { return 0; } -static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) -{ -} #define mtrr_bp_init() do {} while (0) #define mtrr_bp_restore() do {} while (0) #define mtrr_disable() do {} while (0) diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/centaur.c index 4466ddeb0125..6f6c3ae92943 100644 --- a/arch/x86/kernel/cpu/mtrr/centaur.c +++ b/arch/x86/kernel/cpu/mtrr/centaur.c @@ -45,15 +45,6 @@ centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg) return -ENOSPC; } -/* - * Report boot time MCR setups - */ -void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) -{ - centaur_mcr[mcr].low = lo; - centaur_mcr[mcr].high = hi; -} - static void centaur_get_mcr(unsigned int reg, unsigned long *base, unsigned long *size, mtrr_type * type)