From patchwork Tue May 2 05:04:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U3RhbmxleSBDaGFuZ1vmmIzogrLlvrdd?= X-Patchwork-Id: 89248 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp374906vqo; Mon, 1 May 2023 22:35:07 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ75LjyBENl36NBzPYI7AJe15hJNXhZEsmGj3lQznIsJ2C2SEyjszZyz5cyUHOZnRKc6+WHK X-Received: by 2002:a17:90a:7307:b0:23f:9445:318e with SMTP id m7-20020a17090a730700b0023f9445318emr19476702pjk.3.1683005706689; Mon, 01 May 2023 22:35:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683005706; cv=none; d=google.com; s=arc-20160816; b=uT271YwZ4QRWUjOPQxPg/k4bWQvQakjwV1TO+oChLZCCp8+z03Gqadk2JLaTgBOIUM 5bVcb8g39DBlkak6n/mWDU/pk2muSktL5OVOqyOFh8tr1LIBfP2Mjk7guIriyoBq0FN5 jDbkTAgyaC8fW/3oeu4HZ9fCCvcMYWPqTqMPAe7jEex4/lIYlUigEJ0nyBdHp1naRvC+ JKRPrBW/LMpqtFIiQpy/HmEBbBcDdMxFGMGPyGcZQm08J+hHy9OsmLISoqFnn4YVq2M0 pLyx9p29Y2ZZ8hT9W/L/98e8mc82JKRGtmozxI2iiBK27gtk0dFXuT5Z0Lz+qWIl3/mC 7GTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:authenticated-by; bh=esaERRgEFuGt0t0HtJOyEHRbQrcOdCJ4em2c1exghj4=; b=cX11vpZu+o04SDqxuccRJMQbxAK4IVjvWtFyoNPYJIoIYzi5nDfNqIee9OhFOIi7Kn tzQ29ovW4bnonO2uf8V6YTJ/45wAgj4UU6mB+7iGIMRwli0ZWfjz1UhbOTMTS6m+705s vzIVQRWnCSRkg7I4DDu4IF8BhTkOUzq+BTR/aomA6xVUFaF5etUHRAPjT4iSLaym6/Fd H92RPG5XiEXoaquetffIHM87e5TSnPiVLP+UB5qDvc35b1YxazCjOHUF+7rj3eAIGXlB vmrksL7jKtJsp2VmgzOSp2//zZU3JpZhCxFk/C5zRXqDiq2Ai/Y5SCogV4cVfYOzGWy/ dMTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id mr20-20020a17090b239400b002336940f887si10501045pjb.61.2023.05.01.22.34.52; Mon, 01 May 2023 22:35:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233498AbjEBFFS (ORCPT + 99 others); Tue, 2 May 2023 01:05:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229449AbjEBFFK (ORCPT ); Tue, 2 May 2023 01:05:10 -0400 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1C6140D9; Mon, 1 May 2023 22:05:07 -0700 (PDT) Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.77 with qID 34254n4Z2007203, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/2.81/5.90) with ESMTPS id 34254n4Z2007203 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK); Tue, 2 May 2023 13:04:49 +0800 Received: from RTEXMBS05.realtek.com.tw (172.21.6.98) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Tue, 2 May 2023 13:04:53 +0800 Received: from RTEXH36506.realtek.com.tw (172.21.6.27) by RTEXMBS05.realtek.com.tw (172.21.6.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 2 May 2023 13:04:52 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server id 15.1.2507.17 via Frontend Transport; Tue, 2 May 2023 13:04:52 +0800 From: Stanley Chang To: Thinh Nguyen CC: Stanley Chang , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Felipe Balbi , , , Subject: [PATCH v4 1/2] usb: dwc3: core: add support for RTK SoC custom's global register start address Date: Tue, 2 May 2023 13:04:46 +0800 Message-ID: <20230502050452.27276-1-stanley_chang@realtek.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 X-KSE-ServerInfo: RTEXMBS05.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764759391908822526?= X-GMAIL-MSGID: =?utf-8?q?1764759391908822526?= The RTK DHC SoCs were designed, the global register address offset at 0x8100. The default address offset is constant at DWC3_GLOBALS_REGS_START (0xc100). Therefore, add the compatible name of device-tree to specify the SoC custom's global register start address. Signed-off-by: Stanley Chang --- v3 to v4 change: Use the compatible name to specify the global register address offset. If the compatible name is "snps,dwc3-rtk-soc", then the offset use 0x8100. Otherwise, the offset is default value 0xc100. v2 to v3 change: 1. Fix the dtschema validation error. v1 to v2 change: 1. Change the name of the property "snps,global-regs-starting-offset". 2. Adjust the format of comment. 3. Add initial value of the global_regs_starting_offset 4. Remove the log of dev_info. --- drivers/usb/dwc3/core.c | 18 +++++++++++++++--- drivers/usb/dwc3/core.h | 5 +++++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 0beaab932e7d..4f69b26d7dab 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -1793,12 +1794,17 @@ static int dwc3_probe(struct platform_device *pdev) dwc->xhci_resources[0].flags = res->flags; dwc->xhci_resources[0].name = res->name; + dwc->global_regs_starting_offset = (u32)(uintptr_t) + of_device_get_match_data(dev); + if (!dwc->global_regs_starting_offset) + dwc->global_regs_starting_offset = DWC3_GLOBALS_REGS_START; + /* * Request memory region but exclude xHCI regs, * since it will be requested by the xhci-plat driver. */ dwc_res = *res; - dwc_res.start += DWC3_GLOBALS_REGS_START; + dwc_res.start += dwc->global_regs_starting_offset; regs = devm_ioremap_resource(dev, &dwc_res); if (IS_ERR(regs)) @@ -2224,10 +2230,16 @@ static const struct dev_pm_ops dwc3_dev_pm_ops = { #ifdef CONFIG_OF static const struct of_device_id of_dwc3_match[] = { { - .compatible = "snps,dwc3" + .compatible = "snps,dwc3", + .data = (void *)DWC3_GLOBALS_REGS_START, + }, + { + .compatible = "snps,dwc3-rtk-soc", + .data = (void *)DWC3_GLOBALS_REGS_START_FOR_RTK, }, { - .compatible = "synopsys,dwc3" + .compatible = "synopsys,dwc3", + .data = (void *)DWC3_GLOBALS_REGS_START, }, { }, }; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index d56457c02996..46557cf52f4b 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -84,6 +84,8 @@ #define DWC3_OTG_REGS_START 0xcc00 #define DWC3_OTG_REGS_END 0xccff +#define DWC3_GLOBALS_REGS_START_FOR_RTK 0x8100 + /* Global Registers */ #define DWC3_GSBUSCFG0 0xc100 #define DWC3_GSBUSCFG1 0xc104 @@ -1118,6 +1120,8 @@ struct dwc3_scratchpad_array { * @wakeup_configured: set if the device is configured for remote wakeup. * @imod_interval: set the interrupt moderation interval in 250ns * increments or 0 to disable. + * @global_regs_starting_offset: set the dwc3 global register start address + * and it is default at DWC3_GLOBALS_REGS_START (0xc100). * @max_cfg_eps: current max number of IN eps used across all USB configs. * @last_fifo_depth: last fifo depth used to determine next fifo ram start * address. @@ -1334,6 +1338,7 @@ struct dwc3 { unsigned wakeup_configured:1; u16 imod_interval; + u32 global_regs_starting_offset; int max_cfg_eps; int last_fifo_depth; From patchwork Tue May 2 05:04:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U3RhbmxleSBDaGFuZ1vmmIzogrLlvrdd?= X-Patchwork-Id: 89247 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp365533vqo; Mon, 1 May 2023 22:09:32 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ76vot03jS8MLSY6IiAbbx/RIgEdSWXExc1mH2Tt3fZxxNEdk4wHT0Xwp4Vx8OvivlvSZhg X-Received: by 2002:a05:6a00:2451:b0:627:f0e1:4fbf with SMTP id d17-20020a056a00245100b00627f0e14fbfmr22768897pfj.33.1683004172171; Mon, 01 May 2023 22:09:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683004172; cv=none; d=google.com; s=arc-20160816; b=uHbQzqUdqOw7V3sykQhTQ6rsEcDsNlwvf0E8b0gkz1CG10Pd+mX4tamkQAxhKgAvso QUSJW5r7LQDMeoC5KwnJnybSP2WOrfK5GT/2IgsBmSObEjhkR2Prytd/yiCqqxKgvBqb Xg7QbpdFUM4iV87aUAGIVYjSL5ymRyvgpkCcsclsseMhRjOhPwqnoW2q87Pt399H0S9v K5CR9CgnpUHLZOOTAUbKtMfk8XqHBQ0GMqdQgZhMuanI5Ncgs3cS2/jQlX/B2y0QwApE MH9kg/7oyO3fum1s4rjON0CMz6zKogBayubRd4A4JOEgWAmwqvBCCVCg+jJrFF0zrIBh j6xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :authenticated-by; bh=vjL0vcoZeaHXCWFY1qW/90IvygdwExHzpBx3LWJZUN4=; b=Nlx1y7a6BpmJeysUHgDeRY437bW5eBHoFpAM8WlflUKyGpnI01Hyv32zpl4/gzmBqO BJPOZPWlItiExS1YezgJOTisyQAZ5A1DtwtFxpMvdK3HPacTGbmUwtkVfoMJRZk1MmmZ ci45l9l3eTMiH4lI2wgAkqBpwlFewsNrU8cAoWMiYMpMHy3LTTaIZQWodXy348aIfMX9 LFlSeddYzIUlHGtXRW1cTVOJGspHxt4ZT2pu7+L8+lmUAD5UiAWkeoj8O3uc76raCoKi XBL3d8kNYMUd/vYzTUbgPKLAdU5i3REcqYUFmVvqH51DmRRDmeGb5E2uyR2kzACC+NyB sHVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e11-20020aa7980b000000b0063b68fa0803si30537736pfl.268.2023.05.01.22.09.17; Mon, 01 May 2023 22:09:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233481AbjEBFFP (ORCPT + 99 others); Tue, 2 May 2023 01:05:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229379AbjEBFFK (ORCPT ); Tue, 2 May 2023 01:05:10 -0400 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F13F03ABB; Mon, 1 May 2023 22:05:07 -0700 (PDT) Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.77 with qID 34254n3G2007207, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/2.81/5.90) with ESMTPS id 34254n3G2007207 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK); Tue, 2 May 2023 13:04:50 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Tue, 2 May 2023 13:04:53 +0800 Received: from RTEXH36506.realtek.com.tw (172.21.6.27) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Tue, 2 May 2023 13:04:53 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server id 15.1.2507.17 via Frontend Transport; Tue, 2 May 2023 13:04:53 +0800 From: Stanley Chang To: Thinh Nguyen CC: Stanley Chang , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Felipe Balbi , , , Subject: [PATCH v4 2/2] dt-bindings: usb: snps,dwc3: Add the compatible name 'snps,dwc3-rtk-soc' Date: Tue, 2 May 2023 13:04:47 +0800 Message-ID: <20230502050452.27276-2-stanley_chang@realtek.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230502050452.27276-1-stanley_chang@realtek.com> References: <20230502050452.27276-1-stanley_chang@realtek.com> MIME-Version: 1.0 X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764757782907595755?= X-GMAIL-MSGID: =?utf-8?q?1764757782907595755?= Add a new compatible name 'snps,dwc3-rtk-soc' of DT for realtek dwc3 core to adjust the global register start address The RTK DHC SoCs were designed, the global register address offset at 0x8100. The default address offset is constant at DWC3_GLOBALS_REGS_START (0xc100). Therefore, add the compatible name of device-tree to specify the SoC custom's global register start address. Signed-off-by: Stanley Chang --- v3 to v4 change: Use the compatible name to specify the global register address offset. If the compatible name is "snps,dwc3-rtk-soc", then the offset use 0x8100. Otherwise, the offset is default value 0xc100. v2 to v3 change: 1. Fix the dtschema validation error. v1 to v2 change: 1. Change the name of the property "snps,global-regs-starting-offset". 2. Adjust the format of comment. 3. Add initial value of the global_regs_starting_offset 4. Remove the log of dev_info. --- Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 50edc4da780e..40d9a461ed93 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -33,6 +33,7 @@ properties: contains: oneOf: - const: snps,dwc3 + - const: snps,dwc3-rtk-soc - const: synopsys,dwc3 deprecated: true