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There are 4 power event irq interrupts supported by this controller (one for each port of multiport). Added all the 4 as non-optional interrupts for SC8280XP-MP Signed-off-by: Krishna Kurapati --- .../devicetree/bindings/usb/qcom,dwc3.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index d84281926f10..2c96da1ce5b8 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -26,6 +26,7 @@ properties: - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp - qcom,sdm660-dwc3 - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 @@ -455,6 +456,26 @@ allOf: - const: dm_hs_phy_irq - const: ss_phy_irq + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-dwc3-mp + then: + properties: + interrupts: + maxItems: 7 + interrupt-names: + items: + - const: pwr_event_1 + - const: pwr_event_2 + - const: pwr_event_3 + - const: pwr_event_4 + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + - const: ss_phy_irq + additionalProperties: false examples: From patchwork Mon May 1 14:34:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 89054 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2742538vqo; Mon, 1 May 2023 07:40:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5PVGO/JbbMsAroZdVwFS4U1FEFTyfc/MoZGGKTq8Oo3uvw+dmdiic2sRSYaEE9lSug912F X-Received: by 2002:a05:6a00:2e1a:b0:5a8:aca5:817d with SMTP id fc26-20020a056a002e1a00b005a8aca5817dmr21256935pfb.5.1682952044195; Mon, 01 May 2023 07:40:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682952044; cv=none; d=google.com; s=arc-20160816; b=IUMzAqGOMUQvVpJ7zdKo5xD8soeG3MiQT/zsKhlRFSbglO12lcGl3CZHKdSnXT+2cW nkCfo5fC+bTWIfFJME2w46ZgV+qQjDhhoMXCmkKWjdDQs41T4rW0IWHmbQLNnpWus4fR X1LuYrEqT7C74EiYm5W3xtmQhOm4yIwos7acBPqzdOx6UK8XbAtaJW88LGFVenkUAXeJ e360sxcxn3pqg3g+RIUXzHOjYSPznd0u+EoVa+cmwFzOBiCGLLHj4RzmCQWZtqMeDUwL 1j6oOTMfITuHFpSpWU9V4fiEuIKwqzC15Tck81uaySNraUd9WugNHXJWfsRO2I5kLzPr Pd1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=16XAQ02AhULJRGeDJY3Qa4c7PEwmcDbL/yccsoDpkbY=; b=R1TIL7oC1wu92mnlFFWzxMb4z8GxOscBIFlnahZ8qTBBhi5/lO6eF7Rrn5yYuzVfC1 i9zFd0lESYEXp0z1fnmObyhEgn+wOwezjZ5Kg1j4R/fO9hApstlKaZUvfleSuh/VjQ6E Q1KaJtiiv25DMowLsi92FXy3cheYO3YcB3/4ct8qeKIrJ2twlMl5CDrhTQ0dv0n77DJX Ts+22bSyfjoAwkeYEvykpw0wL+k2xbVaLBgcZU3KNrr4AuS8tWyJjJFUwzS3UmkhMWMs KECvwal0WUZGINZHsjZspEyrMX7cDqFL+FHgs3r0WT35tDLTfjHWGEOby8UikpLEQl1V 9fCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=nn5KAx9k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Suggested-by: Bjorn Andersson Signed-off-by: Krishna Kurapati --- .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 50edc4da780e..4de0875c2ae1 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -85,15 +85,16 @@ properties: phys: minItems: 1 - maxItems: 2 + maxItems: 8 phy-names: minItems: 1 - maxItems: 2 - items: - enum: - - usb2-phy - - usb3-phy + maxItems: 8 + oneOf: + - items: + enum: [ usb2-phy, usb3-phy ] + - items: + pattern: "^usb[23]-port[0-3]$" power-domains: description: From patchwork Mon May 1 14:34:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 89051 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2740689vqo; Mon, 1 May 2023 07:37:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6ftSmZw02Ji9Y3S8KR49UUnZPOHMUaE5MmNe7rk3l1u1SRzi8WQN+OFmcRaD7oVp8SrDuU X-Received: by 2002:a17:90b:3b8b:b0:23f:9fac:6b35 with SMTP id pc11-20020a17090b3b8b00b0023f9fac6b35mr15102533pjb.39.1682951844799; Mon, 01 May 2023 07:37:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682951844; cv=none; d=google.com; s=arc-20160816; b=wVl1bKFdwEOmiwiyccGuRvZrgEI/kXCgYqWdtwA/iDoks37g7SfdJBqiY+jOdZVfuo fLbH8WhksRLHxZ+kp+I22Mi0vlSWhmr2PA+BFDpJkKNxJY917ylvMTIQhgW3Mkn9HH6y 2/pp65x7uAPz32b/Rwm8+nsbft+ncO5z0Mb0waMIaljNeidB2Fe3GO7huv2C4ZmBHFs8 CSFGR+tqwua7dwjul+k5w/BJk4QdcTXdRDYdkfDDJ4HdVQZjDmvvHBN5G06mzDBaMcZ7 LlOczv3Buc2Qj12Vq3rM0syEUdLX77j0LsLW08SYu07FNQbzavD86dbv4BnBOrtYFEyx anUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XFJuBPrmx95abh1S7SCQciIy/cR4x26RJM+o00++sI8=; b=PvaHnNO3PF8ZtBZ/DB0yYseEZ9Um5ROtTUH6xOF0X2Ze4MaQDHXkT86z7Ll3JmqVcy 7fYTOEbIOT2+5yRYjSyJI+E78wz4OcnNJfGjqOKzSdb6k72GfB9dK+L3pRfmStiVWele y9VhPMJ8Tv7xy2cBLJxiOHq6N6TKrOUcg2eIs4LlSG8FMTebPtrCYt9Q+ZrOrqsfxyG3 P1UveGPf4bvc5tmmwhgYMVNXMaX1HymuJ5665KPY97JjX8o5SQc8WdihDuWGrjJDxCjs a5KELk6JFVZN1YHjaLp8nSBPETiWWrFcvvrWu1OKVa1SIc576jCe+goDgrJ7ZIRjV9vz y5wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=gOISlIkq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Temporarily map XHCI address space for host-only controllers and parse XHCI Extended Capabilities registers to read number of usb2 ports and usb3 ports present on multiport controller. Each USB Port is at least HS capable. The port info for usb2 and usb3 phy are identified as num_usb2_ports and num_usb3_ports. The intention is as follows: Wherever we need to perform phy operations like: LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS() { phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); } If number of usb2 ports is 3, loop can go from index 0-2 for usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure, if the first 2 ports are SS capable or some other ports like (2 and 3) are SS capable. So instead, num_usb2_ports is used to loop around all phy's (both hs and ss) for performing phy operations. If any usb3_generic_phy turns out to be NULL, phy operation just bails out. num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up phy's as we need to know how many SS capable ports are there for this. Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/core.c | 68 +++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 58 +++++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 0beaab932e7d..b8ac7bcee391 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1767,6 +1767,59 @@ static int dwc3_get_clocks(struct dwc3 *dwc) return 0; } +static int dwc3_read_port_info(struct dwc3 *dwc) +{ + void __iomem *regs; + u32 offset; + u32 temp; + u8 major_revision; + int ret = 0; + + /* + * Remap xHCI address space to access XHCI ext cap regs, + * since it is needed to get port info. + */ + regs = ioremap(dwc->xhci_resources[0].start, + resource_size(&dwc->xhci_resources[0])); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + offset = dwc3_xhci_find_next_ext_cap(regs, 0, + XHCI_EXT_CAPS_PROTOCOL); + while (offset) { + temp = readl(regs + offset); + major_revision = XHCI_EXT_PORT_MAJOR(temp); + + temp = readl(regs + offset + 0x08); + if (major_revision == 0x03) { + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(temp); + } else if (major_revision <= 0x02) { + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(temp); + } else { + dev_err(dwc->dev, "port revision seems wrong\n"); + ret = -EINVAL; + goto unmap_reg; + } + + offset = dwc3_xhci_find_next_ext_cap(regs, offset, + XHCI_EXT_CAPS_PROTOCOL); + } + + temp = readl(regs + DWC3_XHCI_HCSPARAMS1); + if (HCS_MAX_PORTS(temp) != (dwc->num_usb3_ports + dwc->num_usb2_ports)) { + dev_err(dwc->dev, "inconsistency in port info\n"); + ret = -EINVAL; + goto unmap_reg; + } + + dev_dbg(dwc->dev, + "hs-ports: %d ss-ports: %d\n", dwc->num_usb2_ports, dwc->num_usb3_ports); + +unmap_reg: + iounmap(regs); + return ret; +} + static int dwc3_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1774,6 +1827,7 @@ static int dwc3_probe(struct platform_device *pdev) void __iomem *regs; struct dwc3 *dwc; int ret; + unsigned int hw_mode; dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); if (!dwc) @@ -1843,6 +1897,20 @@ static int dwc3_probe(struct platform_device *pdev) goto err_disable_clks; } + /* + * Currently DWC3 controllers that are host-only capable + * support Multiport + */ + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { + ret = dwc3_read_port_info(dwc); + if (ret) + goto err_disable_clks; + } else { + dwc->num_usb2_ports = 1; + dwc->num_usb3_ports = 1; + } + spin_lock_init(&dwc->lock); mutex_init(&dwc->mutex); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index d56457c02996..21312703e053 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -35,6 +35,17 @@ #define DWC3_MSG_MAX 500 +/* Define XHCI Extcap register offsets for getting multiport info */ +#define XHCI_HCC_PARAMS_OFFSET 0x10 +#define DWC3_XHCI_HCSPARAMS1 0x04 +#define XHCI_EXT_CAPS_PROTOCOL 2 +#define XHCI_HCC_EXT_CAPS(x) (((x) >> 16) & 0xffff) +#define XHCI_EXT_CAPS_ID(x) (((x) >> 0) & 0xff) +#define XHCI_EXT_CAPS_NEXT(x) (((x) >> 8) & 0xff) +#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) +#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) +#define HCS_MAX_PORTS(x) (((x) >> 24) & 0x7f) + /* Global constants */ #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ @@ -1025,6 +1036,8 @@ struct dwc3_scratchpad_array { * @usb_psy: pointer to power supply interface. * @usb2_phy: pointer to USB2 PHY * @usb3_phy: pointer to USB3 PHY + * @num_usb2_ports: number of usb2 ports. + * @num_usb3_ports: number of usb3 ports. * @usb2_generic_phy: pointer to USB2 PHY * @usb3_generic_phy: pointer to USB3 PHY * @phys_ready: flag to indicate that PHYs are ready @@ -1162,6 +1175,9 @@ struct dwc3 { struct usb_phy *usb2_phy; struct usb_phy *usb3_phy; + u32 num_usb2_ports; + u32 num_usb3_ports; + struct phy *usb2_generic_phy; struct phy *usb3_generic_phy; @@ -1650,4 +1666,46 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc) { } #endif +/** + * dwc3_xhci_find_next_ext_cap - Find the offset of the extended capabilities + * with capability ID id. + * + * @base PCI MMIO registers base address. + * @start address at which to start looking, (0 or HCC_PARAMS to start at + * beginning of list) + * @id Extended capability ID to search for, or 0 for the next + * capability + * + * Returns the offset of the next matching extended capability structure. + * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL, + * and this provides a way to find them all. + */ +static inline int dwc3_xhci_find_next_ext_cap(void __iomem *base, u32 start, int id) +{ + u32 val; + u32 next; + u32 offset; + + offset = start; + if (!start || start == XHCI_HCC_PARAMS_OFFSET) { + val = readl(base + XHCI_HCC_PARAMS_OFFSET); + if (val == ~0) + return 0; + offset = XHCI_HCC_EXT_CAPS(val) << 2; + if (!offset) + return 0; + } + do { + val = readl(base + offset); + if (val == ~0) + return 0; + if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id)) + return offset; + + next = XHCI_EXT_CAPS_NEXT(val); + offset += next << 2; + } while (next); + + return 0; +} #endif /* __DRIVERS_USB_DWC3_CORE_H */ From patchwork Mon May 1 14:34:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 89050 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2740608vqo; Mon, 1 May 2023 07:37:15 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7rgw93Qf9qKTzWiVtD+vphiZa1VEr8ptVZZH+Qcdrh5Ye+SnyZooX26q8Hpnz2ViHeOfTP X-Received: by 2002:a05:6a20:c1a4:b0:eb:b8:bdc8 with SMTP id bg36-20020a056a20c1a400b000eb00b8bdc8mr14990916pzb.57.1682951835415; Mon, 01 May 2023 07:37:15 -0700 (PDT) ARC-Seal: i=1; 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Trying to setup them up during core_init leads to a crash. For DRD/Peripheral supported controllers, event buffer setup is done again in gadget_pullup. Skip setup or cleanup of event buffers if controller is host-only capable. Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/core.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index b8ac7bcee391..8625fc5c7ab4 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -835,7 +835,12 @@ static void dwc3_clk_disable(struct dwc3 *dwc) static void dwc3_core_exit(struct dwc3 *dwc) { - dwc3_event_buffers_cleanup(dwc); + unsigned int hw_mode; + + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) + dwc3_event_buffers_cleanup(dwc); + dwc3_phy_power_off(dwc); dwc3_phy_exit(dwc); dwc3_clk_disable(dwc); @@ -1141,10 +1146,12 @@ static int dwc3_core_init(struct dwc3 *dwc) if (ret) goto err_exit_phy; - ret = dwc3_event_buffers_setup(dwc); - if (ret) { - dev_err(dwc->dev, "failed to setup event buffers\n"); - goto err_power_off_phy; + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) { + ret = dwc3_event_buffers_setup(dwc); + if (ret) { + dev_err(dwc->dev, "failed to setup event buffers\n"); + goto err_power_off_phy; + } } /* @@ -1958,7 +1965,10 @@ static int dwc3_probe(struct platform_device *pdev) err_exit_debugfs: dwc3_debugfs_exit(dwc); - dwc3_event_buffers_cleanup(dwc); + + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) + dwc3_event_buffers_cleanup(dwc); + dwc3_phy_power_off(dwc); dwc3_phy_exit(dwc); dwc3_ulpi_exit(dwc); From patchwork Mon May 1 14:34:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 89057 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2747713vqo; Mon, 1 May 2023 07:49:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4UG0g2QReWyhpthNSKSgcDw+HJLUGvePhJK/wa+04DDFt2ULXkbLaaYyF95NBv0TOzDJZP X-Received: by 2002:a05:6a00:139e:b0:594:1f1c:3d3a with SMTP id t30-20020a056a00139e00b005941f1c3d3amr24176895pfg.15.1682952588878; Mon, 01 May 2023 07:49:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682952588; cv=none; d=google.com; s=arc-20160816; b=NYMlcntOk1ZNGGHtZQwYODkODDsMEzfBVLnVfOluqhlhDIpIUOuTrrfsoH7nk8FgmR 8mTZ3VzjHzCUP0g9tiG5VJ0e8IoowjSISJFF7tS7YRS+AklV3IOBVgltuaQmEj7ZjCJB NOkwQT0eEXPxvz/x0NxTw8li7DgHzPHvM15oP8QMr8JgyHsUhnFDuWKMxDCYXGnpj6bz EVihql7RIMSsAoC99T7ZgcqWqO0bWFYwlgGSqb0HAcSqZ48g3Xz8CkrFf2VQISC5JYKM Acn0ZwIugayq5Q8PUverckjZ/0ykrBuRMbALumViXScM1opPKeDOKYEpEdxxJ9k7IuiO I2uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hCZCG+ig/Pn4r3DHalNmN3Yw2tzyMX8pdPJp+kRgvhA=; b=YvrsDkC/7SzBN4TWlHLupJOHnJmplm8PKFPKwjxcdpZZlk9G2SodU3hQRIidIZoP/L rfYS2yB3I4iJJWgPjIRb8OamxlQXLWqoTXt5klFix9DU0kFnWjKvB+ZqYPg1Ma6q9h/G zaAbJdajsBD0/+oA5JZD9qDbeXdvox9GCn35KjXolyiWYrMN5BZsyrBXLtP8a1GC43mI YJ1gsls7ipdeOP7ZIjtvrui0HwIa+y9zcSVfUSLzFSPb3ltb1s63s45bx/IGL19XFPEy VcYRp0OD2xTTLgVVdQlFlq6Sd3uaZblCbNgTFymDOV0T4snXyI3xcO467X9SrQgsKkku 62ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Jyd2Mk2O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z21-20020a63d015000000b0051b6a773204si27108485pgf.374.2023.05.01.07.49.36; Mon, 01 May 2023 07:49:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Jyd2Mk2O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229556AbjEAOf6 (ORCPT + 99 others); Mon, 1 May 2023 10:35:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232398AbjEAOfu (ORCPT ); Mon, 1 May 2023 10:35:50 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8518513A; Mon, 1 May 2023 07:35:46 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 341EZ0j2031912; Mon, 1 May 2023 14:35:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=hCZCG+ig/Pn4r3DHalNmN3Yw2tzyMX8pdPJp+kRgvhA=; b=Jyd2Mk2OBtpUHwwlzR/qhqIAloBtshtsepQTPvh+bncxzIYZJ2/m16GEgnwmokZalGkY fakLGcnUFj7PoOfJXf+EhBUeHLkn6LIPc1/i37nhdoliOalQFd+ueWU3Np8a+706ZATz pnMlbfJinkNr3pPaWAOhIvyIZeZ8/ix90bGlAPCMqlV9mm2HxHldxdkZ+72gZyghM4V/ ME60iKikkceH67Xfla4p2Y4IAGmt5T1eZLoFYIn1c3KJUlWfwM9mMZ+GSkOUumK+m/sg UruZ62Rj/U/WrKbLFpXktaFBMP8NtfOXK1bF6R3eegyJkoD19pYBkwiamPg86S16pkTm Mg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3q8t8ubrrr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 01 May 2023 14:35:34 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 341EZXEW012479 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 1 May 2023 14:35:33 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Mon, 1 May 2023 07:35:26 -0700 From: Krishna Kurapati To: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi , Wesley Cheng CC: , , , , , , , , , , Krishna Kurapati Subject: [PATCH v7 5/9] usb: dwc3: core: Refactor PHY logic to support Multiport Controller Date: Mon, 1 May 2023 20:04:41 +0530 Message-ID: <20230501143445.3851-6-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230501143445.3851-1-quic_kriskura@quicinc.com> References: <20230501143445.3851-1-quic_kriskura@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: -LYNkHvOUVG6qd5Gh2mOd2dvAAs3tlwr X-Proofpoint-GUID: -LYNkHvOUVG6qd5Gh2mOd2dvAAs3tlwr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-01_07,2023-04-27_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305010115 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764703694229771598?= X-GMAIL-MSGID: =?utf-8?q?1764703694229771598?= Currently the DWC3 driver supports only single port controller which requires at most one HS and one SS PHY. But the DWC3 USB controller can be connected to multiple ports and each port can have their own PHYs. Each port of the multiport controller can either be HS+SS capable or HS only capable Proper quantification of them is required to modify GUSB2PHYCFG and GUSB3PIPECTL registers appropriately. Add support for detecting, obtaining and configuring phy's supported by a multiport controller and limit the max number of ports supported to 4. Signed-off-by: Harsh Agarwal Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/core.c | 262 +++++++++++++++++++++++++++++----------- drivers/usb/dwc3/core.h | 12 +- drivers/usb/dwc3/drd.c | 13 +- 3 files changed, 209 insertions(+), 78 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 8625fc5c7ab4..b91c3f965abc 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -121,6 +121,7 @@ static void __dwc3_set_mode(struct work_struct *work) struct dwc3 *dwc = work_to_dwc(work); unsigned long flags; int ret; + int i; u32 reg; u32 desired_dr_role; @@ -200,8 +201,10 @@ static void __dwc3_set_mode(struct work_struct *work) } else { if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, true); - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); + for (i = 0; i < dwc->num_usb2_ports; i++) { + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); + } if (dwc->dis_split_quirk) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); reg |= DWC3_GUCTL3_SPLITDISABLE; @@ -216,8 +219,8 @@ static void __dwc3_set_mode(struct work_struct *work) if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, false); - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); ret = dwc3_gadget_init(dwc); if (ret) @@ -575,22 +578,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc) return ret; } -/** - * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core - * @dwc: Pointer to our controller context structure - * - * Returns 0 on success. The USB PHY interfaces are configured but not - * initialized. The PHY interfaces and the PHYs get initialized together with - * the core in dwc3_core_init. - */ -static int dwc3_phy_setup(struct dwc3 *dwc) +static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) { unsigned int hw_mode; u32 reg; hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index)); /* * Make sure UX_EXIT_PX is cleared as that causes issues with some @@ -645,9 +640,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_del_phy_power_chg_quirk) reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg); - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + return 0; +} + +static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) +{ + unsigned int hw_mode; + u32 reg; + + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); + + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index)); /* Select the HS PHY interface */ switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { @@ -659,7 +664,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc) } else if (dwc->hsphy_interface && !strncmp(dwc->hsphy_interface, "ulpi", 4)) { reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); } else { /* Relying on default value. */ if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) @@ -726,7 +731,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->ulpi_ext_vbus_drv) reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); + + return 0; +} + +/** + * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core + * @dwc: Pointer to our controller context structure + * + * Returns 0 on success. The USB PHY interfaces are configured but not + * initialized. The PHY interfaces and the PHYs get initialized together with + * the core in dwc3_core_init. + */ +static int dwc3_phy_setup(struct dwc3 *dwc) +{ + int i; + int ret; + + for (i = 0; i < dwc->num_usb3_ports; i++) { + ret = dwc3_ss_phy_setup(dwc, i); + if (ret) + return ret; + } + + for (i = 0; i < dwc->num_usb2_ports; i++) { + ret = dwc3_hs_phy_setup(dwc, i); + if (ret) + return ret; + } return 0; } @@ -734,22 +767,36 @@ static int dwc3_phy_setup(struct dwc3 *dwc) static int dwc3_phy_init(struct dwc3 *dwc) { int ret; + int i, j; usb_phy_init(dwc->usb2_phy); usb_phy_init(dwc->usb3_phy); - ret = phy_init(dwc->usb2_generic_phy); - if (ret < 0) - goto err_shutdown_usb3_phy; + for (i = 0; i < dwc->num_usb2_ports; i++) { + ret = phy_init(dwc->usb2_generic_phy[i]); + if (ret < 0) { + /* clean up prior initialized HS PHYs */ + for (j = 0; j < i; j++) + phy_exit(dwc->usb2_generic_phy[j]); + goto err_shutdown_usb3_phy; + } + } - ret = phy_init(dwc->usb3_generic_phy); - if (ret < 0) - goto err_exit_usb2_phy; + for (i = 0; i < dwc->num_usb2_ports; i++) { + ret = phy_init(dwc->usb3_generic_phy[i]); + if (ret < 0) { + /* clean up prior initialized SS PHYs */ + for (j = 0; j < i; j++) + phy_exit(dwc->usb3_generic_phy[j]); + goto err_exit_usb2_phy; + } + } return 0; err_exit_usb2_phy: - phy_exit(dwc->usb2_generic_phy); + for (i = 0; i < dwc->num_usb2_ports; i++) + phy_exit(dwc->usb2_generic_phy[i]); err_shutdown_usb3_phy: usb_phy_shutdown(dwc->usb3_phy); usb_phy_shutdown(dwc->usb2_phy); @@ -759,8 +806,12 @@ static int dwc3_phy_init(struct dwc3 *dwc) static void dwc3_phy_exit(struct dwc3 *dwc) { - phy_exit(dwc->usb3_generic_phy); - phy_exit(dwc->usb2_generic_phy); + int i; + + for (i = 0; i < dwc->num_usb2_ports; i++) { + phy_exit(dwc->usb3_generic_phy[i]); + phy_exit(dwc->usb2_generic_phy[i]); + } usb_phy_shutdown(dwc->usb3_phy); usb_phy_shutdown(dwc->usb2_phy); @@ -769,22 +820,36 @@ static void dwc3_phy_exit(struct dwc3 *dwc) static int dwc3_phy_power_on(struct dwc3 *dwc) { int ret; + int i, j; usb_phy_set_suspend(dwc->usb2_phy, 0); usb_phy_set_suspend(dwc->usb3_phy, 0); - ret = phy_power_on(dwc->usb2_generic_phy); - if (ret < 0) - goto err_suspend_usb3_phy; + for (i = 0; i < dwc->num_usb2_ports; i++) { + ret = phy_power_on(dwc->usb2_generic_phy[i]); + if (ret < 0) { + /* Turn off prior ON'ed HS Phy's */ + for (j = 0; j < i; j++) + phy_power_off(dwc->usb2_generic_phy[j]); + goto err_suspend_usb3_phy; + } + } - ret = phy_power_on(dwc->usb3_generic_phy); - if (ret < 0) - goto err_power_off_usb2_phy; + for (i = 0; i < dwc->num_usb2_ports; i++) { + ret = phy_power_on(dwc->usb3_generic_phy[i]); + if (ret < 0) { + /* Turn of prior ON'ed SS Phy's */ + for (j = 0; j < i; j++) + phy_power_off(dwc->usb3_generic_phy[j]); + goto err_power_off_usb2_phy; + } + } return 0; err_power_off_usb2_phy: - phy_power_off(dwc->usb2_generic_phy); + for (i = 0; i < dwc->num_usb2_ports; i++) + phy_power_off(dwc->usb2_generic_phy[i]); err_suspend_usb3_phy: usb_phy_set_suspend(dwc->usb3_phy, 1); usb_phy_set_suspend(dwc->usb2_phy, 1); @@ -794,8 +859,12 @@ static int dwc3_phy_power_on(struct dwc3 *dwc) static void dwc3_phy_power_off(struct dwc3 *dwc) { - phy_power_off(dwc->usb3_generic_phy); - phy_power_off(dwc->usb2_generic_phy); + int i; + + for (i = 0; i < dwc->num_usb2_ports; i++) { + phy_power_off(dwc->usb3_generic_phy[i]); + phy_power_off(dwc->usb2_generic_phy[i]); + } usb_phy_set_suspend(dwc->usb3_phy, 1); usb_phy_set_suspend(dwc->usb2_phy, 1); @@ -1073,6 +1142,7 @@ static int dwc3_core_init(struct dwc3 *dwc) unsigned int hw_mode; u32 reg; int ret; + int i; hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); @@ -1116,15 +1186,19 @@ static int dwc3_core_init(struct dwc3 *dwc) if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { if (!dwc->dis_u3_susphy_quirk) { - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); - reg |= DWC3_GUSB3PIPECTL_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + for (i = 0; i < dwc->num_usb3_ports; i++) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i)); + reg |= DWC3_GUSB3PIPECTL_SUSPHY; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg); + } } if (!dwc->dis_u2_susphy_quirk) { - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg |= DWC3_GUSB2PHYCFG_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + for (i = 0; i < dwc->num_usb2_ports; i++) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); + reg |= DWC3_GUSB2PHYCFG_SUSPHY; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); + } } } @@ -1281,6 +1355,42 @@ static int dwc3_core_init(struct dwc3 *dwc) return ret; } +static int dwc3_get_multiport_phys(struct dwc3 *dwc) +{ + int ret; + struct device *dev = dwc->dev; + int i; + char phy_name[11]; + + /* + * Each port is at least HS capable. So loop over num_usb2_ports + * to get available phy's. + */ + for (i = 0; i < dwc->num_usb2_ports; i++) { + sprintf(phy_name, "usb2-port%d", i); + dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name); + if (IS_ERR(dwc->usb2_generic_phy[i])) { + ret = PTR_ERR(dwc->usb2_generic_phy[i]); + if (ret == -ENOSYS || ret == -ENODEV) + dwc->usb2_generic_phy[i] = NULL; + else + return dev_err_probe(dev, ret, "usb2 phy: %s not configured\n", phy_name); + } + + sprintf(phy_name, "usb3-port%d", i); + dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name); + if (IS_ERR(dwc->usb3_generic_phy[i])) { + ret = PTR_ERR(dwc->usb3_generic_phy[i]); + if (ret == -ENOSYS || ret == -ENODEV) + dwc->usb3_generic_phy[i] = NULL; + else + return dev_err_probe(dev, ret, "usb3 phy: %s not configured\n", phy_name); + } + } + + return 0; +} + static int dwc3_core_get_phy(struct dwc3 *dwc) { struct device *dev = dwc->dev; @@ -1311,20 +1421,23 @@ static int dwc3_core_get_phy(struct dwc3 *dwc) return dev_err_probe(dev, ret, "no usb3 phy configured\n"); } - dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); - if (IS_ERR(dwc->usb2_generic_phy)) { - ret = PTR_ERR(dwc->usb2_generic_phy); + if (dwc->num_usb2_ports > 1) + return dwc3_get_multiport_phys(dwc); + + dwc->usb2_generic_phy[0] = devm_phy_get(dev, "usb2-phy"); + if (IS_ERR(dwc->usb2_generic_phy[0])) { + ret = PTR_ERR(dwc->usb2_generic_phy[0]); if (ret == -ENOSYS || ret == -ENODEV) - dwc->usb2_generic_phy = NULL; + dwc->usb2_generic_phy[0] = NULL; else return dev_err_probe(dev, ret, "no usb2 phy configured\n"); } - dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); - if (IS_ERR(dwc->usb3_generic_phy)) { - ret = PTR_ERR(dwc->usb3_generic_phy); + dwc->usb3_generic_phy[0] = devm_phy_get(dev, "usb3-phy"); + if (IS_ERR(dwc->usb3_generic_phy[0])) { + ret = PTR_ERR(dwc->usb3_generic_phy[0]); if (ret == -ENOSYS || ret == -ENODEV) - dwc->usb3_generic_phy = NULL; + dwc->usb3_generic_phy[0] = NULL; else return dev_err_probe(dev, ret, "no usb3 phy configured\n"); } @@ -1336,6 +1449,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) { struct device *dev = dwc->dev; int ret; + int i; switch (dwc->dr_mode) { case USB_DR_MODE_PERIPHERAL: @@ -1343,8 +1457,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, false); - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); ret = dwc3_gadget_init(dwc); if (ret) @@ -1355,8 +1469,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, true); - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); + for (i = 0; i < dwc->num_usb2_ports; i++) { + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); + } ret = dwc3_host_init(dwc); if (ret) @@ -2046,6 +2162,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc) static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) { + int i; unsigned long flags; u32 reg; @@ -2066,17 +2183,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) /* Let controller to suspend HSPHY before PHY driver suspends */ if (dwc->dis_u2_susphy_quirk || dwc->dis_enblslpm_quirk) { - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | - DWC3_GUSB2PHYCFG_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + for (i = 0; i < dwc->num_usb2_ports; i++) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); + reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | + DWC3_GUSB2PHYCFG_SUSPHY; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); + } /* Give some time for USB2 PHY to suspend */ usleep_range(5000, 6000); } - phy_pm_runtime_put_sync(dwc->usb2_generic_phy); - phy_pm_runtime_put_sync(dwc->usb3_generic_phy); + for (i = 0; i < dwc->num_usb2_ports; i++) { + phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]); + phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]); + } break; case DWC3_GCTL_PRTCAP_OTG: /* do nothing during runtime_suspend */ @@ -2105,6 +2226,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) { unsigned long flags; int ret; + int i; u32 reg; switch (dwc->current_dr_role) { @@ -2125,17 +2247,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) break; } /* Restore GUSB2PHYCFG bits that were modified in suspend */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - if (dwc->dis_u2_susphy_quirk) - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; + for (i = 0; i < dwc->num_usb2_ports; i++) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); + if (dwc->dis_u2_susphy_quirk) + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; - if (dwc->dis_enblslpm_quirk) - reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + if (dwc->dis_enblslpm_quirk) + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); + } - phy_pm_runtime_get_sync(dwc->usb2_generic_phy); - phy_pm_runtime_get_sync(dwc->usb3_generic_phy); + for (i = 0; i < dwc->num_usb2_ports; i++) { + phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); + phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]); + } break; case DWC3_GCTL_PRTCAP_OTG: /* nothing to do on runtime_resume */ diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 21312703e053..0bba074b44e4 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -35,6 +35,9 @@ #define DWC3_MSG_MAX 500 +/* Number of ports supported by a multiport controller */ +#define MAX_PORTS_SUPPORTED 4 + /* Define XHCI Extcap register offsets for getting multiport info */ #define XHCI_HCC_PARAMS_OFFSET 0x10 #define DWC3_XHCI_HCSPARAMS1 0x04 @@ -1038,8 +1041,8 @@ struct dwc3_scratchpad_array { * @usb3_phy: pointer to USB3 PHY * @num_usb2_ports: number of usb2 ports. * @num_usb3_ports: number of usb3 ports. - * @usb2_generic_phy: pointer to USB2 PHY - * @usb3_generic_phy: pointer to USB3 PHY + * @usb2_generic_phy: pointer to array of USB2 PHY + * @usb3_generic_phy: pointer to array of USB3 PHY * @phys_ready: flag to indicate that PHYs are ready * @ulpi: pointer to ulpi interface * @ulpi_ready: flag to indicate that ULPI is initialized @@ -1177,9 +1180,8 @@ struct dwc3 { u32 num_usb2_ports; u32 num_usb3_ports; - - struct phy *usb2_generic_phy; - struct phy *usb3_generic_phy; + struct phy *usb2_generic_phy[MAX_PORTS_SUPPORTED]; + struct phy *usb3_generic_phy[MAX_PORTS_SUPPORTED]; bool phys_ready; diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index 039bf241769a..0377295717ab 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -328,6 +328,7 @@ static void dwc3_otg_device_exit(struct dwc3 *dwc) void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) { int ret; + int i; u32 reg; int id; unsigned long flags; @@ -386,9 +387,11 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) } else { if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, true); - if (dwc->usb2_generic_phy) - phy_set_mode(dwc->usb2_generic_phy, - PHY_MODE_USB_HOST); + for (i = 0; i < dwc->num_usb2_ports; i++) { + if (dwc->usb2_generic_phy[i]) + phy_set_mode(dwc->usb2_generic_phy[i], + PHY_MODE_USB_HOST); + } } break; case DWC3_OTG_ROLE_DEVICE: @@ -400,8 +403,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, false); - if (dwc->usb2_generic_phy) - phy_set_mode(dwc->usb2_generic_phy, + if (dwc->usb2_generic_phy[0]) + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); ret = dwc3_gadget_init(dwc); if (ret) From patchwork Mon May 1 14:34:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 89056 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2747694vqo; Mon, 1 May 2023 07:49:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6KKN7M4leI8GY/rMK91l/9Z2puaAhEcYohuGxg6cWI3tDYgct9X/DtxcZaSOcxM7ch4RPi X-Received: by 2002:a05:6a20:8e10:b0:f0:718f:8ee7 with SMTP id y16-20020a056a208e1000b000f0718f8ee7mr17613974pzj.53.1682952587232; Mon, 01 May 2023 07:49:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682952587; cv=none; d=google.com; s=arc-20160816; b=njLYQ1Uo8IqCD/+3S3xLHnTE3xToE2nbknZiuU78Ip07GpPf9T1KDDelzpi8eP8Mao etKCyxcbsd73/5ChSj7ZQB6tYwWC0elJSK/X0UZk2iJcLxHcrCDZPCi+gJ9LW4s+mG1G meip/BnNTYQROSLAKBsko3mNvp0geQijVjgOE8RTmcYF6Iz69CPl0wJpZLf/iNEA3soV e3IOx47gAZAj9AwH8Gm96vGVbDaEweH2zqC77jIlrxnP6SaQq+0h1eH8PuL4zZnHcREG kpyuzfbiQfSt1Y++8XKurpkIIKGQJF+V2IenfmQmWvYyYPy2WmDQVsTQ8Coxuu7BVFH6 Ny6Q== ARC-Message-Signature: i=1; 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Add support for configuring PWR_EVENT_IRQ's for all the ports during suspend/resume. Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/dwc3-qcom.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 959fc925ca7c..7a9bce66295d 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -37,7 +37,10 @@ #define PIPE3_PHYSTATUS_SW BIT(3) #define PIPE_UTMI_CLK_DIS BIT(8) -#define PWR_EVNT_IRQ_STAT_REG 0x58 +#define PWR_EVNT_IRQ1_STAT_REG 0x58 +#define PWR_EVNT_IRQ2_STAT_REG 0x1dc +#define PWR_EVNT_IRQ3_STAT_REG 0x228 +#define PWR_EVNT_IRQ4_STAT_REG 0x238 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) @@ -93,6 +96,13 @@ struct dwc3_qcom { struct icc_path *icc_path_apps; }; +static u32 pwr_evnt_irq_stat_reg_offset[4] = { + PWR_EVNT_IRQ1_STAT_REG, + PWR_EVNT_IRQ2_STAT_REG, + PWR_EVNT_IRQ3_STAT_REG, + PWR_EVNT_IRQ4_STAT_REG, +}; + static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -413,13 +423,16 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) { u32 val; int i, ret; + struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); if (qcom->is_suspended) return 0; - val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); - if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) - dev_err(qcom->dev, "HS-PHY not in L2\n"); + for (i = 0; i < dwc->num_usb2_ports; i++) { + val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]); + if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) + dev_err(qcom->dev, "HS-PHY%d not in L2\n", i); + } for (i = qcom->num_clocks - 1; i >= 0; i--) clk_disable_unprepare(qcom->clks[i]); @@ -446,6 +459,7 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) { int ret; int i; + struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); if (!qcom->is_suspended) return 0; @@ -467,8 +481,10 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); /* Clear existing events from PHY related to L2 in/out */ - dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, - PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); + for (i = 0; i < dwc->num_usb2_ports; i++) + dwc3_qcom_setbits(qcom->qscratch_base, + pwr_evnt_irq_stat_reg_offset[i], + PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); qcom->is_suspended = false; From patchwork Mon May 1 14:34:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 89053 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2742408vqo; Mon, 1 May 2023 07:40:29 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ55lz5Fzi4+f2Ks0uqkqQWsOAASlvxsHsAF8fot9CsqVj2Il7Z264L9CNBNJ7syVrKDUPp8 X-Received: by 2002:a17:90a:bb0f:b0:249:842d:312f with SMTP id u15-20020a17090abb0f00b00249842d312fmr14279805pjr.4.1682952029648; Mon, 01 May 2023 07:40:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682952029; cv=none; d=google.com; s=arc-20160816; b=V5eaJ84+EgIVEfawBTj+cMA2YtBhqRWqD3AUPvhPcr0qRtF3+7AFNGo8UGbiP8aiIs V/21Va9oElyCLlFzRqpf6plVNyBSpc2ZSJF3hfhZvr1OS7VJpZg/JR8x13P62qSOAV9o 68w+LE+BhPqsfKD5h8nYjU+pyffvIBy8KZFhLgqRUH81SB8tpxPyUYUJ2mo/zEuzub5q Qn85A9H9BUc0NI4DvV9x+7FrAyqihwsuhUrN/8l3rccR+/ByS55UIISpfi2WERxCNfUz v137rc4abVRuv4Zo3b8Kehgh5w1Arob49PKzTs1YbCYLHE2LmM8qnHDT0N1ehqJCPLmX 7NAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YaySEyQ398Lpa/HPI4dn7Um6ZX465c14s2T4qHTfE1w=; b=YYCv+WH9zefnPzLnMDvhIlz9HhGS1E4DlreB2s4weKAyRHBUGohvAlhjFi0gKxaxYS KOzYQuUNEEoYjFAn9LBmKd37BD0F0gPPX9yHcd7ryHlibe6kB8wf0CaM9pfSFYkZCdKC HqqlPk1Mr6AOtjeRVLBFsx3J2fYOd1gYZkZj6IkfpQFck6+FNLd5S1QeFD61pVgb0dsd NCBKWCvMWXAW3rNtkCxFAUmwR6gK8f7FT88b9XwcDh3l+GEUyupUl3X2zOdwxJc8zOac een/8UjM+mWH9EAI/UvMAHiwYSBXLStewdoVFBnqhgiLLXhlL4yoX+HCDdyXDE5xNXKr b+dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=JSYKLwlt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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This will be used as a base for SA8295P and SA8295-Ride platforms. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 64 ++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 8fa9fbfe5d00..0e4fb286956b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3133,6 +3133,70 @@ usb_1_role_switch: endpoint { }; }; + usb_2: usb@a4f8800 { + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, + <&pdc 126 IRQ_TYPE_EDGE_RISING>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + , + , + , + ; + + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq", + "ss_phy_irq", "pwr_event_1", + "pwr_event_2", "pwr_event_3", + "pwr_event_4"; + + power-domains = <&gcc USB30_MP_GDSC>; + + resets = <&gcc GCC_USB30_MP_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + required-opps = <&rpmhpd_opp_nom>; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x800 0x0>; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, + <&usb_2_hsphy2>, + <&usb_2_hsphy3>; + phy-names = "usb2-port0", "usb3-port0", + "usb2-port1", "usb3-port1", + "usb2-port2", + "usb2-port3"; + }; + }; + mdss0: display-subsystem@ae00000 { compatible = "qcom,sc8280xp-mdss"; reg = <0 0x0ae00000 0 0x1000>; From patchwork Mon May 1 14:34:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 89061 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2749366vqo; Mon, 1 May 2023 07:52:50 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5JQJmHXoLuw/mMZLFP2WsGwORohQWuzsJV1cjiI5Uk/VrbFqqodUxAet29ME4gGSBLwHy5 X-Received: by 2002:a05:6a20:144d:b0:f6:2287:e05d with SMTP id a13-20020a056a20144d00b000f62287e05dmr18610852pzi.10.1682952770380; Mon, 01 May 2023 07:52:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682952770; cv=none; d=google.com; s=arc-20160816; b=ALhGUZ9AuEO9guyMOoSXTDln1gIKSjqsuLNW8PfhUMCp6oaIoSLLV4wkCUiar+zfbM ezQtW4ZNfkjINoDQpcMmkfZCCc956loWYp7Q7DRMnok4tt0THHtgB5PGD10xMZz2JzR/ jaO0t+NMZc7JeX44TSB8YUOiVxVfAS2tTpThcKo7ZXBVWj0Yh8x4Nk3zx9A5WdCej0IZ XTCtrCWtLga9i7d7zZNJYD2INTT1kMCYlef1ygUEg8oh5215aaiUmbVHo44T+aI7SH8J emYDvI0pzox1+yKotjSCBoWRCHe6Z4kkWp7iQjQbwR0jRfKPV1vpzlMVaEAuQiJq3XIh plPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SO2o2n33V/6ML1mXMcntAULEnoh70sDCEByz8TtJoro=; b=f8ZooT+6v/f/ERHnca4RYeE+IRitYgg/0XPkvrmr789mkxk0WhtimM451kyIIn0Q35 5gT1OFGGcL/9R0YaO7SPysmLiPvEXOYOOsyCNPiu/KBwXB/bsACFQoukFsMUkwQfL+i2 l6mvPJCIiEbLP4IKa0d9vfobJKYxDppGd5lcg5y1d/HQQmqItFP4btMMpFU4Qj67rOsE 1MRdEnQhvxbA8rKqQYxhAw6fl6PFrqZeNtalQa+wHEio2f17gUMBAJtoOGONP7lJXpQy TrEkGp3If6QqilgBZJb0KIIcyhkDiQEuzcdz91rX/8/lvrYfpF5j4DT7b3O93GQ2f/22 QxBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=f355EohV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Add pinctrl support for usb ports to provide VBUS to connected peripherals. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index fd253942e5e5..7e6061c43835 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -584,6 +584,19 @@ &usb_1_qmpphy { status = "okay"; }; +&usb_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_en_state>, + <&usb3_en_state>, + <&usb4_en_state>, + <&usb5_en_state>; + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + &usb_2_hsphy0 { vdda-pll-supply = <&vreg_l5a>; vdda18-supply = <&vreg_l7g>; @@ -729,3 +742,37 @@ wake-n-pins { }; }; }; + +&pmm8540c_gpios { + usb2_en_state: usb2-en-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; + +&pmm8540e_gpios { + usb3_en_state: usb3-en-state { + pins = "gpio5"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; + +&pmm8540g_gpios { + usb4_en_state: usb4-en-state { + pins = "gpio5"; + function = "normal"; + output-high; + power-source = <0>; + }; + + usb5_en_state: usb5-en-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; From patchwork Mon May 1 14:34:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 89059 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2748634vqo; Mon, 1 May 2023 07:51:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5VoOwEP5LHKjQ5m1txdjxGf2wcUCu1UMc/8vSj8M0Bvj9FqXKYHff/bIrIktHIYPxKDQEF X-Received: by 2002:a05:6a20:1455:b0:ee:d266:32b9 with SMTP id a21-20020a056a20145500b000eed26632b9mr18788626pzi.10.1682952684403; Mon, 01 May 2023 07:51:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682952684; cv=none; d=google.com; s=arc-20160816; b=UvtWTATv4khKEVpDbYpYF9KLbj9vJNezjti56n6zXsB0x88186CIVII7gAdqp2ef+j b4kRfSPUR9AZvEBZfro3C9wC9DN8L3/E50B22TtZ80DBUiae3O3pqdzQwYZjwqT3SLXZ qrX+Rw+Q4iOD6RhC3aFx4sTfnQ/egWwmeKts/z816oQeS5o1waV/KpqbTXlug8a5etMt Wa3yNgRS0EtbRsNizYEUObeIt9BVD2ziuBJKOemmy+/uF94Gu/tPqhSKjQavovZc1QH9 WoarIKnzzoYaWVck4srRkhdNkEonhkMbkwnJTKHt9onCIpws336K5VsoQZKe3teaS5yU NgwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Abuns1dscIhsXqDWAq+7t0Pta40GkCpQ9StWLfQ64cg=; b=VCqBqUrppv82v9CLfNieswUwVcB8kZdRzcoL3zgI6ruKf/GdL795f++wiHOrYueLqm se2o1PPDWKhmXn+N99rhrP98x2PZxI5ldDtDktZDebnKoClRv2KlMC53azMbH0XthgfW jEKwk/g8suYwCtUipcORycX755iUl+Y70OoLUA3Zg1LnJHzL4GnR4fcm1NA9Dzf2SeQ7 K9qI4G5ziBfjB8jDukK+SRF5leZXMN6dIZXi/Jhszm9JyoYybtwMkA/6f+S6i9cobC7C Aof3WF9kJ0VR0h8L3dpeGmbqkHsjcB3QaZVUnR+VC5XSjs4jlK8wQ3zbWPqi2G6pVgQJ NCBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=R6ZVOIVG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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The board only has a single port hooked up (despite it being wired up to the multiport IP on the SoC). There's also a USB 2.0 mux hooked up, which by default on boot is selected to mux properly. Grab the gpio controlling that and ensure it stays in the right position so USB 2.0 continues to be routed from the external port to the SoC. Signed-off-by: Andrew Halaney Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 24fa449d48a6..53d47593306e 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -309,6 +309,19 @@ &usb_2_qmpphy0 { status = "okay"; }; +&usb_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_en_state>; + + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; + phy-names = "usb2-port0", "usb3-port0"; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>; +}; + &xo_board_clk { clock-frequency = <38400000>; }; @@ -401,4 +414,13 @@ wake-pins { bias-pull-up; }; }; + + usb2_en_state: usb2-en-state { + /* TS3USB221A USB2.0 mux select */ + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; };