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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:14 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 01/11] riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extu Date: Fri, 28 Apr 2023 08:12:02 +0200 Message-Id: <20230428061210.2988035-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399434188701251?= X-GMAIL-MSGID: =?utf-8?q?1764399434188701251?= From: Christoph Müllner The current support of the bitfield-extraction instructions th.ext and th.extu (XTheadBb extension) only covers sign_extract and zero_extract. This patch add support for sign_extend and zero_extend to avoid any shifts for sign or zero extensions. gcc/ChangeLog: * config/riscv/riscv.md: No base-ISA extension splitter for XThead*. * config/riscv/thead.md (*extend2_th_ext): New XThead extension INSN. (*zero_extendsidi2_th_extu): New XThead extension INSN. (*zero_extendhi2_th_extu): New XThead extension INSN. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadbb-ext-1.c: New test. * gcc.target/riscv/xtheadbb-extu-1.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 6 +- gcc/config/riscv/thead.md | 31 +++++++++ .../gcc.target/riscv/xtheadbb-ext-1.c | 67 +++++++++++++++++++ .../gcc.target/riscv/xtheadbb-extu-1.c | 67 +++++++++++++++++++ 4 files changed, 168 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1fb29da8a0b..f4cc99187ed 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1368,7 +1368,7 @@ (define_insn_and_split "*zero_extendsidi2_internal" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] - "TARGET_64BIT && !TARGET_ZBA + "TARGET_64BIT && !TARGET_ZBA && !TARGET_XTHEADBB && !(register_operand (operands[1], SImode) && reg_or_subregno (operands[1]) == VL_REGNUM)" "@ @@ -1395,7 +1395,7 @@ (define_insn_and_split "*zero_extendhi2" [(set (match_operand:GPR 0 "register_operand" "=r,r") (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" " r,m")))] - "!TARGET_ZBB" + "!TARGET_ZBB && !TARGET_XTHEADBB" "@ # lhu\t%0,%1" @@ -1451,7 +1451,7 @@ (define_insn_and_split "*extend2" [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") (sign_extend:SUPERQI (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))] - "!TARGET_ZBB" + "!TARGET_ZBB && !TARGET_XTHEADBB" "@ # l\t%0,%1" diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 0623607d3dc..6a06d0dfcf2 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -59,6 +59,17 @@ (define_insn "*th_ext4" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) +(define_insn "*extend2_th_ext" + [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") + (sign_extend:SUPERQI + (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))] + "TARGET_XTHEADBB" + "@ + th.ext\t%0,%1,15,0 + l\t%0,%1" + [(set_attr "type" "bitmanip,load") + (set_attr "mode" "")]) + (define_insn "*th_extu4" [(set (match_operand:GPR 0 "register_operand" "=r") (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r") @@ -72,6 +83,26 @@ (define_insn "*th_extu4" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) +(define_insn "*zero_extendsidi2_th_extu" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))] + "TARGET_64BIT && TARGET_XTHEADBB" + "@ + th.extu\t%0,%1,31,0 + lwu\t%0,%1" + [(set_attr "type" "bitmanip,load") + (set_attr "mode" "SI")]) + +(define_insn "*zero_extendhi2_th_extu" + [(set (match_operand:GPR 0 "register_operand" "=r,r") + (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + "TARGET_XTHEADBB" + "@ + th.extu\t%0,%1,15,0 + lhu\t%0,%1" + [(set_attr "type" "bitmanip,load") + (set_attr "mode" "HI")]) + (define_insn "*th_clz2" [(set (match_operand:X 0 "register_operand" "=r") (clz:X (match_operand:X 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c new file mode 100644 index 00000000000..02f6ec1417d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext-1.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +long sext64_32(int s32) +{ + return s32; +} + +long sext64_16(short s16) +{ + return s16; +} + +long sext64_8(char s8) +{ + return s8; +} + +int sext32_64(long s64) +{ + return s64; +} + +int sext32_16(short s16) +{ + return s16; +} + +int sext32_8(char s8) +{ + return s8; +} + +short sext16_64(long s64) +{ + return s64; +} + +short sext16_32(int s32) +{ + return s32; +} + +short sext16_8(char s8) +{ + return s8; +} + +char sext8_64(long s64) +{ + return s64; +} + +char sext8_32(int s32) +{ + return s32; +} + +char sext8_16(short s16) +{ + return s16; +} + +/* { dg-final { scan-assembler-not "slli" } } */ +/* { dg-final { scan-assembler-not "srli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c new file mode 100644 index 00000000000..01e3eda7df2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-1.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadbb" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +unsigned long zext64_32(unsigned int u32) +{ + return u32; //th.extu a0, a0, 31, 0 +} + +unsigned long zext64_16(unsigned short u16) +{ + return u16; +} + +unsigned long zext64_8(unsigned char u8) +{ + return u8; +} + +unsigned int zext32_64(unsigned long u64) +{ + return u64; +} + +unsigned int zext32_16(unsigned short u16) +{ + return u16; +} + +unsigned int zext32_8(unsigned char u8) +{ + return u8; +} + +unsigned short zext16_64(unsigned long u64) +{ + return u64; +} + +unsigned short zext16_32(unsigned int u32) +{ + return u32; +} + +unsigned short zext16_8(unsigned char u8) +{ + return u8; +} + +unsigned char zext8_64(unsigned long u64) +{ + return u64; +} + +unsigned char zext8_32(unsigned int u32) +{ + return u32; +} + +unsigned char zext8_16(unsigned short u16) +{ + return u16; +} + +/* { dg-final { scan-assembler-not "slli" } } */ +/* { dg-final { scan-assembler-not "srli" } } */ From patchwork Fri Apr 28 06:12:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 88453 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp728828vqo; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:16 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 02/11] riscv: xtheadmempair: Fix CFA reg notes Date: Fri, 28 Apr 2023 08:12:03 +0200 Message-Id: <20230428061210.2988035-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399572779924391?= X-GMAIL-MSGID: =?utf-8?q?1764399572779924391?= From: Christoph Müllner The current implementation triggers an assertion in dwarf2out_frame_debug_cfa_offset() under certain circumstances. The standard code uses REG_FRAME_RELATED_EXPR notes instead of REG_CFA_OFFSET notes when saving registers on the stack. So let's do this as well. gcc/ChangeLog: * config/riscv/thead.cc (th_mempair_save_regs): Emit REG_FRAME_RELATED_EXPR notes in prologue. Signed-off-by: Christoph Müllner --- gcc/config/riscv/thead.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index 75203805310..d7e3cf80d9b 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -368,8 +368,12 @@ th_mempair_save_regs (rtx operands[4]) rtx set2 = gen_rtx_SET (operands[2], operands[3]); rtx insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2))); RTX_FRAME_RELATED_P (insn) = 1; - add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set1)); - add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set2)); + + REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, + copy_rtx (set1), REG_NOTES (insn)); + + REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, + copy_rtx (set2), REG_NOTES (insn)); } /* Similar like riscv_restore_reg, but restores two registers from memory From patchwork Fri Apr 28 06:12:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 88457 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp729583vqo; Thu, 27 Apr 2023 23:17:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5zWIEAEiSEEp5sM2/xEquUWkWURgt+N0LX7IXrbvUAbFkih06UTq2/s+Z3GZozAw9vpa6x X-Received: by 2002:a17:907:6e8b:b0:94e:fdec:67e2 with SMTP id sh11-20020a1709076e8b00b0094efdec67e2mr4498983ejc.77.1682662667101; Thu, 27 Apr 2023 23:17:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682662667; cv=none; d=google.com; s=arc-20160816; b=vvvVwOmBTWVGEweZuYzk6TIAlMbETz0srolkgzQccDMvlvMDrD/VP3L8OPKzt3IG/G Q5IIziX9t4lIAIjfVKprhZ2Rv5iXNFl7Zv8T6y8n9rAOf/wXuBMSaw5GbsXFLSUXy4Mm vDexfKGmAuIfYFObawvvTr/ZnxQhwZikdKHJJq9k10bwHTQbRV7WOhojchuogJII6ql0 KM6A8qvOCUOSQHhnxfKGDdk50XI7dOL9Tw7/BLaz8msJUGSO/pnHEjfSZ0Q2lt5BiWDs 1n6NNKYC3E/hEaQyrwZxSzR9dkM594HhIS8+c3RLzbkScACC1on5ycbGrGfTFIZGYumg cvqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=FTcnJZCTufnx7sYJGxPOWl+mtzwkWCV5eaTR9Z8/Hrk=; b=zPQonEZlfFw6ce5Ku03mLaMfIr3Qsyn7RKgtLBtdXpMZNuNDhbVPxrSKsfqkOZOpmY Og0MZVTVuoRCf0Pc+/JwedQ4TttGcqmLrFFQ7p23IDkWQSLCrHH1EkCkDw1+gzwURDv4 1DjTDbqG/UDGXeYaMtJLuE5Asc6TMa1XeTG+OdVTioBROltq+NsMarSfaVj2CjNk4Sgh 2+gevT1bX3PM5H+I0aee99V4xhtO1D5/H+8KLDsqtlmB91jPqJV03sMZVTt0xbMFQF79 vLFkFLF/IkP5XjCZ7BFT9FzwRWFGX13FOf2UNaV5Dwhwy4RHEShxONpbPWKZ73bz24C+ MmZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=YTRyOWbu; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:17 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 03/11] riscv: xtheadmempair: Fix doc for th_mempair_order_operands() Date: Fri, 28 Apr 2023 08:12:04 +0200 Message-Id: <20230428061210.2988035-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399688973959759?= X-GMAIL-MSGID: =?utf-8?q?1764399688973959759?= From: Christoph Müllner There is an incorrect sentence in the documentation of the function th_mempair_order_operands(). Let's remove it. gcc/ChangeLog: * config/riscv/thead.cc (th_mempair_operands_p): Fix documentation of th_mempair_order_operands(). Signed-off-by: Christoph Müllner --- gcc/config/riscv/thead.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index d7e3cf80d9b..507c912bc39 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -336,8 +336,8 @@ th_mempair_operands_p (rtx operands[4], bool load_p, } /* Given OPERANDS of consecutive load/store that can be merged, - swap them if they are not in ascending order. - Return true if swap was performed. */ + swap them if they are not in ascending order. */ + void th_mempair_order_operands (rtx operands[4], bool load_p, machine_mode mode) { From patchwork Fri Apr 28 06:12:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 88450 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp728069vqo; Thu, 27 Apr 2023 23:14:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ57O2rFSbKojFRnPKjPKaemkil6TifAUMdbMeM0hslq+wtxqPZMNPylxMxqjox1aCjGP3Hh X-Received: by 2002:a17:907:988:b0:94e:dc3c:cca2 with SMTP id bf8-20020a170907098800b0094edc3ccca2mr3702793ejc.70.1682662456827; Thu, 27 Apr 2023 23:14:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682662456; cv=none; d=google.com; s=arc-20160816; b=HtiSe9wvRGgiZkKVNEjsRWWa5u7bWQOL4ZCEVCk4UfbSsi/sVtzVeki+QwQRp5VGOv N2zI2PAAzq6k7DdFgao0z4pHOdle6rUMxCKjzX/cV+J3a50lft6dYWZpoPuV0XHaVQf0 X1zyoZnpHkRS2jPeMLE9XbFpbAeySOp6tYQf3CT2TxNvy/jNSf4iacl5TSUQp3pJsQqQ bCFyW2blxI8wGKpUHv9LaIJBCwmphKiv7a3p4geVWGkxUVccvZ7j+uQvdp2q8v3sXw7o xIXEBOUm2fSdVhmSY5/Ewx80Rzq2IyOHD+NwMowMiSSE2QHzsKvvq8kWJiZOQNe340N1 /7lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=0YQDf5xO5GsN4/iFlGZybwBeaMoRy8QmNAy3edT0ms0=; b=bFugqTx9/0zqsVaucnjgHIQY77EkI0Z3M9sKjdLz0TlMVnBK1mlNI8LqhVvO8RAuHW EaFH4qW1zTn/aET9VfXEV/hb9fjG41SHiWkFFqK8r99Nxgvr9ADFCwi5A3CMQpu6XMAi I5f6pmg2Dd1eImgt+bYRfu7hSvz6ZhqEJbfbS83lbbB1BWIft8gpqxH417QDiEIvvxMx 6+rcfGNNLYIbhgVT2hbzv/1nZrIeQ5XVtBR5PWJl8KUlpsSRTMUpHewt0rzhPYDxuGwc x+jml/QAbG73LW6t18wJrpkmh6zqywJA4uQ8Em87o16z3BNpf+P/sAqHMYDE7cW0Qpb3 jpiw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=nvLfIPla; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:19 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 04/11] riscv: thead: Adjust constraints of th_addsl INSN Date: Fri, 28 Apr 2023 08:12:05 +0200 Message-Id: <20230428061210.2988035-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399467969143250?= X-GMAIL-MSGID: =?utf-8?q?1764399467969143250?= From: Christoph Müllner A recent change adjusted the constraints of ZBA's shNadd INSN. Let's mirror this change here as well. gcc/ChangeLog: * config/riscv/thead.md: Adjust constraints of th_addsl. Signed-off-by: Christoph Müllner --- gcc/config/riscv/thead.md | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 6a06d0dfcf2..aa933960a98 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -22,10 +22,9 @@ (define_insn "*th_addsl4" [(set (match_operand:X 0 "register_operand" "=r") (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") - (match_operand 2 "const_int_operand" "n")) + (match_operand:QI 2 "imm123_operand" "Ds3")) (match_operand:X 3 "register_operand" "r")))] - "TARGET_XTHEADBA - && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)" + "TARGET_XTHEADBA" "th.addsl\t%0,%3,%1,%2" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) From patchwork Fri Apr 28 06:12:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 88452 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp728140vqo; Thu, 27 Apr 2023 23:14:26 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7o2is3dSeDs7pzq6qwW8H9wix5TmBK8hdt07Kb3NFnnVwSVIvdQLetRF5EHDhTbU1do+36 X-Received: by 2002:a17:907:2da9:b0:955:34a5:ae49 with SMTP id gt41-20020a1709072da900b0095534a5ae49mr4347477ejc.54.1682662466159; Thu, 27 Apr 2023 23:14:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682662466; cv=none; d=google.com; s=arc-20160816; b=ecrtAeYpZBzrJcGalKe9WnB8KuBT0PMZAf/4VYe6EIrwSauIBEr0z/gzciUh788kr8 GZVihO7PoW/NXvqqIdhjHMq3ezZWbDeQb+arL/sX4+Y0I+iO/v9H/89G0O9cij59wTTE qZo6nVBa0FHqCb2RywcjjIxu/9+XRVXal8Zti9Vwxf/gaJq3hI7Xi+qaFwITW0F2H19c mbD+RMkpkWLNfeHO/BeT25YDDqBXKR88PrhJvHjeK5pCIxKb3h1liOCbB1KKK6c+/8op LdAj3H6fh4iYRZwwHsGDZmWqpVEIjHqbDcUMKioeNSZLJOouEy2lzr47+2DtjKrMqDVu F7/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=k1tgD8PDTTGDPcgtLgrufG3OW/9CO5A0P+acFEGVB9A=; b=0tfiOsjVyJGg5ZAdl5wUvkyGB0VxpzFjLX7WD14lLTKkbZLkwM5RWwt82MHrxJFbU0 CIm5lncXqxEN2Dea63roK7Vd4KPlhqz7t/o+K25SC2gKnoCKXHUFozfs6nFTGZ+jIx4g wfhXhFFeA98M2U+7aF6A8FEmOVNhayilcybYYbUBNss/3oAjJ9rW1nBVf7YY/YsKyskZ +/Le9VKpb0AigGk6QvdphnijQeiAZeX9Fi+3kvc8kC50SbenP4gMZlzNGd1tkYaIXELX 0ijYZ37a6D4hxtRgoInh0enSzWtNVyA63RDWLXg1/klPSgRAxRv+V/pd75iHCs9st4kZ 4MIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=H3fEWDqp; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:20 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 05/11] riscv: Simplify output of MEM addresses Date: Fri, 28 Apr 2023 08:12:06 +0200 Message-Id: <20230428061210.2988035-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399478402277379?= X-GMAIL-MSGID: =?utf-8?q?1764399478402277379?= From: Christoph Müllner We have the following situation for MEM RTX objects: * TARGET_PRINT_OPERAND expands to riscv_print_operand() * This falls into the default case (unknown or on letter) of the outer switch-case-block and the MEM case of the inner switch-case-block and calls output_address() in final.cc with XEXP (op, 0) (the address) * This calls targetm.asm_out.print_operand_address() which is riscv_print_operand_address() * riscv_print_operand_address() is targeting the address of a MEM RTX * riscv_print_operand_address() calls riscv_print_operand() for the offset and directly prints the register if the address is classified as ADDRESS_REG * This falls into the default case (unknown or on letter) of the outer switch-case-block and the default case of the inner switch-case-block and calls output_addr_const(). However, since we know that offset must be a CONST_INT (which will be followed by a '()' string), there is no need to call riscv_print_operand() for the offset. Instead we can take the shortcut and use output_addr_const(). This change also brings the code in riscv_print_operand_address() in line with the other cases, where output_addr_const() is used to print offsets. Tested with GCC regression test suite and SPEC intrate. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5d2550871c7..92043236b17 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4581,7 +4581,7 @@ riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx switch (addr.type) { case ADDRESS_REG: - riscv_print_operand (file, addr.offset, 0); + output_addr_const (file, riscv_strip_unspec_address (addr.offset)); fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); return; From patchwork Fri Apr 28 06:12:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 88455 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp729026vqo; Thu, 27 Apr 2023 23:16:28 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4ZDR/0Sb4oxqjc9nz4OJiCmzbxepX3iM3ZxJR6Jr/Tk33ndVMyy7/HUCPt3PmbwP9RO8Bg X-Received: by 2002:a17:907:1b09:b0:948:fe00:77f2 with SMTP id mp9-20020a1709071b0900b00948fe0077f2mr3987765ejc.58.1682662588099; Thu, 27 Apr 2023 23:16:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682662588; cv=none; d=google.com; s=arc-20160816; b=u1/yYXhNqetEOfT0Lgm37EYvay76gyKE76p24tf2NwXYhtNaijPlDe/UIE2XlV5bip QiEw3/EQEr9dTnTvbeD4Gkf5u45d8GIfhzDwpb3awYcjOPnrfm8/C613390LvIHG8NDp /FZPajFQL2SWPHTyQpj4AZeYeb+Bgs+wEsREl6BkAGn+3TcYizhxPOllUHJCfRwODHLx kxvx2dMVPtTYNb2bKzXQG+PzBNgAwnq+Ykb36sCoT/j9SepvuXq3++xnQhqIoYMcSrMn CHbsMXjqwFwbQ3a+PVDpM7Xgfm432t78pEtI3HB1QrxXPlSta+tkP87c8DWOC1u2tgZ4 vJHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=vc/rsq/Wz3BvmMBob0cP9kMS0136vC3kGuubXfDPkaY=; b=K0LmnSopAla6D2nYtCEy/4aP7lB99IyHnaUzK2hVaDfDZq9Wsa478BEJ+2W+pV9GVk s9ZT9dY6KJwCIOvUU4VuI3/OvmI9PmM7DtkhXPBDblbFvpDKdQwOzhydwoFCTLHciscO yALpYgOWQLrumZVYhZtDZ0sOt+yNZTPi8z5FSAIQPRD9oHovB7dLFvdk4YoqGeMzQ+Ta INkyPEOUhrtp0mVfN9VhZcujT36dqCfSdVEFV7F6NvhbMtx+idrgPznhD8t4lzf9W8gm AITkduwJn84RSDqHkeeRvEF9gCIYDLrKGcN6V6TY7InS9bFUFbOYlDF4Dh3ohFdlh7Jg e7Xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=E5hQTkKD; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:21 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 06/11] riscv: Define Xmode macro Date: Fri, 28 Apr 2023 08:12:07 +0200 Message-Id: <20230428061210.2988035-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399605877547394?= X-GMAIL-MSGID: =?utf-8?q?1764399605877547394?= From: Christoph Müllner Define a Xmode macro that specifies the registers size (XLEN) similar to Pmode. This allows the backend code to write generic RV32/RV64 C code (under certain circumstances). gcc/ChangeLog: * config/riscv/riscv.h (Xmode): New macro. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 66fb07d6652..90746fe14e3 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -791,6 +791,10 @@ typedef struct { #define Pmode word_mode +/* Specify the machine mode that registers have. */ + +#define Xmode (TARGET_64BIT ? DImode : SImode) + /* Give call MEMs SImode since it is the "most permissive" mode for both 32-bit and 64-bit targets. */ From patchwork Fri Apr 28 06:12:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 88454 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp728966vqo; Thu, 27 Apr 2023 23:16:16 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ49OzfwQ5qKcxfOJHwbe5v+Z9qq2KIjuW7Od1+7jHdIDVauRJ4jzCk3hJWU2gxTVmbqR8kT X-Received: by 2002:a17:906:c153:b0:957:800:912f with SMTP id dp19-20020a170906c15300b009570800912fmr3967402ejc.71.1682662576679; Thu, 27 Apr 2023 23:16:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682662576; cv=none; d=google.com; s=arc-20160816; b=x0HaqUGn+TtefJlEOpJKmjcwCfyQYhqlpw5ZM9oEa7wikL8sUvycmVBchtoi9hbXRV Jq9+9y0ueEPXRwJLhoSbKUYvc6EW9MY0Xi5Jo/S0zTn928ijnvFzakeZWm0lfwLd6iTq GjVi66TkcltVCWwT8LsC75bqgsVrukaHE2/ZDbthp36i/JyC7BvMi5Czntbb/nk2PbYR pfyMOn1hFsOXy/BeQXe2TabghmC6fuWvocnNV13GZNv2GwiwTj/DeOMHlZGdo4SmszJk Lnb+/Fh2tTAxTcQ6ASz2mWbKlvabN0qYiI1tYRnZxrI1d6fjsvEgiTN2vV517d5Lvs6k Fuyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=z+H6VC4UCtSwD/YYDi1wqQehV4k/KvJMoU6j35Tb8Yw=; b=kojrQcspmBTZMmlmbv8HhFmp+W7bKXYJqX7tOzmCYgUg+8JwrcS9Az0FIMBvNRgIl0 Xb4ugwZR2IYEifZizigjIRrq600D5VJi7NooPJhKsupWrkR5gsniSqwSIG6ID2EpzPXp 5Dj6vYGeK2lZAJCvgNDFWduaASdrHAm7VFm622hB5oZx8bEdn/hgfLAoc9bz7D6TcRGR uxOx19lu+iVD8y41bpZ3B6zuO/WJF01UYUnkg84X/H+2s1aL4asVSQ+YrVh6xl7ajL+L dOeIAjT81rzd3SOIn1YaQmghSvw8oI6ViWbVb27G/xsPKLCRCnI0DqrV6/jMvWBc0YR8 MFvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=jjzjsE4U; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:23 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 07/11] riscv: Move address classification info types to riscv-protos.h Date: Fri, 28 Apr 2023 08:12:08 +0200 Message-Id: <20230428061210.2988035-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399594115717840?= X-GMAIL-MSGID: =?utf-8?q?1764399594115717840?= From: Christoph Müllner enum riscv_address_type and struct riscv_address_info are used to store address classification information. Let's move this types into our common header file in order to share them with other compilation units. This is a non-functional change without any intendet side-effects. gcc/ChangeLog: * config/riscv/riscv-protos.h (enum riscv_address_type): New location of type definition. (struct riscv_address_info): Likewise. * config/riscv/riscv.cc (enum riscv_address_type): Old location of type definition. (struct riscv_address_info): Likewise. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-protos.h | 43 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 43 --------------------------------- 2 files changed, 43 insertions(+), 43 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5244e8dcbf0..628c64cf628 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -35,6 +35,49 @@ enum riscv_symbol_type { }; #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1) +/* Classifies an address. + + ADDRESS_REG + A natural register + offset address. The register satisfies + riscv_valid_base_register_p and the offset is a const_arith_operand. + + ADDRESS_LO_SUM + A LO_SUM rtx. The first operand is a valid base register and + the second operand is a symbolic address. + + ADDRESS_CONST_INT + A signed 16-bit constant address. + + ADDRESS_SYMBOLIC: + A constant symbolic address. */ +enum riscv_address_type { + ADDRESS_REG, + ADDRESS_LO_SUM, + ADDRESS_CONST_INT, + ADDRESS_SYMBOLIC +}; + +/* Information about an address described by riscv_address_type. + + ADDRESS_CONST_INT + No fields are used. + + ADDRESS_REG + REG is the base register and OFFSET is the constant offset. + + ADDRESS_LO_SUM + REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE + is the type of symbol it references. + + ADDRESS_SYMBOLIC + SYMBOL_TYPE is the type of symbol that the address references. */ +struct riscv_address_info { + enum riscv_address_type type; + rtx reg; + rtx offset; + enum riscv_symbol_type symbol_type; +}; + /* Routines implemented in riscv.cc. */ extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 92043236b17..8388235d8cc 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -81,28 +81,6 @@ along with GCC; see the file COPYING3. If not see /* True if bit BIT is set in VALUE. */ #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0) -/* Classifies an address. - - ADDRESS_REG - A natural register + offset address. The register satisfies - riscv_valid_base_register_p and the offset is a const_arith_operand. - - ADDRESS_LO_SUM - A LO_SUM rtx. The first operand is a valid base register and - the second operand is a symbolic address. - - ADDRESS_CONST_INT - A signed 16-bit constant address. - - ADDRESS_SYMBOLIC: - A constant symbolic address. */ -enum riscv_address_type { - ADDRESS_REG, - ADDRESS_LO_SUM, - ADDRESS_CONST_INT, - ADDRESS_SYMBOLIC -}; - /* Information about a function's frame layout. */ struct GTY(()) riscv_frame_info { /* The size of the frame in bytes. */ @@ -182,27 +160,6 @@ struct riscv_arg_info { unsigned int fpr_offset; }; -/* Information about an address described by riscv_address_type. - - ADDRESS_CONST_INT - No fields are used. - - ADDRESS_REG - REG is the base register and OFFSET is the constant offset. - - ADDRESS_LO_SUM - REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE - is the type of symbol it references. - - ADDRESS_SYMBOLIC - SYMBOL_TYPE is the type of symbol that the address references. */ -struct riscv_address_info { - enum riscv_address_type type; - rtx reg; - rtx offset; - enum riscv_symbol_type symbol_type; -}; - /* One stage in a constant building sequence. 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:24 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 08/11] riscv: Prepare backend for index registers Date: Fri, 28 Apr 2023 08:12:09 +0200 Message-Id: <20230428061210.2988035-9-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399709510502824?= X-GMAIL-MSGID: =?utf-8?q?1764399709510502824?= From: Christoph Müllner RISC-V does currently not support index registers. However, there are some vendor extensions that specify them. Let's do the necessary changes in the backend so that we can add support for such a vendor extension in the future. This is a non-functional change without any intended side-effects. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_regno_ok_for_index_p): New prototype. (riscv_index_reg_class): Likewise. * config/riscv/riscv.cc (riscv_regno_ok_for_index_p): New function. (riscv_index_reg_class): New function. * config/riscv/riscv.h (INDEX_REG_CLASS): Call new function riscv_index_reg_class(). (REGNO_OK_FOR_INDEX_P): Call new function riscv_regno_ok_for_index_p(). Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-protos.h | 2 ++ gcc/config/riscv/riscv.cc | 20 ++++++++++++++++++++ gcc/config/riscv/riscv.h | 6 ++++-- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 628c64cf628..b7417e97d99 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -82,6 +82,8 @@ struct riscv_address_info { extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool); +extern enum reg_class riscv_index_reg_class (); +extern int riscv_regno_ok_for_index_p (int); extern int riscv_address_insns (rtx, machine_mode, bool); extern int riscv_const_insns (rtx); extern int riscv_split_const_insns (rtx); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8388235d8cc..a33f0fff8ea 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -827,6 +827,26 @@ riscv_regno_mode_ok_for_base_p (int regno, return GP_REG_P (regno); } +/* Get valid index register class. + The RISC-V base instructions don't support index registers, + but extensions might support that. */ + +enum reg_class +riscv_index_reg_class () +{ + return NO_REGS; +} + +/* Return true if register REGNO is a valid index register. + The RISC-V base instructions don't support index registers, + but extensions might support that. */ + +int +riscv_regno_ok_for_index_p (int regno) +{ + return 0; +} + /* Return true if X is a valid base register for mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */ diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 90746fe14e3..21b81c22dea 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -535,7 +535,7 @@ enum reg_class factor or added to another register (as well as added to a displacement). */ -#define INDEX_REG_CLASS NO_REGS +#define INDEX_REG_CLASS riscv_index_reg_class() /* We generally want to put call-clobbered registers ahead of call-saved ones. (IRA expects this.) */ @@ -705,7 +705,9 @@ typedef struct { /* Addressing modes, and classification of registers for them. */ -#define REGNO_OK_FOR_INDEX_P(REGNO) 0 +#define REGNO_OK_FOR_INDEX_P(REGNO) \ + riscv_regno_ok_for_index_p (REGNO) + #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1) From patchwork Fri Apr 28 06:12:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 88456 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp729122vqo; Thu, 27 Apr 2023 23:16:40 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ55LfsLx0LsWEBz+w5/E2d8PXBxhvvuS73KW3f5qZ59p+UTBEjGkYM8cNDm4Db6x9dkEcMs X-Received: by 2002:a17:907:3d94:b0:947:72bd:f72a with SMTP id he20-20020a1709073d9400b0094772bdf72amr4109206ejc.72.1682662600610; Thu, 27 Apr 2023 23:16:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682662600; cv=none; d=google.com; s=arc-20160816; b=LnfrZVx4tRPsXJ6CjEln55eymry5+iMYUp+3wOVJD30n0OZquaviC82JMdlae8a91i za3SVuQ6sZEUXhQT5jze4wquPentNRvEEj6W0pS9A/pG5oDEU7xIDcslbNTNU1wUODHW iHiDXK9npXRacLwF52zQmrgc6Dsc2M7FiphkjSBXuBb1acUJmyxaYIXBWmtZDIQJcblW 3Qel3gwLjemqyTWHYcHVcRIk4gPHDgC2Hsohpo0I/oI1Xu6FJSlrj86uUCXsdMij/nYt aFdFTnMxvzSKkxy2826FK/PMtx357gOwFGukEjdV8gNrwSlt7zq/3SDbVoRoDQ/qUEW7 TBdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=AOMvpaRB7JwuHoTJjmK0Tm82n/ZGehm3uadhCC4HgV0=; b=hMJLZFpmveDwXZnwhk4gYHCfexVkUsLfAepaEgd/SvytqzjCE+ZX9I/b7xrM0a2Noq 3w0eKbtVx8cSuixa03yESgv90NxXFY6b/LCz8AuSEUKra+O6iMEkMXF4r/0SXGUQFxn9 hNhNnpoqsr4kOAyLrAx0XmnpnEYzKjP3UDp6wQ5o3XkuLLe4zG1OOeCykF1+Yxoepj+e mtr9WFl9TiRNEJw0/9+Fd/KX/TFAhSvREK3OJuB9goB8PoWWQLJIzkKQbVpKrYx0McPR Ekf5Gs7lm8nXx+RLOf1ucWuMcFQN2ZwgyT8ycfAn5guEC76bjo3RWkbQF2EbDo1l7rwG SZ9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=TIhL1+KE; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:26 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 09/11] riscv: thead: Factor out XThead*-specific peepholes Date: Fri, 28 Apr 2023 08:12:10 +0200 Message-Id: <20230428061210.2988035-10-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399618915886515?= X-GMAIL-MSGID: =?utf-8?q?1764399618915886515?= From: Christoph Müllner This patch moves the XThead*-specific peephole passes into thead-peephole.md with the intend to keep vendor-specific code separated from RISC-V standard code. This patch does not contain any functional changes. gcc/ChangeLog: * config/riscv/peephole.md: Remove XThead* peephole passes. * config/riscv/thead.md: Include thead-peephole.md. * config/riscv/thead-peephole.md: New file. Signed-off-by: Christoph Müllner --- gcc/config/riscv/peephole.md | 56 ---------------------- gcc/config/riscv/thead-peephole.md | 74 ++++++++++++++++++++++++++++++ gcc/config/riscv/thead.md | 2 + 3 files changed, 76 insertions(+), 56 deletions(-) create mode 100644 gcc/config/riscv/thead-peephole.md diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md index 67e7046d7e6..0ef0c04410b 100644 --- a/gcc/config/riscv/peephole.md +++ b/gcc/config/riscv/peephole.md @@ -38,59 +38,3 @@ (define_peephole2 { operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5])); }) - -;; XTheadMemPair: merge two SI or DI loads -(define_peephole2 - [(set (match_operand:GPR 0 "register_operand" "") - (match_operand:GPR 1 "memory_operand" "")) - (set (match_operand:GPR 2 "register_operand" "") - (match_operand:GPR 3 "memory_operand" ""))] - "TARGET_XTHEADMEMPAIR - && th_mempair_operands_p (operands, true, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] -{ - th_mempair_order_operands (operands, true, mode); -}) - -;; XTheadMemPair: merge two SI or DI stores -(define_peephole2 - [(set (match_operand:GPR 0 "memory_operand" "") - (match_operand:GPR 1 "register_operand" "")) - (set (match_operand:GPR 2 "memory_operand" "") - (match_operand:GPR 3 "register_operand" ""))] - "TARGET_XTHEADMEMPAIR - && th_mempair_operands_p (operands, false, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] -{ - th_mempair_order_operands (operands, false, mode); -}) - -;; XTheadMemPair: merge two SI loads with sign-extension -(define_peephole2 - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:SI 1 "memory_operand" ""))) - (set (match_operand:DI 2 "register_operand" "") - (sign_extend:DI (match_operand:SI 3 "memory_operand" "")))] - "TARGET_XTHEADMEMPAIR && TARGET_64BIT - && th_mempair_operands_p (operands, true, SImode)" - [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1))) - (set (match_dup 2) (sign_extend:DI (match_dup 3)))])] -{ - th_mempair_order_operands (operands, true, SImode); -}) - -;; XTheadMemPair: merge two SI loads with zero-extension -(define_peephole2 - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:SI 1 "memory_operand" ""))) - (set (match_operand:DI 2 "register_operand" "") - (zero_extend:DI (match_operand:SI 3 "memory_operand" "")))] - "TARGET_XTHEADMEMPAIR && TARGET_64BIT - && th_mempair_operands_p (operands, true, SImode)" - [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1))) - (set (match_dup 2) (zero_extend:DI (match_dup 3)))])] -{ - th_mempair_order_operands (operands, true, SImode); -}) diff --git a/gcc/config/riscv/thead-peephole.md b/gcc/config/riscv/thead-peephole.md new file mode 100644 index 00000000000..5b829b5b968 --- /dev/null +++ b/gcc/config/riscv/thead-peephole.md @@ -0,0 +1,74 @@ +;; Machine description for T-Head vendor extensions +;; Copyright (C) 2023 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; XTheadMemPair: merge two SI or DI loads +(define_peephole2 + [(set (match_operand:GPR 0 "register_operand" "") + (match_operand:GPR 1 "memory_operand" "")) + (set (match_operand:GPR 2 "register_operand" "") + (match_operand:GPR 3 "memory_operand" ""))] + "TARGET_XTHEADMEMPAIR + && th_mempair_operands_p (operands, true, mode)" + [(parallel [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3))])] +{ + th_mempair_order_operands (operands, true, mode); +}) + +;; XTheadMemPair: merge two SI or DI stores +(define_peephole2 + [(set (match_operand:GPR 0 "memory_operand" "") + (match_operand:GPR 1 "register_operand" "")) + (set (match_operand:GPR 2 "memory_operand" "") + (match_operand:GPR 3 "register_operand" ""))] + "TARGET_XTHEADMEMPAIR + && th_mempair_operands_p (operands, false, mode)" + [(parallel [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3))])] +{ + th_mempair_order_operands (operands, false, mode); +}) + +;; XTheadMemPair: merge two SI loads with sign-extension +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (sign_extend:DI (match_operand:SI 1 "memory_operand" ""))) + (set (match_operand:DI 2 "register_operand" "") + (sign_extend:DI (match_operand:SI 3 "memory_operand" "")))] + "TARGET_XTHEADMEMPAIR && TARGET_64BIT + && th_mempair_operands_p (operands, true, SImode)" + [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1))) + (set (match_dup 2) (sign_extend:DI (match_dup 3)))])] +{ + th_mempair_order_operands (operands, true, SImode); +}) + +;; XTheadMemPair: merge two SI loads with zero-extension +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:SI 1 "memory_operand" ""))) + (set (match_operand:DI 2 "register_operand" "") + (zero_extend:DI (match_operand:SI 3 "memory_operand" "")))] + "TARGET_XTHEADMEMPAIR && TARGET_64BIT + && th_mempair_operands_p (operands, true, SImode)" + [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1))) + (set (match_dup 2) (zero_extend:DI (match_dup 3)))])] +{ + th_mempair_order_operands (operands, true, SImode); +}) diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index aa933960a98..1ac4dd9b462 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -374,3 +374,5 @@ (define_insn "*th_mempair_load_zero_extendsidi2" [(set_attr "move_type" "load") (set_attr "mode" "DI") (set_attr "length" "8")]) + +(include "thead-peephole.md") From patchwork Fri Apr 28 06:23:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 88462 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp732215vqo; Thu, 27 Apr 2023 23:24:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ612B2Kg+CIohqn5lg+rO8KMRP+jRbhHSEWs4pnv6kFSV1TNVLCcI1Hai0Irb1GGUS2cr1h X-Received: by 2002:a17:906:4fd6:b0:94a:78a2:6092 with SMTP id i22-20020a1709064fd600b0094a78a26092mr3885884ejw.66.1682663079143; Thu, 27 Apr 2023 23:24:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682663079; cv=none; d=google.com; s=arc-20160816; b=hWDtYhCshqqD+sdrUGL7M+oerLMERY76bGXjOwJVr4TRctyjye/Y1BakemU0fosDud 6GiYHHzLQh4Y3nhJtOysgjBR+u7E0uUtxDCb8/2xZ2SRQUHhGgTC2DTaZdM0VrFGlbAt AcEX0QS8+85U/yqg/GKZ7clECb9w+vI7sImBwUXh7yNCmQnQ2wCKkI5TS/wDiisgADV2 dIFCqW0OeeZMF4UjYQbutl4g5JA1EBuKOzckoIKH1IZHCYTeudF+ga7DpFgNNKIqXV/P qwhL+6NOqZf5GryqUFogpa9lguFi/DkFNNDwLOSYzrKVXqIjL847yakXwXy4WdsKtU3y 3sbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature :dmarc-filter:delivered-to; bh=l0hJzFd1u/MxAj1ZRNLY9WR5K3FkzsKZq8MJ6OJeMgQ=; b=s0+Rf9fIuyjGhhT0+agRISNSxl6nUoopfswP2JMZVDH+H45dlbbWy4U/chSCdq3qoQ K2IGm7Chs2yF/lLcd/Lh9KydGr7Sq1fjBl78GRi4hyToV9cQZJxY29NRPC00zE6ytEkV YGLzNRu7pXNhOXUZJ+Lb3yTKAWpFH9jTi3chw82lMtm1AzjiOFFxLZMbPEjCSPgk4Be4 jHLePcDP9p89kcI3rdT8aNmpaR7EXMSD9ssAdeEZWcsZ6tx1nVmNodr1i+9fQ6aG0x9m UvksRnPRYR3hWAADNn3bGFrAAU/nOLRj5SoTnzMBFv9Jf/Sv9ukT1HBK3yv+QRCLmCv1 9qtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@vrull.eu header.s=google header.b=J6TNUTQq; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id e14-20020a170906504e00b0094a90d3e385sm10556730ejk.30.2023.04.27.23.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:23:17 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 10/11] riscv: thead: Add support for the XTheadMemIdx ISA extension Date: Fri, 28 Apr 2023 08:23:13 +0200 Message-Id: <20230428062314.2995571-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764400121128517648?= X-GMAIL-MSGID: =?utf-8?q?1764400121128517648?= From: Christoph Müllner The XTheadMemIdx ISA extension provides a additional load and store instructions with new addressing modes. The following memory accesses types are supported: * ltype = [b,bu,h,hu,w,wu,d] * stype = [b,h,w,d] The following addressing modes are supported: * immediate offset with PRE_MODIFY or POST_MODIFY (22 instructions): l.ia, l.ib, s.ia, s.ib * register offset with additional immediate offset (11 instructions): lr, sr * zero-extended register offset with additional immediate offset (11 instructions): lur, sur The RISC-V base ISA does not support index registers, so the changes are kept separate from the RISC-V standard support. Similar like other extensions (Zbb, XTheadBb), this patch needs to prevent the conversion of sign-extensions/zero-extensions into shift instructions. The case of the zero-extended register offset addressing mode is handled by a new peephole pass. Handling the different cases of extensions results in a couple of INSNs that look redundant on first view, but they are just the equivalent of what we already have for Zbb as well. The only difference is, that we have much more load instructions. To fully utilize the capabilities of the instructions, there are a few new peephole passes which fold shift amounts into the RTX if possible. The added tests ensure that this feature won't regress without notice. We already have a constraint with the name 'th_f_fmv', therefore, the new constraints follow this pattern and have the same length as required ('th_m_mia', 'th_m_mib', 'th_m_mir', 'th_m_miu'). gcc/ChangeLog: * config/riscv/constraints.md (th_m_mia): New constraint. (th_m_mib): Likewise. (th_m_mir): Likewise. (th_m_miu): Likewise. * config/riscv/riscv-protos.h (enum riscv_address_type): Add new address types ADDRESS_REG_REG, ADDRESS_REG_UREG, and ADDRESS_REG_WB and their documentation. (struct riscv_address_info): Add new field 'shift' and document the field usage for the new address types. (riscv_valid_base_register_p): New prototype. (th_memidx_legitimate_modify_p): Likewise. (th_memidx_legitimate_index_p): Likewise. (th_classify_address): Likewise. (th_output_move): Likewise. (th_print_operand_address): Likewise. * config/riscv/riscv.cc (riscv_index_reg_class): Return GR_REGS for XTheadMemIdx. (riscv_regno_ok_for_index_p): Add support for XTheadMemIdx. (riscv_classify_address): Call th_classify_address() on top. (riscv_output_move): Call th_output_move() on top. (riscv_print_operand_address): Call th_print_operand_address() on top. * config/riscv/riscv.h (HAVE_POST_MODIFY_DISP): New macro. (HAVE_PRE_MODIFY_DISP): Likewise. * config/riscv/riscv.md (zero_extendqi2): Disable for XTheadMemIdx. (*zero_extendqi2_internal): Convert to expand, create INSN with same name and disable it for XTheadMemIdx. (extendsidi2): Likewise. (*extendsidi2_internal): Disable for XTheadMemIdx. * config/riscv/thead-peephole.md: Add helper peephole passes. * config/riscv/thead.cc (valid_signed_immediate): New helper function. (th_memidx_classify_address_modify): New function. (th_memidx_legitimate_modify_p): Likewise. (th_memidx_output_modify): Likewise. (is_memidx_mode): Likewise. (th_memidx_classify_address_index): Likewise. (th_memidx_legitimate_index_p): Likewise. (th_memidx_output_index): Likewise. (th_classify_address): Likewise. (th_output_move): Likewise. (th_print_operand_address): Likewise. * config/riscv/thead.md (*th_memidx_mov2): New INSN. (*th_memidx_zero_extendqi2): Likewise. (*th_memidx_extendsidi2): Likewise (*th_memidx_zero_extendsidi2): Likewise. (*th_memidx_zero_extendhi2): Likewise. (*th_memidx_extend2): Likewise (*th_memidx_bb_zero_extendsidi2): Likewise. (*th_memidx_bb_zero_extendhi2): Likewise. (*th_memidx_bb_extendhi2): Likewise. (*th_memidx_bb_extendqi2): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadmemidx-helpers.h: New test. * gcc.target/riscv/xtheadmemidx-index-update.c: New test. * gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c: New test. * gcc.target/riscv/xtheadmemidx-index-xtheadbb.c: New test. * gcc.target/riscv/xtheadmemidx-index.c: New test. * gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c: New test. * gcc.target/riscv/xtheadmemidx-modify.c: New test. * gcc.target/riscv/xtheadmemidx-uindex-update.c: New test. * gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c: New test. * gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c: New test. * gcc.target/riscv/xtheadmemidx-uindex.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/constraints.md | 24 + gcc/config/riscv/riscv-protos.h | 29 ++ gcc/config/riscv/riscv.cc | 22 +- gcc/config/riscv/riscv.h | 3 + gcc/config/riscv/riscv.md | 26 +- gcc/config/riscv/thead-peephole.md | 214 +++++++++ gcc/config/riscv/thead.cc | 428 ++++++++++++++++++ gcc/config/riscv/thead.md | 186 +++++++- .../gcc.target/riscv/xtheadmemidx-helpers.h | 152 +++++++ .../riscv/xtheadmemidx-index-update.c | 27 ++ .../xtheadmemidx-index-xtheadbb-update.c | 27 ++ .../riscv/xtheadmemidx-index-xtheadbb.c | 36 ++ .../gcc.target/riscv/xtheadmemidx-index.c | 36 ++ .../riscv/xtheadmemidx-modify-xtheadbb.c | 74 +++ .../gcc.target/riscv/xtheadmemidx-modify.c | 74 +++ .../riscv/xtheadmemidx-uindex-update.c | 27 ++ .../xtheadmemidx-uindex-xtheadbb-update.c | 27 ++ .../riscv/xtheadmemidx-uindex-xtheadbb.c | 44 ++ .../gcc.target/riscv/xtheadmemidx-uindex.c | 44 ++ 19 files changed, 1489 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-index.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index c448e6b37e9..9cf83c0aa8f 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -188,3 +188,27 @@ (define_register_constraint "th_f_fmv" "TARGET_XTHEADFMV ? FP_REGS : NO_REGS" (define_register_constraint "th_r_fmv" "TARGET_XTHEADFMV ? GR_REGS : NO_REGS" "An integer register for XTheadFmv.") + +(define_memory_constraint "th_m_mia" + "@internal + A MEM with a valid address for th.[l|s]*ia instructions." + (and (match_code "mem") + (match_test "th_memidx_legitimate_modify_p (op, true)"))) + +(define_memory_constraint "th_m_mib" + "@internal + A MEM with a valid address for th.[l|s]*ib instructions." + (and (match_code "mem") + (match_test "th_memidx_legitimate_modify_p (op, false)"))) + +(define_memory_constraint "th_m_mir" + "@internal + A MEM with a valid address for th.[l|s]*r* instructions." + (and (match_code "mem") + (match_test "th_memidx_legitimate_index_p (op, false)"))) + +(define_memory_constraint "th_m_miu" + "@internal + A MEM with a valid address for th.[l|s]*ur* instructions." + (and (match_code "mem") + (match_test "th_memidx_legitimate_index_p (op, true)"))) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index b7417e97d99..d9b3c964285 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -41,6 +41,15 @@ enum riscv_symbol_type { A natural register + offset address. The register satisfies riscv_valid_base_register_p and the offset is a const_arith_operand. + ADDRESS_REG_REG + A base register indexed by (optionally scaled) register. + + ADDRESS_REG_UREG + A base register indexed by (optionally scaled) zero-extended register. + + ADDRESS_REG_WB + A base register indexed by immediate offset with writeback. + ADDRESS_LO_SUM A LO_SUM rtx. The first operand is a valid base register and the second operand is a symbolic address. @@ -52,6 +61,9 @@ enum riscv_symbol_type { A constant symbolic address. */ enum riscv_address_type { ADDRESS_REG, + ADDRESS_REG_REG, + ADDRESS_REG_UREG, + ADDRESS_REG_WB, ADDRESS_LO_SUM, ADDRESS_CONST_INT, ADDRESS_SYMBOLIC @@ -65,6 +77,13 @@ enum riscv_address_type { ADDRESS_REG REG is the base register and OFFSET is the constant offset. + ADDRESS_REG_REG and ADDRESS_REG_UREG + REG is the base register and OFFSET is the index register. + + ADDRESS_REG_WB + REG is the base register, OFFSET is the constant offset, and + shift is the shift amount for the offset. + ADDRESS_LO_SUM REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE is the type of symbol it references. @@ -76,12 +95,14 @@ struct riscv_address_info { rtx reg; rtx offset; enum riscv_symbol_type symbol_type; + int shift; }; /* Routines implemented in riscv.cc. */ extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool); +extern bool riscv_valid_base_register_p (rtx, machine_mode, bool); extern enum reg_class riscv_index_reg_class (); extern int riscv_regno_ok_for_index_p (int); extern int riscv_address_insns (rtx, machine_mode, bool); @@ -280,6 +301,14 @@ extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode); #ifdef RTX_CODE extern const char* th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); +extern bool th_memidx_legitimate_modify_p (rtx); +extern bool th_memidx_legitimate_modify_p (rtx, bool); +extern bool th_memidx_legitimate_index_p (rtx); +extern bool th_memidx_legitimate_index_p (rtx, bool); +extern bool th_classify_address (struct riscv_address_info *, + rtx, machine_mode, bool); +extern const char *th_output_move (rtx, rtx); +extern bool th_print_operand_address (FILE *, machine_mode, rtx); #endif #endif /* ! GCC_RISCV_PROTOS_H */ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index a33f0fff8ea..1691ecf3a94 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -834,6 +834,9 @@ riscv_regno_mode_ok_for_base_p (int regno, enum reg_class riscv_index_reg_class () { + if (TARGET_XTHEADMEMIDX) + return GR_REGS; + return NO_REGS; } @@ -844,13 +847,16 @@ riscv_index_reg_class () int riscv_regno_ok_for_index_p (int regno) { + if (TARGET_XTHEADMEMIDX) + return riscv_regno_mode_ok_for_base_p (regno, VOIDmode, 1); + return 0; } /* Return true if X is a valid base register for mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */ -static bool +bool riscv_valid_base_register_p (rtx x, machine_mode mode, bool strict_p) { if (!strict_p && GET_CODE (x) == SUBREG) @@ -1022,6 +1028,9 @@ static bool riscv_classify_address (struct riscv_address_info *info, rtx x, machine_mode mode, bool strict_p) { + if (th_classify_address (info, x, mode, strict_p)) + return true; + switch (GET_CODE (x)) { case REG: @@ -2813,6 +2822,10 @@ riscv_output_move (rtx dest, rtx src) machine_mode mode; bool dbl_p; unsigned width; + const char *insn; + + if ((insn = th_output_move (dest, src))) + return insn; dest_code = GET_CODE (dest); src_code = GET_CODE (src); @@ -4554,6 +4567,9 @@ riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx { struct riscv_address_info addr; + if (th_print_operand_address (file, mode, x)) + return; + if (riscv_classify_address (&addr, x, word_mode, true)) switch (addr.type) { @@ -4575,7 +4591,11 @@ riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx case ADDRESS_SYMBOLIC: output_addr_const (file, riscv_strip_unspec_address (x)); return; + + default: + gcc_unreachable (); } + gcc_unreachable (); } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 21b81c22dea..7b8cc6f6499 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1103,4 +1103,7 @@ extern void riscv_remove_unneeded_save_restore_calls (void); #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \ ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO) +#define HAVE_POST_MODIFY_DISP TARGET_XTHEADMEMIDX +#define HAVE_PRE_MODIFY_DISP TARGET_XTHEADMEMIDX + #endif /* ! GCC_RISCV_H */ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index f4cc99187ed..1d260ddacfa 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1368,7 +1368,7 @@ (define_insn_and_split "*zero_extendsidi2_internal" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] - "TARGET_64BIT && !TARGET_ZBA && !TARGET_XTHEADBB + "TARGET_64BIT && !TARGET_ZBA && !TARGET_XTHEADBB && !TARGET_XTHEADMEMIDX && !(register_operand (operands[1], SImode) && reg_or_subregno (operands[1]) == VL_REGNUM)" "@ @@ -1395,7 +1395,7 @@ (define_insn_and_split "*zero_extendhi2" [(set (match_operand:GPR 0 "register_operand" "=r,r") (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" " r,m")))] - "!TARGET_ZBB && !TARGET_XTHEADBB" + "!TARGET_ZBB && !TARGET_XTHEADBB && !TARGET_XTHEADMEMIDX" "@ # lhu\t%0,%1" @@ -1413,11 +1413,17 @@ (define_insn_and_split "*zero_extendhi2" [(set_attr "move_type" "shift_shift,load") (set_attr "mode" "")]) -(define_insn "zero_extendqi2" +(define_expand "zero_extendqi2" + [(set (match_operand:SUPERQI 0 "register_operand") + (zero_extend:SUPERQI + (match_operand:QI 1 "nonimmediate_operand")))] + "") + +(define_insn "*zero_extendqi2_internal" [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") (zero_extend:SUPERQI (match_operand:QI 1 "nonimmediate_operand" " r,m")))] - "" + "!TARGET_XTHEADMEMIDX" "@ andi\t%0,%1,0xff lbu\t%0,%1" @@ -1431,11 +1437,17 @@ (define_insn "zero_extendqi2" ;; ;; .................... -(define_insn "extendsidi2" +(define_expand "extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r,r") (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] - "TARGET_64BIT" + "TARGET_64BIT") + +(define_insn "*extendsidi2_internal" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (sign_extend:DI + (match_operand:SI 1 "nonimmediate_operand" " r,m")))] + "TARGET_64BIT && !TARGET_XTHEADMEMIDX && !TARGET_XTHEADMEMIDX" "@ sext.w\t%0,%1 lw\t%0,%1" @@ -1451,7 +1463,7 @@ (define_insn_and_split "*extend2" [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") (sign_extend:SUPERQI (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))] - "!TARGET_ZBB && !TARGET_XTHEADBB" + "!TARGET_ZBB && !TARGET_XTHEADBB && !TARGET_XTHEADMEMIDX" "@ # l\t%0,%1" diff --git a/gcc/config/riscv/thead-peephole.md b/gcc/config/riscv/thead-peephole.md index 5b829b5b968..2a4c734a220 100644 --- a/gcc/config/riscv/thead-peephole.md +++ b/gcc/config/riscv/thead-peephole.md @@ -72,3 +72,217 @@ (define_peephole2 { th_mempair_order_operands (operands, true, SImode); }) + +;; All modes that are supported by XTheadMemIdx +(define_mode_iterator TH_M_ANY [QI HI SI (DI "TARGET_64BIT")]) + +;; All non-extension modes that are supported by XTheadMemIdx +(define_mode_iterator TH_M_NOEXT [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) + +;; XTheadMemIdx overview: +;; All peephole passes attempt to improve the operand utilization of +;; XTheadMemIdx instructions, where one sign or zero extended +;; register-index-operand can be shifted left by a 2-bit immediate. +;; +;; The basic idea is the following optimization: +;; (set (reg 0) (op (reg 1) (imm 2))) +;; (set (reg 3) (mem (plus (reg 0) (reg 4))) +;; ==> +;; (set (reg 3) (mem (plus (reg 4) (op2 (reg 1) (imm 2)))) +;; This optimization only valid if (reg 0) has no further uses. +;; +;; The three-instruction case is as follows: +;; (set (reg 0) (op1 (reg 1) (imm 2))) +;; (set (reg 3) (op2 (reg 0) (imm 4))) +;; (set (reg 5) (mem (plus (reg 3) (reg 6))) +;; ==> +;; (set (reg 5) (mem (plus (reg 6) (op2 (reg 1) (imm 2/4))))) +;; This optimization is only valid if (reg 0) and (reg 3) have no further uses. +;; +;; The optimization cases are: +;; I) fold 2-bit ashift of register offset into mem-plus RTX +;; US) fold 32-bit zero-extended (shift) offset into mem-plus +;; UZ) fold 32-bit zero-extended (zext) offset into mem-plus +;; +;; The first optimization case is targeting the th.lr instructions. +;; The other optimization cases are targeting the th.lur instructions +;; and have to consider two forms of zero-extensions: +;; - ashift-32 + lshiftrt-{29..32} if there are no zero-extension instructions. +;; Left-shift amounts of 29..31 indicate a left-shifted zero-extended value. +;; - zero-extend32 if there are zero-extension instructions (XTheadBb or Zbb). +;; +;; We always have three peephole passes per optimization case: +;; a) no-extended (X) word-load +;; b) any-extend (SUBX) word-load +;; c) store + +;; XTheadMemIdx I/a +(define_peephole2 + [(set (match_operand:X 0 "register_operand" "") + (ashift:X (match_operand:X 1 "register_operand" "") + (match_operand:QI 2 "immediate_operand" ""))) + (set (match_operand:TH_M_NOEXT 3 "register_operand" "") + (mem:TH_M_NOEXT (plus:X + (match_dup 0) + (match_operand:X 4 "register_operand" ""))))] + "TARGET_XTHEADMEMIDX + && peep2_reg_dead_p (2, operands[0]) + && IN_RANGE (INTVAL (operands[2]), 0, 3)" + [(set (match_dup 3) + (mem:TH_M_NOEXT (plus:X + (match_dup 4) + (ashift:X (match_dup 1) (match_dup 2)))))] +) + +;; XTheadMemIdx I/b +(define_peephole2 + [(set (match_operand:X 0 "register_operand" "") + (ashift:X (match_operand:X 1 "register_operand" "") + (match_operand:QI 2 "immediate_operand" ""))) + (set (match_operand:X 3 "register_operand" "") + (any_extend:X (mem:SUBX (plus:X + (match_dup 0) + (match_operand:X 4 "register_operand" "")))))] + "TARGET_XTHEADMEMIDX + && peep2_reg_dead_p (2, operands[0]) + && IN_RANGE (INTVAL (operands[2]), 0, 3)" + [(set (match_dup 3) + (any_extend:X (mem:SUBX (plus:X + (match_dup 4) + (ashift:X (match_dup 1) (match_dup 2))))))] +) + +;; XTheadMemIdx I/c +(define_peephole2 + [(set (match_operand:X 0 "register_operand" "") + (ashift:X (match_operand:X 1 "register_operand" "") + (match_operand:QI 2 "immediate_operand" ""))) + (set (mem:TH_M_ANY (plus:X + (match_dup 0) + (match_operand:X 4 "register_operand" ""))) + (match_operand:TH_M_ANY 3 "register_operand" ""))] + "TARGET_XTHEADMEMIDX + && peep2_reg_dead_p (2, operands[0]) + && IN_RANGE (INTVAL (operands[2]), 0, 3)" + [(set (mem:TH_M_ANY (plus:X + (match_dup 4) + (ashift:X (match_dup 1) (match_dup 2)))) + (match_dup 3))] +) + +;; XTheadMemIdx US/a +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") (const_int 32))) + (set (match_operand:DI 3 "register_operand" "") + (lshiftrt:DI (match_dup 0) (match_operand:QI 4 "immediate_operand" ""))) + (set (match_operand:TH_M_NOEXT 5 "register_operand" "") + (mem:TH_M_NOEXT (plus:DI + (match_dup 3) + (match_operand:DI 6 "register_operand" ""))))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX + && peep2_reg_dead_p (3, operands[0]) + && peep2_reg_dead_p (3, operands[3]) + && IN_RANGE (INTVAL (operands[4]), 29, 32)" + [(set (match_dup 5) + (mem:TH_M_NOEXT (plus:DI + (match_dup 6) + (ashift:DI (zero_extend:DI (match_dup 1)) (match_dup 4)))))] + { operands[1] = gen_lowpart (SImode, operands[1]); + operands[4] = GEN_INT (32 - (INTVAL (operands [4]))); + } +) + +;; XTheadMemIdx US/b +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") (const_int 32))) + (set (match_operand:DI 3 "register_operand" "") + (lshiftrt:DI (match_dup 0) (match_operand:QI 4 "immediate_operand" ""))) + (set (match_operand:X 5 "register_operand" "") + (any_extend:X (mem:SUBX (plus:DI + (match_dup 3) + (match_operand:DI 6 "register_operand" "")))))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX + && peep2_reg_dead_p (3, operands[0]) + && peep2_reg_dead_p (3, operands[3]) + && IN_RANGE (INTVAL (operands[4]), 29, 32)" + [(set (match_dup 5) + (any_extend:X (mem:SUBX (plus:DI + (match_dup 6) + (ashift:DI (zero_extend:DI (match_dup 1)) (match_dup 4))))))] + { operands[1] = gen_lowpart (SImode, operands[1]); + operands[4] = GEN_INT (32 - (INTVAL (operands [4]))); + } +) + +;; XTheadMemIdx US/c +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") (const_int 32))) + (set (match_operand:DI 3 "register_operand" "") + (lshiftrt:DI (match_dup 0) (match_operand:QI 4 "immediate_operand" ""))) + (set (mem:TH_M_ANY (plus:DI + (match_dup 3) + (match_operand:DI 6 "register_operand" ""))) + (match_operand:TH_M_ANY 5 "register_operand" ""))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX + && peep2_reg_dead_p (3, operands[0]) + && peep2_reg_dead_p (3, operands[3]) + && IN_RANGE (INTVAL (operands[4]), 29, 32)" + [(set (mem:TH_M_ANY (plus:DI + (match_dup 6) + (ashift:DI (zero_extend:DI (match_dup 1)) (match_dup 4)))) + (match_dup 5))] + { operands[1] = gen_lowpart (SImode, operands[1]); + operands[4] = GEN_INT (32 - (INTVAL (operands [4]))); + } +) + +;; XTheadMemIdx UZ/a +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) + (set (match_operand:TH_M_NOEXT 3 "register_operand" "") + (mem:TH_M_NOEXT (plus:DI + (match_dup 0) + (match_operand:DI 4 "register_operand" ""))))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX + && peep2_reg_dead_p (2, operands[0])" + [(set (match_dup 3) + (mem:TH_M_NOEXT (plus:DI + (match_dup 4) + (zero_extend:DI (match_dup 1)))))] +) + +;; XTheadMemIdx UZ/b +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) + (set (match_operand:X 3 "register_operand" "") + (any_extend:X (mem:SUBX (plus:DI + (match_dup 0) + (match_operand:DI 4 "register_operand" "")))))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX + && peep2_reg_dead_p (2, operands[0])" + [(set (match_dup 3) + (any_extend:X (mem:SUBX (plus:DI + (match_dup 4) + (zero_extend:DI (match_dup 1))))))] +) + +;; XTheadMemIdx UZ/c +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) + (set (mem:TH_M_ANY (plus:DI + (match_dup 0) + (match_operand:DI 4 "register_operand" ""))) + (match_operand:TH_M_ANY 3 "register_operand" ""))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX + && peep2_reg_dead_p (2, operands[0])" + [(set (mem:TH_M_ANY (plus:DI + (match_dup 4) + (zero_extend:DI (match_dup 1)))) + (match_dup 3))] +) diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index 507c912bc39..bfe035250af 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -25,11 +25,16 @@ #include "coretypes.h" #include "target.h" #include "backend.h" +#include "tree.h" #include "rtl.h" +#include "explow.h" #include "memmodel.h" #include "emit-rtl.h" +#include "optabs.h" #include "poly-int.h" #include "output.h" +#include "regs.h" +#include "riscv-protos.h" /* If MEM is in the form of "base+offset", extract the two parts of address and set to BASE and OFFSET, otherwise return false @@ -429,3 +434,426 @@ th_mempair_save_restore_regs (rtx operands[4], bool load_p, else th_mempair_save_regs (operands); } + +/* Return true if X can be represented as signed immediate of NBITS bits. + The immediate is assumed to be shifted by LSHAMT bits left. */ + +static bool +valid_signed_immediate (rtx x, unsigned nbits, unsigned lshamt) +{ + if (GET_CODE (x) != CONST_INT) + return false; + + HOST_WIDE_INT v = INTVAL (x); + + HOST_WIDE_INT vunshifted = v >> lshamt; + + /* Make sure we did not shift out any bits. */ + if (vunshifted << lshamt != v) + return false; + + unsigned HOST_WIDE_INT imm_reach = 1LL << nbits; + return ((unsigned HOST_WIDE_INT) vunshifted + imm_reach/2 < imm_reach); +} + +/* Return true if X is a valid address for T-Head's memory addressing modes + with pre/post modification for machine mode MODE. + If it is, fill in INFO appropriately (if non-NULL). + If STRICT_P is true then REG_OK_STRICT is in effect. */ + +static bool +th_memidx_classify_address_modify (struct riscv_address_info *info, rtx x, + machine_mode mode, bool strict_p) +{ + if (!TARGET_XTHEADMEMIDX) + return false; + + if (!TARGET_64BIT && mode == DImode) + return false; + + if (!(INTEGRAL_MODE_P (mode) && GET_MODE_SIZE (mode).to_constant () <= 8)) + return false; + + if (GET_CODE (x) != POST_MODIFY + && GET_CODE (x) != PRE_MODIFY) + return false; + + rtx reg = XEXP (x, 0); + rtx exp = XEXP (x, 1); + rtx expreg = XEXP (exp, 0); + rtx expoff = XEXP (exp, 1); + + if (GET_CODE (exp) != PLUS + || !rtx_equal_p (expreg, reg) + || !CONST_INT_P (expoff) + || !riscv_valid_base_register_p (reg, mode, strict_p)) + return false; + + /* The offset is calculated as (sign_extend(imm5) << imm2) */ + const int shamt_bits = 2; + for (int shamt = 0; shamt < (1 << shamt_bits); shamt++) + { + const int nbits = 5; + if (valid_signed_immediate (expoff, nbits, shamt)) + { + if (info) + { + info->type = ADDRESS_REG_WB; + info->reg = reg; + info->offset = expoff; + info->shift = shamt; + } + return true; + } + } + + return false; +} + +/* Return TRUE if X is a MEM with a legitimate modify address. */ + +bool +th_memidx_legitimate_modify_p (rtx x) +{ + if (!MEM_P (x)) + return false; + + /* Get the mode from the MEM and unpack it. */ + machine_mode mode = GET_MODE (x); + x = XEXP (x, 0); + + return th_memidx_classify_address_modify (NULL, x, mode, reload_completed); +} + +/* Return TRUE if X is a MEM with a legitimate modify address + and the address is POST_MODIFY (if POST is true) or a PRE_MODIFY + (otherwise). */ + +bool +th_memidx_legitimate_modify_p (rtx x, bool post) +{ + if (!th_memidx_legitimate_modify_p (x)) + return false; + + /* Unpack the MEM and check the code. */ + x = XEXP (x, 0); + if (post) + return GET_CODE (x) == POST_MODIFY; + else + return GET_CODE (x) == PRE_MODIFY; +} + +/* Provide a buffer for a th.lXia/th.lXib/th.sXia/th.sXib instruction + for the given MODE. If LOAD is true, a load instruction will be + provided (otherwise, a store instruction). If X is not suitable + return NULL. */ + +static const char * +th_memidx_output_modify (rtx x, machine_mode mode, bool load) +{ + static char buf[128] = {0}; + + /* Validate x. */ + if (!th_memidx_classify_address_modify (NULL, x, mode, reload_completed)) + return NULL; + + int index = exact_log2 (GET_MODE_SIZE (mode).to_constant ()); + bool post = GET_CODE (x) == POST_MODIFY; + + const char *const insn[][4] = { + { + "th.sbi%s\t%%z1,%%0", + "th.shi%s\t%%z1,%%0", + "th.swi%s\t%%z1,%%0", + "th.sdi%s\t%%z1,%%0" + }, + { + "th.lbui%s\t%%0,%%1", + "th.lhui%s\t%%0,%%1", + "th.lwi%s\t%%0,%%1", + "th.ldi%s\t%%0,%%1" + } + }; + + snprintf (buf, sizeof (buf), insn[load][index], post ? "a" : "b"); + return buf; +} + +static bool +is_memidx_mode (machine_mode mode) +{ + if (mode == QImode || mode == HImode || mode == SImode) + return true; + + if (mode == DImode && TARGET_64BIT) + return true; + + return false; +} + +/* Return true if X is a valid address for T-Head's memory addressing modes + with scaled register offsets for machine mode MODE. + If it is, fill in INFO appropriately (if non-NULL). + If STRICT_P is true then REG_OK_STRICT is in effect. */ + +static bool +th_memidx_classify_address_index (struct riscv_address_info *info, rtx x, + machine_mode mode, bool strict_p) +{ + /* Ensure that the mode is supported. */ + if (!(TARGET_XTHEADMEMIDX && is_memidx_mode (mode))) + return false; + + if (GET_CODE (x) != PLUS) + return false; + + rtx reg = XEXP (x, 0); + enum riscv_address_type type; + rtx offset = XEXP (x, 1); + int shift; + + if (!riscv_valid_base_register_p (reg, mode, strict_p)) + return false; + + /* (reg:X) */ + if (REG_P (offset) + && GET_MODE (offset) == Xmode) + { + type = ADDRESS_REG_REG; + shift = 0; + offset = offset; + } + /* (zero_extend:DI (reg:SI)) */ + else if (GET_CODE (offset) == ZERO_EXTEND + && GET_MODE (offset) == DImode + && GET_MODE (XEXP (offset, 0)) == SImode) + { + type = ADDRESS_REG_UREG; + shift = 0; + offset = XEXP (offset, 0); + } + /* (ashift:X (reg:X) (const_int shift)) */ + else if (GET_CODE (offset) == ASHIFT + && GET_MODE (offset) == Xmode + && REG_P (XEXP (offset, 0)) + && GET_MODE (XEXP (offset, 0)) == Xmode + && CONST_INT_P (XEXP (offset, 1)) + && IN_RANGE(INTVAL (XEXP (offset, 1)), 0, 3)) + { + type = ADDRESS_REG_REG; + shift = INTVAL (XEXP (offset, 1)); + offset = XEXP (offset, 0); + } + /* (ashift:DI (zero_extend:DI (reg:SI)) (const_int shift)) */ + else if (GET_CODE (offset) == ASHIFT + && GET_MODE (offset) == DImode + && GET_CODE (XEXP (offset, 0)) == ZERO_EXTEND + && GET_MODE (XEXP (offset, 0)) == DImode + && REG_P (XEXP (XEXP (offset, 0), 0)) + && GET_MODE (XEXP (XEXP (offset, 0), 0)) == SImode + && CONST_INT_P (XEXP (offset, 1)) + && IN_RANGE(INTVAL (XEXP (offset, 1)), 0, 3)) + { + type = ADDRESS_REG_UREG; + shift = INTVAL (XEXP (offset, 1)); + offset = XEXP (XEXP (offset, 0), 0); + } + else + return false; + + if (!strict_p + && GET_CODE (offset) == SUBREG + && contains_reg_of_mode[GENERAL_REGS][GET_MODE (SUBREG_REG (offset))]) + offset = SUBREG_REG (offset); + + if (riscv_valid_base_register_p (offset, mode, strict_p)) + { + if (info) + { + info->reg = reg; + info->type = type; + info->offset = offset; + info->shift = shift; + } + return true; + } + return false; +} + +/* Return TRUE if X is a MEM with a legitimate indexed address. */ + +bool +th_memidx_legitimate_index_p (rtx x) +{ + if (!MEM_P (x)) + return false; + + /* Get the mode from the MEM and unpack it. */ + machine_mode mode = GET_MODE (x); + x = XEXP (x, 0); + + return th_memidx_classify_address_index (NULL, x, mode, reload_completed); +} + +/* Return TRUE if X is a MEM with a legitimate indexed address + and the offset register is zero-extended (if UINDEX is true) + or sign-extended (otherwise). */ + +bool +th_memidx_legitimate_index_p (rtx x, bool uindex) +{ + if (!MEM_P (x)) + return false; + + /* Get the mode from the MEM and unpack it. */ + machine_mode mode = GET_MODE (x); + x = XEXP (x, 0); + + struct riscv_address_info info; + if (!th_memidx_classify_address_index (&info, x, mode, reload_completed)) + return false; + + if (uindex) + return info.type == ADDRESS_REG_UREG; + else + return info.type == ADDRESS_REG_REG; +} + +/* Provide a buffer for a th.lrX/th.lurX/th.srX/th.surX instruction + for the given MODE. If LOAD is true, a load instruction will be + provided (otherwise, a store instruction). If X is not suitable + return NULL. */ + +static const char * +th_memidx_output_index (rtx x, machine_mode mode, bool load) +{ + struct riscv_address_info info; + static char buf[128] = {0}; + + /* Validate x. */ + if (!th_memidx_classify_address_index (&info, x, mode, reload_completed)) + return NULL; + + int index = exact_log2 (GET_MODE_SIZE (mode).to_constant ()); + bool uindex = info.type == ADDRESS_REG_UREG; + + const char *const insn[][4] = { + { + "th.s%srb\t%%z1,%%0", + "th.s%srh\t%%z1,%%0", + "th.s%srw\t%%z1,%%0", + "th.s%srd\t%%z1,%%0" + }, + { + "th.l%srbu\t%%0,%%1", + "th.l%srhu\t%%0,%%1", + "th.l%srw\t%%0,%%1", + "th.l%srd\t%%0,%%1" + } + }; + + snprintf (buf, sizeof (buf), insn[load][index], uindex ? "u" : ""); + + return buf; +} + +/* Return true if X is a valid address for T-Head's memory addressing modes + for machine mode MODE. If it is, fill in INFO appropriately (if non-NULL). + If STRICT_P is true then REG_OK_STRICT is in effect. */ + +bool +th_classify_address (struct riscv_address_info *info, rtx x, + machine_mode mode, bool strict_p) +{ + switch (GET_CODE (x)) + { + case PLUS: + if (th_memidx_classify_address_index (info, x, mode, strict_p)) + return true; + break; + + case POST_MODIFY: + case PRE_MODIFY: + if (th_memidx_classify_address_modify (info, x, mode, strict_p)) + return true; + break; + + default: + return false; + } + + return false; +} + +/* Provide a buffer for a XTheadMemIdx instruction for the given MODE. + If LOAD is true, a load instruction will be provided (otherwise, + a store instruction). If X is not suitable return NULL. */ + +const char * +th_output_move (rtx dest, rtx src) +{ + enum rtx_code dest_code, src_code; + machine_mode mode; + const char *insn = NULL; + + dest_code = GET_CODE (dest); + src_code = GET_CODE (src); + mode = GET_MODE (dest); + + if (dest_code == REG && GP_REG_P (REGNO (dest)) && src_code == MEM) + { + rtx x = XEXP (src, 0); + mode = GET_MODE (src); + + if ((insn = th_memidx_output_index (x, mode, true))) + return insn; + + if ((insn = th_memidx_output_modify (x, mode, true))) + return insn; + } + else if (((src_code == REG && GP_REG_P (REGNO (src))) + || (src == CONST0_RTX (mode))) + && dest_code == MEM) + { + rtx x = XEXP (dest, 0); + mode = GET_MODE (dest); + + if ((insn = th_memidx_output_index (x, mode, false))) + return insn; + + if ((insn = th_memidx_output_modify (x, mode, false))) + return insn; + } + + return NULL; +} + +/* Implement TARGET_PRINT_OPERAND_ADDRESS for XTheadMemIdx. */ + +bool +th_print_operand_address (FILE *file, machine_mode mode, rtx x) +{ + struct riscv_address_info addr; + + if (!th_classify_address (&addr, x, mode, reload_completed)) + return false; + + switch (addr.type) + { + case ADDRESS_REG_REG: + case ADDRESS_REG_UREG: + fprintf (file, "%s,%s,%u", reg_names[REGNO (addr.reg)], + reg_names[REGNO (addr.offset)], addr.shift); + return true; + + case ADDRESS_REG_WB: + fprintf (file, "(%s),%ld,%u", reg_names[REGNO (addr.reg)], + INTVAL (addr.offset) >> addr.shift, addr.shift); + return true; + + default: + gcc_unreachable (); + } + + gcc_unreachable (); +} diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 1ac4dd9b462..5536500e4ff 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -62,7 +62,7 @@ (define_insn "*extend2_th_ext" [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") (sign_extend:SUPERQI (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))] - "TARGET_XTHEADBB" + "TARGET_XTHEADBB && !TARGET_XTHEADMEMIDX" "@ th.ext\t%0,%1,15,0 l\t%0,%1" @@ -85,7 +85,7 @@ (define_insn "*th_extu4" (define_insn "*zero_extendsidi2_th_extu" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))] - "TARGET_64BIT && TARGET_XTHEADBB" + "TARGET_64BIT && TARGET_XTHEADBB && !TARGET_XTHEADMEMIDX" "@ th.extu\t%0,%1,31,0 lwu\t%0,%1" @@ -95,7 +95,7 @@ (define_insn "*zero_extendsidi2_th_extu" (define_insn "*zero_extendhi2_th_extu" [(set (match_operand:GPR 0 "register_operand" "=r,r") (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))] - "TARGET_XTHEADBB" + "TARGET_XTHEADBB && !TARGET_XTHEADMEMIDX" "@ th.extu\t%0,%1,15,0 lhu\t%0,%1" @@ -375,4 +375,184 @@ (define_insn "*th_mempair_load_zero_extendsidi2" (set_attr "mode" "DI") (set_attr "length" "8")]) +;; XTheadMemIdx + +(define_insn "*th_memidx_zero_extendqi2" + [(set (match_operand:SUPERQI 0 "register_operand" "=r,r,r,r,r,r") + (zero_extend:SUPERQI + (match_operand:QI 1 "nonimmediate_operand" + " r,th_m_mia,th_m_mib,th_m_mir,th_m_miu,m")))] + "TARGET_XTHEADMEMIDX" + "@ + andi\t%0,%1,0xff + th.lbuia\t%0,%1 + th.lbuib\t%0,%1 + th.lrbu\t%0,%1 + th.lurbu\t%0,%1 + lbu\t%0,%1" + [(set_attr "move_type" "andi,load,load,load,load,load") + (set_attr "mode" "")]) + +(define_insn "*th_memidx_extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r") + (sign_extend:DI + (match_operand:SI 1 "nonimmediate_operand" + " r,th_m_mia,th_m_mib,th_m_mir,th_m_miu,m")))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX" + "@ + sext.w\t%0,%1 + th.lwia\t%0,%1 + th.lwib\t%0,%1 + th.lrw\t%0,%1 + th.lurw\t%0,%1 + lw\t%0,%1" + [(set_attr "move_type" "move,load,load,load,load,load") + (set_attr "mode" "DI")]) + +;; XTheadMemIdx (without XTheadBb) + +(define_insn_and_split "*th_memidx_zero_extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r") + (zero_extend:DI + (match_operand:SI 1 "nonimmediate_operand" + " r,th_m_mia,th_m_mib,th_m_mir,th_m_miu,m")))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX && !TARGET_XTHEADBB" + "@ + # + th.lwuia\t%0,%1 + th.lwuib\t%0,%1 + th.lrwu\t%0,%1 + th.lurwu\t%0,%1 + lwu\t%0,%1" + "&& reload_completed + && REG_P (operands[1]) + && !paradoxical_subreg_p (operands[0])" + [(set (match_dup 0) + (ashift:DI (match_dup 1) (const_int 32))) + (set (match_dup 0) + (lshiftrt:DI (match_dup 0) (const_int 32)))] + { operands[1] = gen_lowpart (DImode, operands[1]); } + [(set_attr "move_type" "shift_shift,load,load,load,load,load") + (set_attr "mode" "DI")]) + +(define_insn_and_split "*th_memidx_zero_extendhi2" + [(set (match_operand:GPR 0 "register_operand" "=r,r,r,r,r,r") + (zero_extend:GPR + (match_operand:HI 1 "nonimmediate_operand" + " r,th_m_mia,th_m_mib,th_m_mir,th_m_miu,m")))] + "TARGET_XTHEADMEMIDX && !TARGET_XTHEADBB" + "@ + # + th.lhuia\t%0,%1 + th.lhuib\t%0,%1 + th.lrhu\t%0,%1 + th.lurhu\t%0,%1 + lhu\t%0,%1" + "&& reload_completed + && REG_P (operands[1]) + && !paradoxical_subreg_p (operands[0])" + [(set (match_dup 0) + (ashift:GPR (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (lshiftrt:GPR (match_dup 0) (match_dup 2)))] + { + operands[1] = gen_lowpart (mode, operands[1]); + operands[2] = GEN_INT(GET_MODE_BITSIZE(mode) - 16); + } + [(set_attr "move_type" "shift_shift,load,load,load,load,load") + (set_attr "mode" "")]) + +(define_insn_and_split "*th_memidx_extend2" + [(set (match_operand:SUPERQI 0 "register_operand" "=r,r,r,r,r,r") + (sign_extend:SUPERQI + (match_operand:SHORT 1 "nonimmediate_operand" + " r,th_m_mia,th_m_mib,th_m_mir,th_m_miu,m")))] + "TARGET_XTHEADMEMIDX && !TARGET_XTHEADBB" + "@ + # + th.lia\t%0,%1 + th.lib\t%0,%1 + th.lr\t%0,%1 + th.lur\t%0,%1 + l\t%0,%1" + "&& reload_completed + && REG_P (operands[1]) + && !paradoxical_subreg_p (operands[0])" + [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))] +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); + operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode) + - GET_MODE_BITSIZE (mode)); +} + [(set_attr "move_type" "shift_shift,load,load,load,load,load") + (set_attr "mode" "SI")]) + +;; XTheadMemIdx (with XTheadBb) + +(define_insn "*th_memidx_bb_zero_extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r") + (zero_extend:DI + (match_operand:SI 1 "nonimmediate_operand" + " r,th_m_mia,th_m_mib,th_m_mir,th_m_miu,m")))] + "TARGET_64BIT && TARGET_XTHEADMEMIDX && TARGET_XTHEADBB" + "@ + th.extu\t%0,%1,31,0 + th.lwuia\t%0,%1 + th.lwuib\t%0,%1 + th.lrwu\t%0,%1 + th.lurwu\t%0,%1 + lwu\t%0,%1" + [(set_attr "move_type" "shift_shift,load,load,load,load,load") + (set_attr "mode" "DI")]) + +(define_insn "*th_memidx_bb_zero_extendhi2" + [(set (match_operand:GPR 0 "register_operand" "=r,r,r,r,r,r") + (zero_extend:GPR + (match_operand:HI 1 "nonimmediate_operand" + " r,th_m_mia,th_m_mib,th_m_mir,th_m_miu,m")))] + "TARGET_XTHEADMEMIDX && TARGET_XTHEADBB" + "@ + th.extu\t%0,%1,15,0 + th.lhuia\t%0,%1 + th.lhuib\t%0,%1 + th.lrhu\t%0,%1 + th.lurhu\t%0,%1 + lhu\t%0,%1" + [(set_attr "move_type" "shift_shift,load,load,load,load,load") + (set_attr "mode" "")]) + +(define_insn "*th_memidx_bb_extendhi2" + [(set (match_operand:GPR 0 "register_operand" "=r,r,r,r,r,r") + (sign_extend:GPR + (match_operand:HI 1 "nonimmediate_operand" + " r,th_m_mia,th_m_mib,th_m_mir,th_m_miu,m")))] + "TARGET_XTHEADMEMIDX && TARGET_XTHEADBB" + "@ + th.ext\t%0,%1,15,0 + th.lhia\t%0,%1 + th.lhib\t%0,%1 + th.lrh\t%0,%1 + th.lurh\t%0,%1 + lh\t%0,%1" + [(set_attr "move_type" "shift_shift,load,load,load,load,load") + (set_attr "mode" "")]) + +(define_insn "*th_memidx_bb_extendqi2" + [(set (match_operand:SUPERQI 0 "register_operand" "=r,r,r,r,r,r") + (sign_extend:SUPERQI + (match_operand:QI 1 "nonimmediate_operand" + " r,th_m_mia,th_m_mib,th_m_mir,th_m_miu,m")))] + "TARGET_XTHEADMEMIDX && TARGET_XTHEADBB" + "@ + th.ext\t%0,%1,7,0 + th.lbia\t%0,%1 + th.lbib\t%0,%1 + th.lrb\t%0,%1 + th.lurb\t%0,%1 + lb\t%0,%1" + [(set_attr "move_type" "shift_shift,load,load,load,load,load") + (set_attr "mode" "")]) + (include "thead-peephole.md") diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h new file mode 100644 index 00000000000..a97f08c5cc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h @@ -0,0 +1,152 @@ +#ifndef XTHEADMEMIDX_HELPERS_H +#define XTHEADMEMIDX_HELPERS_H + +#include + +#define intX_t long +#define uintX_t unsigned long + +#define PRE_DEC_LOAD(T, N) \ + void \ + T ## _pre_dec_load_ ## N (T *p) \ + { \ + extern void f ## T ## N (T*, uintX_t); \ + p = p - N; \ + T x = *p; \ + f ## T ## N (p, x); \ + } + +#define PRE_INC_LOAD(T, N) \ + void \ + T ## _pre_inc_load_ ## N (T *p) \ + { \ + extern void f ## T ## N (T*, uintX_t); \ + p = p + N; \ + T x = *p; \ + f ## T ## N (p, x); \ + } + +#define POST_DEC_LOAD(T, N) \ + void \ + T ## _post_dec_load_ ## N (T *p) \ + { \ + extern void f ## T ## N (T*, uintX_t); \ + T x = *p; \ + p = p - N; \ + f ## T ## N (p, x); \ + } + +#define POST_INC_LOAD(T,N) \ + void \ + T ## _post_inc_load_ ## N (T *p) \ + { \ + extern void f ## T ## N (T*,uintX_t); \ + T x = *p; \ + p = p + N; \ + f ## T ## N (p, x); \ + } + +#define PRE_DEC_STORE(T, N) \ + T * \ + T ## _pre_dec_store_ ## N (T *p, T v) \ + { \ + p = p - N; \ + *p = v; \ + return p; \ + } + +#define PRE_INC_STORE(T, N) \ + T * \ + T ## _pre_inc_store_ ## N (T *p, T v) \ + { \ + p = p + N; \ + *p = v; \ + return p; \ + } + +#define POST_DEC_STORE(T, N) \ + T * \ + T ## _post_dec_store_ ## N (T *p, T v) \ + { \ + *p = v; \ + p = p - N; \ + return p; \ + } + +#define POST_INC_STORE(T, N) \ + T * \ + T ## _post_inc_store_ ## N (T *p, T v) \ + { \ + *p = v; \ + p = p + N; \ + return p; \ + } + +#define LR_REG_IMM(T, IMM) \ + intX_t \ + lr_reg_imm_ ## T ## _ ## IMM (intX_t rs1, intX_t rs2) \ + { \ + return *(T*)(rs1 + (rs2 << IMM)); \ + } + +#define SR_REG_IMM(T, IMM) \ + void \ + sr_reg_imm_ ## T ## _ ## IMM (intX_t rs1, intX_t rs2, T val) \ + { \ + *(T*)(rs1 + (rs2 << IMM)) = val; \ + } + +#define LR_REG_IMM_UPD(T, IMM) \ + intX_t \ + lr_reg_imm_upd_ ## T ## _ ## IMM (intX_t *rs1, intX_t rs2) \ + { \ + *rs1 = *rs1 + (rs2 << IMM); \ + return *(T*)(*rs1); \ + } + +#define SR_REG_IMM_UPD(T, IMM) \ + void \ + sr_reg_imm_upd_ ## T ## _ ## IMM (intX_t *rs1, intX_t rs2, T val) \ + { \ + *rs1 = *rs1 + (rs2 << IMM); \ + *(T*)(*rs1) = val; \ + } + +#define LRU_REG_IMM(T, IMM) \ + intX_t \ + lru_reg_imm_ ## T ## IMM (intX_t rs1, intX_t rs2) \ + { \ + rs2 = (uint32_t)rs2; \ + return *(T*)(rs1 + (rs2 << IMM)); \ + } + +#define SRU_REG_IMM(T, IMM) \ + void \ + sr_reg_imm_ ## T ## _ ## IMM (intX_t rs1, intX_t rs2, T val) \ + { \ + rs2 = (uint32_t)rs2; \ + *(T*)(rs1 + (rs2 << IMM)) = val; \ + } + +#define LRU_REG_IMM_UPD(T, IMM) \ + intX_t \ + lru_reg_imm_upd_ ## T ## IMM (intX_t rs1, intX_t *rs2) \ + { \ + uintX_t rs2_32 = (uint32_t)*rs2; \ + intX_t t = rs1 + (rs2_32 << IMM); \ + intX_t v = *(T*)t; \ + *rs2 = t; \ + return v; \ + } + +#define SRU_REG_IMM_UPD(T, IMM) \ + void \ + sr_reg_imm_upd_ ## T ## _ ## IMM (intX_t rs1, intX_t *rs2, T val) \ + { \ + uintX_t rs2_32 = (uint32_t)*rs2; \ + intX_t t = rs1 + (rs2_32 << IMM); \ + *(T*)t = val; \ + *rs2 = t; \ + } + +#endif /* XTHEADMEMIDX_HELPERS_H */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-update.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-update.c new file mode 100644 index 00000000000..8237b3e62cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-update.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LR_REG_IMM_UPD(int8_t, 0) +LR_REG_IMM_UPD(uint8_t, 1) +LR_REG_IMM_UPD(int16_t, 2) +LR_REG_IMM_UPD(uint16_t, 3) +LR_REG_IMM_UPD(int32_t, 0) +#if __riscv_xlen == 64 +LR_REG_IMM_UPD(uint32_t, 1) +LR_REG_IMM_UPD(int64_t, 2) +#endif + +SR_REG_IMM_UPD(int8_t, 3) +SR_REG_IMM_UPD(int16_t, 0) +SR_REG_IMM_UPD(int32_t, 1) +#if __riscv_xlen == 64 +SR_REG_IMM_UPD(int64_t, 2) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 5 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 8 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c new file mode 100644 index 00000000000..069c66d7ef6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadbb_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LR_REG_IMM_UPD(int8_t, 0) +LR_REG_IMM_UPD(uint8_t, 1) +LR_REG_IMM_UPD(int16_t, 2) +LR_REG_IMM_UPD(uint16_t, 3) +LR_REG_IMM_UPD(int32_t, 0) +#if __riscv_xlen == 64 +LR_REG_IMM_UPD(uint32_t, 1) +LR_REG_IMM_UPD(int64_t, 2) +#endif + +SR_REG_IMM_UPD(int8_t, 3) +SR_REG_IMM_UPD(int16_t, 0) +SR_REG_IMM_UPD(int32_t, 1) +#if __riscv_xlen == 64 +SR_REG_IMM_UPD(int64_t, 2) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 5 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 8 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb.c new file mode 100644 index 00000000000..c9bf1505061 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index-xtheadbb.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadbb_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LR_REG_IMM(int8_t, 0) +/* { dg-final { scan-assembler-times "th.lrb\t\[^\n\r\]*0" 1 } } */ +LR_REG_IMM(uint8_t, 1) +/* { dg-final { scan-assembler-times "th.lrbu\t\[^\n\r\]*1" 1 } } */ +LR_REG_IMM(int16_t, 2) +/* { dg-final { scan-assembler-times "th.lrh\t\[^\n\r\]*2" 1 } } */ +LR_REG_IMM(uint16_t, 3) +/* { dg-final { scan-assembler-times "th.lrhu\t\[^\n\r\]*3" 1 } } */ +LR_REG_IMM(int32_t, 0) +/* { dg-final { scan-assembler-times "th.lrw\t\[^\n\r\]*0" 1 } } */ +#if __riscv_xlen == 64 +LR_REG_IMM(uint32_t, 1) +/* { dg-final { scan-assembler-times "th.lrwu\t\[^\n\r\]*1" 1 { target { rv64 } } } } */ +LR_REG_IMM(int64_t, 2) +/* { dg-final { scan-assembler-times "th.lrd\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +#endif + +SR_REG_IMM(int8_t, 3) +/* { dg-final { scan-assembler-times "th.srb\t\[^\n\r\]*3" 1 } } */ +SR_REG_IMM(int16_t, 0) +/* { dg-final { scan-assembler-times "th.srh\t\[^\n\r\]*0" 1 } } */ +SR_REG_IMM(int32_t, 1) +/* { dg-final { scan-assembler-times "th.srw\t\[^\n\r\]*1" 1 } } */ +#if __riscv_xlen == 64 +SR_REG_IMM(int64_t, 2) +/* { dg-final { scan-assembler-times "th.srd\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index.c new file mode 100644 index 00000000000..3fa0e8fa355 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-index.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LR_REG_IMM(int8_t, 0) +/* { dg-final { scan-assembler-times "th.lrb\t\[^\n\r\]*0" 1 } } */ +LR_REG_IMM(uint8_t, 1) +/* { dg-final { scan-assembler-times "th.lrbu\t\[^\n\r\]*1" 1 } } */ +LR_REG_IMM(int16_t, 2) +/* { dg-final { scan-assembler-times "th.lrh\t\[^\n\r\]*2" 1 } } */ +LR_REG_IMM(uint16_t, 3) +/* { dg-final { scan-assembler-times "th.lrhu\t\[^\n\r\]*3" 1 } } */ +LR_REG_IMM(int32_t, 0) +/* { dg-final { scan-assembler-times "th.lrw\t\[^\n\r\]*0" 1 } } */ +#if __riscv_xlen == 64 +LR_REG_IMM(uint32_t, 1) +/* { dg-final { scan-assembler-times "th.lrwu\t\[^\n\r\]*1" 1 { target { rv64 } } } } */ +LR_REG_IMM(int64_t, 2) +/* { dg-final { scan-assembler-times "th.lrd\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +#endif + +SR_REG_IMM(int8_t, 3) +/* { dg-final { scan-assembler-times "th.srb\t\[^\n\r\]*3" 1 } } */ +SR_REG_IMM(int16_t, 0) +/* { dg-final { scan-assembler-times "th.srh\t\[^\n\r\]*0" 1 } } */ +SR_REG_IMM(int32_t, 1) +/* { dg-final { scan-assembler-times "th.srw\t\[^\n\r\]*1" 1 } } */ +#if __riscv_xlen == 64 +SR_REG_IMM(int64_t, 2) +/* { dg-final { scan-assembler-times "th.srd\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c new file mode 100644 index 00000000000..745a1be8a53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadbb_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +/* We have a simm5 shifted by a imm2. + imm2 | range (simm5 << imm2) + 0 | -16..-1,0..15 + 1 | -32..-2,0..30 + 2 | -64..-4,0..60 + 3 | -128..-8,0..120 */ + +POST_INC_LOAD(int8_t, 1) +/* { dg-final { scan-assembler "th.lbia\[^\n\r\]*1,0" } } */ +PRE_DEC_LOAD(int8_t, 32) +/* { dg-final { scan-assembler "th.lbib\[^\n\r\]*-16,1" } } */ + +POST_DEC_LOAD(uint8_t, 1) +/* { dg-final { scan-assembler "th.lbuia\[^\n\r\]*-1,0" } } */ +PRE_INC_LOAD(uint8_t, 32) +/* { dg-final { scan-assembler "th.lbuib\[^\n\r\]*8,2" } } */ + +POST_INC_LOAD(int16_t, 1) +/* { dg-final { scan-assembler "th.lhia\[^\n\r\]*2,0" } } */ +POST_DEC_LOAD(int16_t, 64) +/* { dg-final { scan-assembler "th.lhia\[^\n\r\]*-16,3" } } */ + +POST_DEC_LOAD(uint16_t, 1) +/* { dg-final { scan-assembler "th.lhuia\[^\n\r\]*-2,0" } } */ +POST_INC_LOAD(uint16_t, 60) +/* { dg-final { scan-assembler "th.lhuia\[^\n\r\]*15,3" } } */ + +POST_INC_LOAD(int32_t, 1) +/* { dg-final { scan-assembler "th.lwia\[^\n\r\]*4,0" } } */ +PRE_DEC_LOAD(int32_t, 32) +/* { dg-final { scan-assembler "th.lwib\[^\n\r\]*-16,3" } } */ + +#if __riscv_xlen == 64 +POST_DEC_LOAD(uint32_t, 1) +/* { dg-final { scan-assembler "th.lwuia\[^\n\r\]*-4,0" { target { rv64 } } } } */ +PRE_INC_LOAD(uint32_t, 15) +/* { dg-final { scan-assembler "th.lwuib\[^\n\r\]*15,2" { target { rv64 } } } } */ + +POST_INC_LOAD(int64_t, 1) +/* { dg-final { scan-assembler "th.ldia\[^\n\r\]*8,0" { target { rv64 } } } } */ +PRE_DEC_LOAD(int64_t, 16) +/* { dg-final { scan-assembler "th.ldib\[^\n\r\]*-16,3" { target { rv64 } } } } */ +#endif + +POST_DEC_STORE(int8_t, 1) +/* { dg-final { scan-assembler "th.sbia\[^\n\r\]*-1,0" } } */ +PRE_INC_STORE(int8_t, 120) +/* { dg-final { scan-assembler "th.sbib\[^\n\r\]*15,3" } } */ + +POST_INC_STORE(int16_t, 1) +/* { dg-final { scan-assembler "th.shia\[^\n\r\]*2,0" } } */ +PRE_DEC_STORE(int16_t, 64) +/* { dg-final { scan-assembler "th.shib\[^\n\r\]*-16,3" } } */ + +POST_DEC_STORE(int32_t, 1) +/* { dg-final { scan-assembler "th.swia\[^\n\r\]*-4,0" } } */ +PRE_INC_STORE(int32_t, 2) +/* { dg-final { scan-assembler "th.swib\[^\n\r\]*8,0" } } */ + +#if __riscv_xlen == 64 +POST_INC_STORE(int64_t, 1) +/* { dg-final { scan-assembler "th.sdia\[^\n\r\]*8,0" { target { rv64 } } } } */ +PRE_DEC_STORE(int64_t, 8) +/* { dg-final { scan-assembler "th.sdib\[^\n\r\]*-16,2" { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "\taddi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c new file mode 100644 index 00000000000..e1ec0bdabd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-modify.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +/* We have a simm5 shifted by a imm2. + imm2 | range (simm5 << imm2) + 0 | -16..-1,0..15 + 1 | -32..-2,0..30 + 2 | -64..-4,0..60 + 3 | -128..-8,0..120 */ + +POST_INC_LOAD(int8_t, 1) +/* { dg-final { scan-assembler "th.lbia\[^\n\r\]*1,0" } } */ +PRE_DEC_LOAD(int8_t, 32) +/* { dg-final { scan-assembler "th.lbib\[^\n\r\]*-16,1" } } */ + +POST_DEC_LOAD(uint8_t, 1) +/* { dg-final { scan-assembler "th.lbuia\[^\n\r\]*-1,0" } } */ +PRE_INC_LOAD(uint8_t, 32) +/* { dg-final { scan-assembler "th.lbuib\[^\n\r\]*8,2" } } */ + +POST_INC_LOAD(int16_t, 1) +/* { dg-final { scan-assembler "th.lhia\[^\n\r\]*2,0" } } */ +POST_DEC_LOAD(int16_t, 64) +/* { dg-final { scan-assembler "th.lhia\[^\n\r\]*-16,3" } } */ + +POST_DEC_LOAD(uint16_t, 1) +/* { dg-final { scan-assembler "th.lhuia\[^\n\r\]*-2,0" } } */ +POST_INC_LOAD(uint16_t, 60) +/* { dg-final { scan-assembler "th.lhuia\[^\n\r\]*15,3" } } */ + +POST_INC_LOAD(int32_t, 1) +/* { dg-final { scan-assembler "th.lwia\[^\n\r\]*4,0" } } */ +PRE_DEC_LOAD(int32_t, 32) +/* { dg-final { scan-assembler "th.lwib\[^\n\r\]*-16,3" } } */ + +#if __riscv_xlen == 64 +POST_DEC_LOAD(uint32_t, 1) +/* { dg-final { scan-assembler "th.lwuia\[^\n\r\]*-4,0" { target { rv64 } } } } */ +PRE_INC_LOAD(uint32_t, 15) +/* { dg-final { scan-assembler "th.lwuib\[^\n\r\]*15,2" { target { rv64 } } } } */ + +POST_INC_LOAD(int64_t, 1) +/* { dg-final { scan-assembler "th.ldia\[^\n\r\]*8,0" { target { rv64 } } } } */ +PRE_DEC_LOAD(int64_t, 16) +/* { dg-final { scan-assembler "th.ldib\[^\n\r\]*-16,3" { target { rv64 } } } } */ +#endif + +POST_DEC_STORE(int8_t, 1) +/* { dg-final { scan-assembler "th.sbia\[^\n\r\]*-1,0" } } */ +PRE_INC_STORE(int8_t, 120) +/* { dg-final { scan-assembler "th.sbib\[^\n\r\]*15,3" } } */ + +POST_INC_STORE(int16_t, 1) +/* { dg-final { scan-assembler "th.shia\[^\n\r\]*2,0" } } */ +PRE_DEC_STORE(int16_t, 64) +/* { dg-final { scan-assembler "th.shib\[^\n\r\]*-16,3" } } */ + +POST_DEC_STORE(int32_t, 1) +/* { dg-final { scan-assembler "th.swia\[^\n\r\]*-4,0" } } */ +PRE_INC_STORE(int32_t, 2) +/* { dg-final { scan-assembler "th.swib\[^\n\r\]*8,0" } } */ + +#if __riscv_xlen == 64 +POST_INC_STORE(int64_t, 1) +/* { dg-final { scan-assembler "th.sdia\[^\n\r\]*8,0" { target { rv64 } } } } */ +PRE_DEC_STORE(int64_t, 8) +/* { dg-final { scan-assembler "th.sdib\[^\n\r\]*-16,2" { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "\taddi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-update.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-update.c new file mode 100644 index 00000000000..c46d7d1474d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-update.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LRU_REG_IMM_UPD(int8_t, 0) +LRU_REG_IMM_UPD(uint8_t, 1) +LRU_REG_IMM_UPD(int16_t, 2) +LRU_REG_IMM_UPD(uint16_t, 3) +LRU_REG_IMM_UPD(int32_t, 0) +#if __riscv_xlen == 64 +LRU_REG_IMM_UPD(uint32_t, 1) +LRU_REG_IMM_UPD(int64_t, 2) +#endif + +SRU_REG_IMM_UPD(int8_t, 3) +SRU_REG_IMM_UPD(int16_t, 0) +SRU_REG_IMM_UPD(int32_t, 1) +#if __riscv_xlen == 64 +SRU_REG_IMM_UPD(int64_t, 2) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 5 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 8 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c new file mode 100644 index 00000000000..dc69f228371 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb-update.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadbb_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LRU_REG_IMM_UPD(int8_t, 0) +LRU_REG_IMM_UPD(uint8_t, 1) +LRU_REG_IMM_UPD(int16_t, 2) +LRU_REG_IMM_UPD(uint16_t, 3) +LRU_REG_IMM_UPD(int32_t, 0) +#if __riscv_xlen == 64 +LRU_REG_IMM_UPD(uint32_t, 1) +LRU_REG_IMM_UPD(int64_t, 2) +#endif + +SRU_REG_IMM_UPD(int8_t, 3) +SRU_REG_IMM_UPD(int16_t, 0) +SRU_REG_IMM_UPD(int32_t, 1) +#if __riscv_xlen == 64 +SRU_REG_IMM_UPD(int64_t, 2) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 5 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 8 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c new file mode 100644 index 00000000000..6116762b839 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex-xtheadbb.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadbb_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LRU_REG_IMM(int8_t, 0) +/* { dg-final { scan-assembler-times "th.lurb\t\[^\n\r\]*0" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrb\t\[^\n\r\]*0" 1 { target { rv32 } } } } */ +LRU_REG_IMM(uint8_t, 1) +/* { dg-final { scan-assembler-times "th.lurbu\t\[^\n\r\]*1" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrbu\t\[^\n\r\]*1" 1 { target { rv32 } } } } */ +LRU_REG_IMM(int16_t, 2) +/* { dg-final { scan-assembler-times "th.lurh\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrh\t\[^\n\r\]*2" 1 { target { rv32 } } } } */ +LRU_REG_IMM(uint16_t, 3) +/* { dg-final { scan-assembler-times "th.lurhu\t\[^\n\r\]*3" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrhu\t\[^\n\r\]*3" 1 { target { rv32 } } } } */ +LRU_REG_IMM(int32_t, 0) +/* { dg-final { scan-assembler-times "th.lurw\t\[^\n\r\]*0" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrw\t\[^\n\r\]*0" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +LRU_REG_IMM(uint32_t, 1) +/* { dg-final { scan-assembler-times "th.lurwu\t\[^\n\r\]*1" 1 { target { rv64 } } } } */ +LRU_REG_IMM(int64_t, 2) +/* { dg-final { scan-assembler-times "th.lurd\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +#endif + +SRU_REG_IMM(int8_t, 3) +/* { dg-final { scan-assembler-times "th.surb\t\[^\n\r\]*3" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.srb\t\[^\n\r\]*3" 1 { target { rv32 } } } } */ +SRU_REG_IMM(int16_t, 0) +/* { dg-final { scan-assembler-times "th.surh\t\[^\n\r\]*0" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.srh\t\[^\n\r\]*0" 1 { target { rv32 } } } } */ +SRU_REG_IMM(int32_t, 1) +/* { dg-final { scan-assembler-times "th.surw\t\[^\n\r\]*1" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.srw\t\[^\n\r\]*1" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +SRU_REG_IMM(int64_t, 2) +/* { dg-final { scan-assembler-times "th.surd\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex.c new file mode 100644 index 00000000000..b2ff4542347 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-uindex.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadmemidx" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +LRU_REG_IMM(int8_t, 0) +/* { dg-final { scan-assembler-times "th.lurb\t\[^\n\r\]*0" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrb\t\[^\n\r\]*0" 1 { target { rv32 } } } } */ +LRU_REG_IMM(uint8_t, 1) +/* { dg-final { scan-assembler-times "th.lurbu\t\[^\n\r\]*1" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrbu\t\[^\n\r\]*1" 1 { target { rv32 } } } } */ +LRU_REG_IMM(int16_t, 2) +/* { dg-final { scan-assembler-times "th.lurh\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrh\t\[^\n\r\]*2" 1 { target { rv32 } } } } */ +LRU_REG_IMM(uint16_t, 3) +/* { dg-final { scan-assembler-times "th.lurhu\t\[^\n\r\]*3" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrhu\t\[^\n\r\]*3" 1 { target { rv32 } } } } */ +LRU_REG_IMM(int32_t, 0) +/* { dg-final { scan-assembler-times "th.lurw\t\[^\n\r\]*0" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.lrw\t\[^\n\r\]*0" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +LRU_REG_IMM(uint32_t, 1) +/* { dg-final { scan-assembler-times "th.lurwu\t\[^\n\r\]*1" 1 { target { rv64 } } } } */ +LRU_REG_IMM(int64_t, 2) +/* { dg-final { scan-assembler-times "th.lurd\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +#endif + +SRU_REG_IMM(int8_t, 3) +/* { dg-final { scan-assembler-times "th.surb\t\[^\n\r\]*3" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.srb\t\[^\n\r\]*3" 1 { target { rv32 } } } } */ +SRU_REG_IMM(int16_t, 0) +/* { dg-final { scan-assembler-times "th.surh\t\[^\n\r\]*0" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.srh\t\[^\n\r\]*0" 1 { target { rv32 } } } } */ +SRU_REG_IMM(int32_t, 1) +/* { dg-final { scan-assembler-times "th.surw\t\[^\n\r\]*1" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.srw\t\[^\n\r\]*1" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +SRU_REG_IMM(int64_t, 2) +/* { dg-final { scan-assembler-times "th.surd\t\[^\n\r\]*2" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ From patchwork Fri Apr 28 06:23:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 88461 Return-Path: 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id e14-20020a170906504e00b0094a90d3e385sm10556730ejk.30.2023.04.27.23.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:23:18 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 11/11] riscv: thead: Add support for the XTheadFMemIdx ISA extension Date: Fri, 28 Apr 2023 08:23:14 +0200 Message-Id: <20230428062314.2995571-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428062314.2995571-1-christoph.muellner@vrull.eu> References: <20230428062314.2995571-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764400102224939268?= X-GMAIL-MSGID: =?utf-8?q?1764400102224939268?= From: Christoph Müllner The XTheadFMemIdx ISA extension provides additional load and store instructions for floating-point registers with new addressing modes. The following memory accesses types are supported: * ftype = [w,d] (single-precision, double-precision) The following addressing modes are supported: * register offset with additional immediate offset (4 instructions): flr, fsr * zero-extended register offset with additional immediate offset (4 instructions): flur, fsur These addressing modes are also part of the similar XTheadMemIdx ISA extension support, whose code is reused and extended to support floating-point registers. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_index_reg_class): Also allow for XTheadFMemIdx. (riscv_regno_ok_for_index_p): Likewise. * config/riscv/thead-peephole.md (TARGET_64BIT): Generalize peepholes for XTheadFMemIdx. * config/riscv/thead.cc (is_fmemidx_mode): New function. (th_memidx_classify_address_index): Add support for XTheadFMemIdx. (th_fmemidx_output_index): New function. (th_output_move): Add support for XTheadFMemIdx. * config/riscv/thead.md (*th_fmemidx_movsf_hardfloat): New INSN. (*th_fmemidx_movdf_hardfloat_rv64): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadmemidx-helpers.h: Add helpers for XTheadMemFIdx. * gcc.target/riscv/xtheadfmemidx-index-update.c: New test. * gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c: New test. * gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c: New test. * gcc.target/riscv/xtheadfmemidx-index.c: New test. * gcc.target/riscv/xtheadfmemidx-uindex-update.c: New test. * gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c: New test. * gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c: New test. * gcc.target/riscv/xtheadfmemidx-uindex.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.cc | 4 +- gcc/config/riscv/thead-peephole.md | 24 ++++--- gcc/config/riscv/thead.cc | 68 +++++++++++++++++- gcc/config/riscv/thead.md | 22 ++++++ .../riscv/xtheadfmemidx-index-update.c | 20 ++++++ .../xtheadfmemidx-index-xtheadbb-update.c | 20 ++++++ .../riscv/xtheadfmemidx-index-xtheadbb.c | 22 ++++++ .../gcc.target/riscv/xtheadfmemidx-index.c | 22 ++++++ .../riscv/xtheadfmemidx-uindex-update.c | 20 ++++++ .../xtheadfmemidx-uindex-xtheadbb-update.c | 20 ++++++ .../riscv/xtheadfmemidx-uindex-xtheadbb.c | 24 +++++++ .../gcc.target/riscv/xtheadfmemidx-uindex.c | 25 +++++++ .../gcc.target/riscv/xtheadmemidx-helpers.h | 70 +++++++++++++++++++ 13 files changed, 348 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1691ecf3a94..d1e08974023 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -834,7 +834,7 @@ riscv_regno_mode_ok_for_base_p (int regno, enum reg_class riscv_index_reg_class () { - if (TARGET_XTHEADMEMIDX) + if (TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) return GR_REGS; return NO_REGS; @@ -847,7 +847,7 @@ riscv_index_reg_class () int riscv_regno_ok_for_index_p (int regno) { - if (TARGET_XTHEADMEMIDX) + if (TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) return riscv_regno_mode_ok_for_base_p (regno, VOIDmode, 1); return 0; diff --git a/gcc/config/riscv/thead-peephole.md b/gcc/config/riscv/thead-peephole.md index 2a4c734a220..e3de9b8e8d3 100644 --- a/gcc/config/riscv/thead-peephole.md +++ b/gcc/config/riscv/thead-peephole.md @@ -73,11 +73,15 @@ (define_peephole2 th_mempair_order_operands (operands, true, SImode); }) -;; All modes that are supported by XTheadMemIdx -(define_mode_iterator TH_M_ANY [QI HI SI (DI "TARGET_64BIT")]) +;; All modes that are supported by XTheadMemIdx and XTheadFMemIdx +(define_mode_iterator TH_M_ANY [QI HI SI (DI "TARGET_64BIT") + (SF "TARGET_HARD_FLOAT") + (DF "TARGET_DOUBLE_FLOAT")]) -;; All non-extension modes that are supported by XTheadMemIdx -(define_mode_iterator TH_M_NOEXT [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) +;; All non-extension modes that are supported by XTheadMemIdx and XTheadFMemIdx +(define_mode_iterator TH_M_NOEXT [(SI "!TARGET_64BIT") (DI "TARGET_64BIT") + (SF "TARGET_HARD_FLOAT") + (DF "TARGET_DOUBLE_FLOAT")]) ;; XTheadMemIdx overview: ;; All peephole passes attempt to improve the operand utilization of @@ -125,7 +129,7 @@ (define_peephole2 (mem:TH_M_NOEXT (plus:X (match_dup 0) (match_operand:X 4 "register_operand" ""))))] - "TARGET_XTHEADMEMIDX + "(TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) && peep2_reg_dead_p (2, operands[0]) && IN_RANGE (INTVAL (operands[2]), 0, 3)" [(set (match_dup 3) @@ -161,7 +165,7 @@ (define_peephole2 (match_dup 0) (match_operand:X 4 "register_operand" ""))) (match_operand:TH_M_ANY 3 "register_operand" ""))] - "TARGET_XTHEADMEMIDX + "(TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) && peep2_reg_dead_p (2, operands[0]) && IN_RANGE (INTVAL (operands[2]), 0, 3)" [(set (mem:TH_M_ANY (plus:X @@ -180,7 +184,7 @@ (define_peephole2 (mem:TH_M_NOEXT (plus:DI (match_dup 3) (match_operand:DI 6 "register_operand" ""))))] - "TARGET_64BIT && TARGET_XTHEADMEMIDX + "TARGET_64BIT && (TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[3]) && IN_RANGE (INTVAL (operands[4]), 29, 32)" @@ -226,7 +230,7 @@ (define_peephole2 (match_dup 3) (match_operand:DI 6 "register_operand" ""))) (match_operand:TH_M_ANY 5 "register_operand" ""))] - "TARGET_64BIT && TARGET_XTHEADMEMIDX + "TARGET_64BIT && (TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[3]) && IN_RANGE (INTVAL (operands[4]), 29, 32)" @@ -247,7 +251,7 @@ (define_peephole2 (mem:TH_M_NOEXT (plus:DI (match_dup 0) (match_operand:DI 4 "register_operand" ""))))] - "TARGET_64BIT && TARGET_XTHEADMEMIDX + "TARGET_64BIT && (TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) && peep2_reg_dead_p (2, operands[0])" [(set (match_dup 3) (mem:TH_M_NOEXT (plus:DI @@ -279,7 +283,7 @@ (define_peephole2 (match_dup 0) (match_operand:DI 4 "register_operand" ""))) (match_operand:TH_M_ANY 3 "register_operand" ""))] - "TARGET_64BIT && TARGET_XTHEADMEMIDX + "TARGET_64BIT && (TARGET_XTHEADMEMIDX || TARGET_XTHEADFMEMIDX) && peep2_reg_dead_p (2, operands[0])" [(set (mem:TH_M_ANY (plus:DI (match_dup 4) diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index bfe035250af..3671f1bf9ac 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -591,6 +591,21 @@ is_memidx_mode (machine_mode mode) return false; } +static bool +is_fmemidx_mode (machine_mode mode) +{ + if (!TARGET_HARD_FLOAT) + return false; + + if (mode == SFmode) + return true; + + if (mode == DFmode && TARGET_DOUBLE_FLOAT) + return true; + + return false; +} + /* Return true if X is a valid address for T-Head's memory addressing modes with scaled register offsets for machine mode MODE. If it is, fill in INFO appropriately (if non-NULL). @@ -601,7 +616,8 @@ th_memidx_classify_address_index (struct riscv_address_info *info, rtx x, machine_mode mode, bool strict_p) { /* Ensure that the mode is supported. */ - if (!(TARGET_XTHEADMEMIDX && is_memidx_mode (mode))) + if (!(TARGET_XTHEADMEMIDX && is_memidx_mode (mode)) + && !(TARGET_XTHEADFMEMIDX && is_fmemidx_mode (mode))) return false; if (GET_CODE (x) != PLUS) @@ -757,6 +773,40 @@ th_memidx_output_index (rtx x, machine_mode mode, bool load) return buf; } +/* Provide a buffer for a th.flX/th.fluX/th.fsX/th.fsuX instruction + for the given MODE. If LOAD is true, a load instruction will be + provided (otherwise, a store instruction). If X is not suitable + return NULL. */ + +static const char * +th_fmemidx_output_index (rtx x, machine_mode mode, bool load) +{ + struct riscv_address_info info; + static char buf[128] = {0}; + + /* Validate x. */ + if (!th_memidx_classify_address_index (&info, x, mode, false)) + return NULL; + + int index = exact_log2 (GET_MODE_SIZE (mode).to_constant ()) - 2; + bool uindex = info.type == ADDRESS_REG_UREG; + + const char *const insn[][2] = { + { + "th.fs%srw\t%%z1,%%0", + "th.fs%srd\t%%z1,%%0" + }, + { + "th.fl%srw\t%%0,%%1", + "th.fl%srd\t%%0,%%1" + } + }; + + snprintf (buf, sizeof (buf), insn[load][index], uindex ? "u" : ""); + + return buf; +} + /* Return true if X is a valid address for T-Head's memory addressing modes for machine mode MODE. If it is, fill in INFO appropriately (if non-NULL). If STRICT_P is true then REG_OK_STRICT is in effect. */ @@ -811,6 +861,14 @@ th_output_move (rtx dest, rtx src) if ((insn = th_memidx_output_modify (x, mode, true))) return insn; } + else if (dest_code == REG && FP_REG_P (REGNO (dest)) && src_code == MEM) + { + rtx x = XEXP (src, 0); + mode = GET_MODE (src); + + if ((insn = th_fmemidx_output_index (x, mode, true))) + return insn; + } else if (((src_code == REG && GP_REG_P (REGNO (src))) || (src == CONST0_RTX (mode))) && dest_code == MEM) @@ -824,6 +882,14 @@ th_output_move (rtx dest, rtx src) if ((insn = th_memidx_output_modify (x, mode, false))) return insn; } + else if (src_code == REG && FP_REG_P (REGNO (src)) && dest_code == MEM) + { + rtx x = XEXP (dest, 0); + mode = GET_MODE (dest); + + if ((insn = th_fmemidx_output_index (x, mode, false))) + return insn; + } return NULL; } diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 5536500e4ff..e8759e1b77d 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -555,4 +555,26 @@ (define_insn "*th_memidx_bb_extendqi2" [(set_attr "move_type" "shift_shift,load,load,load,load,load") (set_attr "mode" "")]) +;; XTheadFMemIdx + +(define_insn "*th_fmemidx_movsf_hardfloat" + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,th_m_mir,f,th_m_miu") + (match_operand:SF 1 "move_operand" " th_m_mir,f,th_m_miu,f"))] + "TARGET_HARD_FLOAT && TARGET_XTHEADFMEMIDX + && (register_operand (operands[0], SFmode) + || reg_or_0_operand (operands[1], SFmode))" + { return riscv_output_move (operands[0], operands[1]); } + [(set_attr "move_type" "fpload,fpstore,fpload,fpstore") + (set_attr "mode" "SF")]) + +(define_insn "*th_fmemidx_movdf_hardfloat_rv64" + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,th_m_mir,f,th_m_miu") + (match_operand:DF 1 "move_operand" " th_m_mir,f,th_m_miu,f"))] + "TARGET_64BIT && TARGET_DOUBLE_FLOAT && TARGET_XTHEADFMEMIDX + && (register_operand (operands[0], DFmode) + || reg_or_0_operand (operands[1], DFmode))" + { return riscv_output_move (operands[0], operands[1]); } + [(set_attr "move_type" "fpload,fpstore,fpload,fpstore") + (set_attr "mode" "DF")]) + (include "thead-peephole.md") diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c new file mode 100644 index 00000000000..cc97fd2f786 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-update.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +FLR_REG_IMM_UPD(float, 0) +#if __riscv_xlen == 64 +FLR_REG_IMM_UPD(double, 2) +#endif + +FSR_REG_IMM_UPD(float, 1) +#if __riscv_xlen == 64 +FSR_REG_IMM_UPD(double, 3) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 3 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c new file mode 100644 index 00000000000..3b3a7fbdd4a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadbb_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +FLR_REG_IMM_UPD(float, 0) +#if __riscv_xlen == 64 +FLR_REG_IMM_UPD(double, 2) +#endif + +FSR_REG_IMM_UPD(float, 1) +#if __riscv_xlen == 64 +FSR_REG_IMM_UPD(double, 3) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 3 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c new file mode 100644 index 00000000000..55d1f651bd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadbb_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +FLR_REG_IMM(float, 0) +/* { dg-final { scan-assembler-times "th.flrw\t\[^\n\r\]*0\[\n\r\]" 1 } } */ +#if __riscv_xlen == 64 +FLR_REG_IMM(double, 2) +/* { dg-final { scan-assembler-times "th.flrd\t\[^\n\r\]*2\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +FSR_REG_IMM(float, 1) +/* { dg-final { scan-assembler-times "th.fsrw\t\[^\n\r\]*1\[\n\r\]" 1 } } */ +#if __riscv_xlen == 64 +FSR_REG_IMM(double, 3) +/* { dg-final { scan-assembler-times "th.fsrd\t\[^\n\r\]*3\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c new file mode 100644 index 00000000000..b92f4adc0b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-index.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +FLR_REG_IMM(float, 0) +/* { dg-final { scan-assembler-times "th.flrw\t\[^\n\r\]*0\[\n\r\]" 1 } } */ +#if __riscv_xlen == 64 +FLR_REG_IMM(double, 2) +/* { dg-final { scan-assembler-times "th.flrd\t\[^\n\r\]*2\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +FSR_REG_IMM(float, 1) +/* { dg-final { scan-assembler-times "th.fsrw\t\[^\n\r\]*1\[\n\r\]" 1 } } */ +#if __riscv_xlen == 64 +FSR_REG_IMM(double, 3) +/* { dg-final { scan-assembler-times "th.fsrd\t\[^\n\r\]*3\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c new file mode 100644 index 00000000000..075cefdb971 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-update.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +FLUR_REG_IMM_UPD(float, 0) +#if __riscv_xlen == 64 +FLUR_REG_IMM_UPD(double, 2) +#endif + +FSUR_REG_IMM_UPD(float, 1) +#if __riscv_xlen == 64 +FSUR_REG_IMM_UPD(double, 3) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 3 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c new file mode 100644 index 00000000000..a677e82768a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadbb_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +FLUR_REG_IMM_UPD(float, 0) +#if __riscv_xlen == 64 +FLUR_REG_IMM_UPD(double, 2) +#endif + +FSUR_REG_IMM_UPD(float, 1) +#if __riscv_xlen == 64 +FSUR_REG_IMM_UPD(double, 3) +#endif + +/* If the shifted value is used later, we cannot eliminate it. */ +/* { dg-final { scan-assembler-times "slli" 1 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "slli" 3 { target { rv64 } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c new file mode 100644 index 00000000000..3377c26963b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadbb_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadbb_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +FLUR_REG_IMM(float, 0) +/* { dg-final { scan-assembler-times "th.flurw\t\[^\n\r\]*0\[\n\r\]" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.flrw\t\[^\n\r\]*0\[\n\r\]" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +FLUR_REG_IMM(double, 2) +/* { dg-final { scan-assembler-times "th.flurd\t\[^\n\r\]*2\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +FSUR_REG_IMM(float, 1) +/* { dg-final { scan-assembler-times "th.fsurw\t\[^\n\r\]*1\[\n\r\]" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.fsrw\t\[^\n\r\]*1\[\n\r\]" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +FSUR_REG_IMM(double, 3) +/* { dg-final { scan-assembler-times "th.fsurd\t\[^\n\r\]*3\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c new file mode 100644 index 00000000000..0c84a651eb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_xtheadfmemidx" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_xtheadfmemidx -mabi=ilp32f" { target { rv32 } } } */ + +#include "xtheadmemidx-helpers.h" + +FLUR_REG_IMM(float, 0) +/* { dg-final { scan-assembler-times "th.flurw\t\[^\n\r\]*0\[\n\r\]" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.flrw\t\[^\n\r\]*0\[\n\r\]" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +FLUR_REG_IMM(double, 2) +/* { dg-final { scan-assembler-times "th.flurd\t\[^\n\r\]*2\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +FSUR_REG_IMM(float, 1) +/* { dg-final { scan-assembler-times "th.fsurw\t\[^\n\r\]*1\[\n\r\]" 1 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.fsrw\t\[^\n\r\]*1\[\n\r\]" 1 { target { rv32 } } } } */ +#if __riscv_xlen == 64 +FSUR_REG_IMM(double, 3) +/* { dg-final { scan-assembler-times "th.fsurd\t\[^\n\r\]*3\[\n\r\]" 1 { target { rv64 } } } } */ +#endif + +/* { dg-final { scan-assembler-not "slli" } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h index a97f08c5cc1..62c4f67f968 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx-helpers.h @@ -149,4 +149,74 @@ *rs2 = t; \ } +#define FLR_REG_IMM(T, IMM) \ + T \ + flr_reg_imm_ ## T ## _ ## IMM (intX_t rs1, intX_t rs2) \ + { \ + return *(T*)(rs1 + (rs2 << IMM)); \ + } + +#define FSR_REG_IMM(T, IMM) \ + void \ + sr_reg_imm_ ## T ## _ ## IMM (intX_t rs1, intX_t rs2, T val) \ + { \ + *(T*)(rs1 + (rs2 << IMM)) = val; \ + } + +#define FLR_REG_IMM_UPD(T, IMM) \ + T \ + flr_reg_imm_upd_ ## T ## _ ## IMM (intX_t rs1, intX_t *rs2) \ + { \ + intX_t addr = rs1 + (*rs2 << IMM); \ + T val = *(T*)addr; \ + *rs2 = addr; \ + return val; \ + } + +#define FSR_REG_IMM_UPD(T, IMM) \ + void \ + sr_reg_imm_upd_ ## T ## _ ## IMM (intX_t rs1, intX_t *rs2, T val) \ + { \ + intX_t addr = rs1 + (*rs2 << IMM); \ + *(T*)addr = val; \ + *rs2 = addr; \ + } + +#define FLUR_REG_IMM(T, IMM) \ + T \ + flr_reg_imm_ ## T ## _ ## IMM (intX_t rs1, intX_t rs2) \ + { \ + rs2 = (uint32_t)rs2; \ + return *(T*)(rs1 + (rs2 << IMM)); \ + } + +#define FSUR_REG_IMM(T, IMM) \ + void \ + sr_reg_imm_ ## T ## _ ## IMM (intX_t rs1, intX_t rs2, T val) \ + { \ + rs2 = (uint32_t)rs2; \ + *(T*)(rs1 + (rs2 << IMM)) = val; \ + } + +#define FLUR_REG_IMM_UPD(T, IMM) \ + T \ + flr_reg_imm_upd_ ## T ## _ ## IMM (intX_t rs1, intX_t *rs2) \ + { \ + intX_t rs2_32 = (uint32_t)*rs2; \ + intX_t addr = rs1 + (rs2_32 << IMM); \ + T val = *(T*)addr; \ + *rs2 = addr; \ + return val; \ + } + +#define FSUR_REG_IMM_UPD(T, IMM) \ + void \ + sr_reg_imm_upd_ ## T ## _ ## IMM (intX_t rs1, intX_t *rs2, T val) \ + { \ + intX_t rs2_32 = (uint32_t)*rs2; \ + intX_t addr = rs1 + (rs2_32 << IMM); \ + *(T*)addr = val; \ + *rs2 = addr; \ + } + #endif /* XTHEADMEMIDX_HELPERS_H */