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Thu, 27 Apr 2023 09:24:09 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 01/11] RISC-V: Eliminate SYNC memory models Date: Thu, 27 Apr 2023 09:22:51 -0700 Message-Id: <20230427162301.1151333-2-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347355894421195?= X-GMAIL-MSGID: =?utf-8?q?1764347355894421195?= Remove references to MEMMODEL_SYNC_* models by converting via memmodel_base(). 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and sanitize memmodel input with memmodel_base. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1529855a2b4..02eb5125ac1 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4299,14 +4299,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: return true; case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: case MEMMODEL_RELAXED: return false; @@ -4325,14 +4322,11 @@ riscv_memmodel_needs_release_fence (enum memmodel model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: return true; case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: case MEMMODEL_RELAXED: return false; @@ -4371,6 +4365,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) } machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); + const enum memmodel model = memmodel_base (INTVAL (op)); switch (letter) { @@ -4508,12 +4503,12 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); break; case 'F': - if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_release_fence (model)) fputs ("fence iorw,ow; ", file); break; From patchwork Thu Apr 27 16:22:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 88314 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp390287vqo; Thu, 27 Apr 2023 09:29:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6vR0BcSv9qvlN55UHasbfUgMmGUloi3eNe3Q1avRfIOaJ3CYMpNo/++pZS7DFWNGWlP4nY X-Received: by 2002:a17:906:99c5:b0:94e:9a73:1637 with SMTP id s5-20020a17090699c500b0094e9a731637mr2160002ejn.75.1682612945324; Thu, 27 Apr 2023 09:29:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682612945; cv=none; d=google.com; s=arc-20160816; b=qzipv5aBPLPB/x5poGOt5RFfxxsEo40dD1T/yQSxyyKeYdlLOyfjV4aaegDNKjzL1N Y6Md0c+fmWO3+Y8tmhDwAe7u6pS5XI4pezczwCBMHK2Wcri/kTNRLii52TnLN1DKOCpt Cpex9+jZdval9iEIQmRaEgLBYHJzaHIpUeCs4NIgemDcQYsaVu6644JFGv9J97hlLlUy lX4IwoO2mlu6HBS251yR+vJAGkf9u+sGfUL9i5AeAGZWlh2/YCzq/wUvsOkDDji1QW12 hJsjctyH7fZbxIlMqsPAfl3lA/d/bDz2CpmJOr0b2cBU6VXG7HLKcavO6KxENLO9veSU vLNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=GpkEHnwd8AiRKPTc0a347tmJp8ty3YVj6SX6sNF0Z/Y=; b=EGCak6g30WcuMWKd+VuOack9upwJ51ZOgAFfIvZJPsYecmk34yC4BD3oz1qkunVLIu AZu+bCS/T5V5qp2me/61di2j0odtDB84JGFnSt75mFDpz7FmrPBm0XdjYDS7pHaGEkdu rmmR8G1EUFa2T5/Jh2Mk8qfTF6Up7MMjbg0Wr45rY0OYFXcgqyo8jR6B+JhE/hqBzPPL 5kaBH2Bqv+2riur1FB2iQNBfWIHainb9oGIEloW/FpjsDU6RZ4mAVViIlBYBkrRmzWrD Y6naaPRrxW4wx/C27C9plJzVWWWQVAoy++nU0lMOnXsV6XXfYKFmMBRTSNiXXeM2Txov Hzhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=p3gTODaG; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Thu, 27 Apr 2023 09:24:11 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 02/11] RISC-V: Enforce Libatomic LR/SC SEQ_CST Date: Thu, 27 Apr 2023 09:22:52 -0700 Message-Id: <20230427162301.1151333-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347551646325784?= X-GMAIL-MSGID: =?utf-8?q?1764347551646325784?= Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill libgcc/ChangeLog: * config/riscv/atomic.c: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pairs. Signed-off-by: Patrick O'Neill --- libgcc/config/riscv/atomic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c index 573d163ea04..bd2b033132b 100644 --- a/libgcc/config/riscv/atomic.c +++ b/libgcc/config/riscv/atomic.c @@ -41,7 +41,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1, tmp2; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ #insn " %[tmp1], %[old], %[value]\n\t" \ invert \ "and %[tmp1], %[tmp1], %[mask]\n\t" \ @@ -75,7 +75,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ "and %[tmp1], %[old], %[mask]\n\t" \ "bne %[tmp1], %[o], 1f\n\t" \ "and %[tmp1], %[old], %[not_mask]\n\t" \ From patchwork Thu Apr 27 16:22:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 88317 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp391336vqo; Thu, 27 Apr 2023 09:30:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5+s4AtcZwpZMz9tcEaDkziJvjgv3cFrVFQmjezj9GgXJNiOzdMnB+Ue73XvTmamPK1eFlC X-Received: by 2002:a05:6402:1648:b0:505:8f4:7412 with SMTP id s8-20020a056402164800b0050508f47412mr2108345edx.10.1682613052955; Thu, 27 Apr 2023 09:30:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682613052; cv=none; d=google.com; s=arc-20160816; b=TRCvL7ZRNl60yAhyo9CcXCGDp5CnfLYUEuR/5tqQ5Cjd8Tvu0sxErDG422XGLAI6YP HsL9Mtgt+1OFtkvt8nhuSELps/Z4Soth/aayNHpKC9+QJ1UajVV1HpqRu1cICZRbwKwo ddxm4xMB8nXNHvW3bIKZ88A5GdGFFf/zWcofBqsdYVHDEO+k+Ry88xjSm1sCt/WIwyr6 mqvWTjlNuF4cq/HFb+4h0cdlxk32dMSwrQDz9xEzhp2cfdLJzd94MwR8UV4yCDskdduy wgD38ZLnu6y3jGp34EOeftfpNgmlSvXo5Wm9BPLS7lKtJmwysn/a7UphjmUi+0dInBDP AKMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=i9Bs2zCAlDDlyeMB7GO35vaNTrSB4ULe6R2VR6cHvtY=; b=WQTGHUHaNxayEuWpmdzN20KWfERtEQCh4ZFFG10AtTKNBQbHaOcI4z/BIE3lYE9ZH2 fjG+83yFJob1djC7o5DEmHjMlLjrxIm5QGXtqZ+2qpgoCz7LmpOYuJTKRUPzNWrBTFFk YyBw8Mk0wviSw2AWxampSZbI4Ufz7amPf9zwBh94atWT4NJCcoid1Y+z49X+bTJTFyjv NI0N1L0SvhXXPttmuDtgyS0ylTBUcWgBPycsjxx830zvdno/x25Q+/Srhqt5kUUHh8I+ UyqfLfkw1FPD+dxexTIkqqpCraUlxUjh8DBa1/E+xhBmRfXsut/4LkpzZc42J+gb5rgF s4RA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=gV5+XA8z; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Thu, 27 Apr 2023 09:24:12 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 03/11] RISC-V: Enforce subword atomic LR/SC SEQ_CST Date: Thu, 27 Apr 2023 09:22:53 -0700 Message-Id: <20230427162301.1151333-4-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347664640978684?= X-GMAIL-MSGID: =?utf-8?q?1764347664640978684?= Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/sync.md: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pairs. Signed-off-by: Patrick O'Neill --- v5 Changelog: * Add this patch to address the added inline subword atomic sequences. --- gcc/config/riscv/sync.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 19274528262..0c83ef04607 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -109,7 +109,7 @@ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aq\t%0, %1\;" + "lr.w.aqrl\t%0, %1\;" "\t%5, %0, %2\;" "and\t%5, %5, %3\;" "and\t%6, %0, %4\;" @@ -173,7 +173,7 @@ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aq\t%0, %1\;" + "lr.w.aqrl\t%0, %1\;" "and\t%5, %0, %2\;" "not\t%5, %5\;" "and\t%5, %5, %3\;" @@ -278,7 +278,7 @@ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aq\t%0, %1\;" + "lr.w.aqrl\t%0, %1\;" "and\t%4, %0, %3\;" "or\t%4, %4, %2\;" "sc.w.rl\t%4, %4, %1\;" @@ -443,7 +443,7 @@ "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aq\t%0, %1\;" + "lr.w.aqrl\t%0, %1\;" "and\t%6, %0, %4\;" "bne\t%6, %z2, 1f\;" "and\t%6, %0, %5\;" From patchwork Thu Apr 27 16:22:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 88310 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp389002vqo; Thu, 27 Apr 2023 09:26:34 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6U6XENlrIsRDQWZ6PNgZhVPT6YeFS/HukTvWWOUlphhFoky6AcStpU07hh2jy/D/UDoiLi X-Received: by 2002:a50:fc08:0:b0:506:87fd:7c77 with SMTP id i8-20020a50fc08000000b0050687fd7c77mr2323226edr.8.1682612794412; Thu, 27 Apr 2023 09:26:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682612794; cv=none; d=google.com; s=arc-20160816; b=uKj71ap3UJArtexwQSL3oLRW6MCo9hH3r9HBEoVgaJr71nXEg+gzeHOMlUqysq3DhU kV1RyxSDrUEGifG09X+JxSDpaaK2n4/UQTGQ2NVd9gemWnB3HgEPeIWV5VFImwZJYAGl BDL5L905zUY0ISvFJZpfQ6NLIaKQzFXtftFAICSMktQ3sMc7pbWfhwFXtueU42znsB9Z +TlldQxoUOERqguwKai1b4Diy/YeL96VYnXcTjDBzDtrdnu+/RwKO7t7IzHdZcYjQnFn 9oT7etVl9l2z0Aj+ZWAF1yxNrU12huxPsC1Nc9JRLWSEybu6iZ15dcT+Y1pbKjfD7n+4 q/PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=3WX4PyACZXCjj/SabLqf6nUx4PsGAAJsQWdBIB/iEwA=; b=p3Mfewym17HLRXxr7trq/B/lCTAXnqU5jxC+nq2ycp0Si3LX1QQde98L/pxgGluBrM pC7oIYOGNBDJpCvkL1rVmVatBh0QZEbb5B6mTUn/zDCt/mRFQxZFc5HlF5pqaUHyf86q 0DB0GkhRpNlT7H6120xsCKNAfcF7qUqmYuumufopTDMjVL/TvELfLJGurHgtGU+hr23C 4Xzgq6vygDTL1vf8TQ5L0NqjLzxWONhw2V1qdb13kKjiWFIg9SHt3cfrYfiDcasdP1uo 8tGonNJpA785VKplYmFM0vgeT+E6R3y003GR66kpI8ualERIa94y15pBIJq+Uhb3LMcz 1tZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=dgK17+NT; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Thu, 27 Apr 2023 09:24:13 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 04/11] RISC-V: Enforce atomic compare_exchange SEQ_CST Date: Thu, 27 Apr 2023 09:22:54 -0700 Message-Id: <20230427162301.1151333-5-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347393674991321?= X-GMAIL-MSGID: =?utf-8?q?1764347393674991321?= This patch enforces SEQ_CST for atomic compare_exchange ops. Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/sync.md: Change FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 0c83ef04607..5620d6ffa58 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -297,9 +297,16 @@ UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" + { + return "1:\;" + "lr..aqrl\t%0,%1\;" + "bne\t%0,%z2,1f\;" + "sc..rl\t%6,%z3,%1\;" + "bnez\t%6,1b\;" + "1:"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 20))]) + (set (attr "length") (const_int 16))]) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand" "") ;; bool output From patchwork Thu Apr 27 16:22:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 88319 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp392094vqo; Thu, 27 Apr 2023 09:31:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6fB3T2S85ivx8jPdRBoZLhXTuPyS1dt1lnk90ffxYL3Go+Zf6dtx/8AEpNW+xjKXL1onO6 X-Received: by 2002:a17:907:72c3:b0:94e:e859:7b07 with SMTP id du3-20020a17090772c300b0094ee8597b07mr2460455ejc.32.1682613115960; Thu, 27 Apr 2023 09:31:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682613115; cv=none; d=google.com; s=arc-20160816; b=TeCn3+iegw/J8LDN+UqO1bsKnyKfzHBqliRYuNZ/rsepBHUnAqYQKusY3nFML0RXp/ ko+zXxGUdoisZ5C9XzJvJvyhZRh62vQVEvKzUz1+50KWgYEJXdwrrmmSIE1O1zOnK6hk x5IprxSnahLOfx5ii+gJj06TTvRWlRXhimQCzu6HeZ/Y59bGhw8IoLbPdlI0YrpyyI8v mov5imyR0J0ZY64gR/ugl/Ut7aEfn6c1RXDSPowVwvvneyXmmPHii04KwfoDRaHVZ8mE AcIivlY4QW3c96cz7sv3IV64tD+8Gbmm+3Zt65CDx9IJcRVzploOABS2NV7eDBF+H/tK pMBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=bNjSgMTTHLV0g1Ugg2ndTxjKWJO/vLcHLnGM5M4SXmU=; b=aL8cQrXMP7Ww+IgOFTPqtd1IIyv9zuF87DFf8+paTS28E8ImKCOhiiJaYwAzhG7soC e5Tiyop0cIk4ZuLlYYeb9nG1u6M8B/UcFsZ6g5/yHqWplMcB7IEZTJ5GADqSMz8VqUI8 cau487fKc3HF1LKlmXBqEhFFmYw7F4FiF5eOcAfERiLMono0esF4R4sHhHiKjBGHkOtj Im11VOGllgiszou1/3Kh2EbhbLVKnlY/v7fPJRt2GR91w8/JUj7CT4iBgrLcNPjCSqQf INvB/XgazpwTt3YqmgBP+6nf33f8F091VNEV72LtPNZPO95XkZzVbcWOGuSCuxactOx7 vTyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=19osVDk5; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. 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Thu, 27 Apr 2023 09:24:15 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 05/11] RISC-V: Add AMO release bits Date: Thu, 27 Apr 2023 09:22:55 -0700 Message-Id: <20230427162301.1151333-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347730958193573?= X-GMAIL-MSGID: =?utf-8?q?1764347730958193573?= This patch sets the relevant .rl bits on amo operations. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): change behavior of %A to include release bits. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 02eb5125ac1..d46781d8981 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4503,8 +4503,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) + if (riscv_memmodel_needs_amo_acquire (model) + && riscv_memmodel_needs_release_fence (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence (model)) + fputs (".rl", file); break; case 'F': From patchwork Thu Apr 27 16:22:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 88309 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp388986vqo; Thu, 27 Apr 2023 09:26:33 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6mfr10ssTYCYBLikF3xPYOXkpw/1T4Vvh4/N7v7rEkUpyYZi8NstmG/q3lBtm1Y4rWuFkA X-Received: by 2002:a17:906:eec8:b0:93e:fa12:aa1a with SMTP id wu8-20020a170906eec800b0093efa12aa1amr2756915ejb.1.1682612793018; Thu, 27 Apr 2023 09:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682612793; cv=none; d=google.com; s=arc-20160816; b=gJ8pEhybIwBZ8bltHeRRQnkO2N517t3eOXoK+zInNeOvZd3uaMYCQZbpDe9JWc9X6N tWw4ZsSO7bii17U0cWvgoMWeEp3fIkzDaOF2C5uA0FLk+enP7epVvm65sNh362rFJ3op YgIfkJ5fvby9U3v5YnDSlXuwXVH9/Qj6dn/DR4b8TnfhN6G3U3t3o3AKpP+wpf4orKLX 4Trxaf6wd77ChLRv4ZD04G52o5NYt+pleRideWiqX489avxzzXRE7/TYHFLEJxDVry0R TkLY9gszDc2LqhFYQO3m0sJYdObxq9OGXbncysSqiwDCwNFKfFZT/C2KJztisD2At8uM tpXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=Fkgy1RpPD1W3gIeYbyfMEFXSyb13FWzwkogasS4gr10=; b=RrmeEebMVsCjeN4ytgKyvEEZjt059ZL7z80wYB9TsHFLFkxRtx36ETOgobyqXIAFKt RGLsAUP/Fs7UfUPpZXBYSIC2h6E5N2R5Yf5Pfwry8V4NSlLDaxoL/L1hS8lagCpLFgp5 iDaMtx1xeozCIGaALxzVlNID7Fn4S3tDa1a0qi/aol4QwrGPPzix+Iok7l9TxKdqfKxp P95hd9UqJj0B+pFAsB2huksPGmNRx40w/lS19tE4grpLI73QwvuoSdPVlFDmsCOBhEw4 rkx3C5DDtgva669BCWHjPZGBqiZ1xNykSoSN+Yr6pTzI4AoEjlbMKE4aC9kg1kpYPT86 RE7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=kOnEh29K; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Thu, 27 Apr 2023 09:24:17 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 06/11] RISC-V: Strengthen atomic stores Date: Thu, 27 Apr 2023 09:22:56 -0700 Message-Id: <20230427162301.1151333-7-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347392008617221?= X-GMAIL-MSGID: =?utf-8?q?1764347392008617221?= This change makes atomic stores strictly stronger than table A.6 of the ISA manual. This mapping makes the overall patchset compatible with table A.7 as well. 2023-04-27 Patrick O'Neill PR 89835 gcc/ChangeLog: * config/riscv/sync.md: gcc/testsuite/ChangeLog: * gcc.target/riscv/pr89835.c: New test. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 21 ++++++++++++++++++--- gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++ 2 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 5620d6ffa58..1acb78a9ae4 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -56,7 +56,9 @@ ;; Atomic memory operations. -;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. +;; Implement atomic stores with conservative fences. Fall back to fences for +;; atomic loads. +;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") (unspec_volatile:GPR @@ -64,9 +66,22 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,w\;" + "s\t%z1,%0\;" + "fence\trw,rw"; + if (model == MEMMODEL_RELEASE) + return "fence\trw,w\;" + "s\t%z1,%0"; + else + return "s\t%z1,%0"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 12))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c new file mode 100644 index 00000000000..ab190e11b60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr89835.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that relaxed atomic stores use simple store instuctions. */ +/* { dg-final { scan-assembler-not "amoswap" } } */ + +void +foo(int bar, int baz) +{ + __atomic_store_n(&bar, baz, __ATOMIC_RELAXED); +} From patchwork Thu Apr 27 16:22:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 88312 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp390098vqo; Thu, 27 Apr 2023 09:28:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7IZTy1Uea9pnJb5rhbZMDfCm6VfD3OpjzbfF89jlOJoxF38LpNSnooXrotFgDQ6m/IgWXi X-Received: by 2002:a17:906:3a8f:b0:953:37d9:282f with SMTP id y15-20020a1709063a8f00b0095337d9282fmr5167577ejd.38.1682612924051; Thu, 27 Apr 2023 09:28:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682612924; cv=none; d=google.com; s=arc-20160816; b=ZOSMhpqkw37SHzhAu0eiGO86PKWtr0YonfYH3bLpQKZgBAFM5s63uuzJ1OqmueGVPf gww16Bt6Tlo20s1SGE5BgqX4wRYWXqcSgYFUyiMPjtwTjiJU8rhBHzvmUuUIgDpRDLWR szYbCNzGyJiD+ZeAxGG0TDXkU5q01M6hjcRUR9olUOrve8/HgLNbx95CpOGmt1/dnHul PVDZLKNk9cLVv4MjQf6FOPuFw5gs2kh5SvWfcXyOXtaEslxFwBojt6C5dHTrrZ3K9C51 aUSVYTGVH/54/4DxRXRlHk9KaKJaKmfiLFF7HRv19+pdDwSzaVZlARK2ccPZVR4kkHPi FWow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=vXnEuSJcUm5WuWYOJ9yr9SOJ0ChWceAC7VRnimbg1a0=; b=r9Vf4NJQ0LV2IoBgvNmoR/wvPfsDTyrIXEllFGWEkftkydSLoaO3xO5SDVbhgtanUI PF3GFyvu4cUj84EE+tevWVl5f20rBCAwR57wzyzvU/Vg0Rv9NIqRa45528FtpLQqAmGa ChW3BsL9/6ZXt6gzDVna+OqD/sKeq+ArgcvoIKWvSEdr8+0PjnP/iLzAjYZsnFwltKLV 8ol2Y3Vh8fdMS4MhB3/P2zFWKe4HftVr+2aB1zKAmLd/REFBc3KOOUtPxPYz9h8/1djD d2NOZZHnGQwVra8MjJv4qK/b3Vt35BktokcdW2wz6mYeljrUxwkUgGqcEIhA9k1iJqgo Bs9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=XtTNFCd1; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Thu, 27 Apr 2023 09:24:18 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 07/11] RISC-V: Eliminate AMO op fences Date: Thu, 27 Apr 2023 09:22:57 -0700 Message-Id: <20230427162301.1151333-8-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347529640155104?= X-GMAIL-MSGID: =?utf-8?q?1764347529640155104?= Atomic operations with the appropriate bits set already enfore release semantics. Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc (riscv_memmodel_needs_amo_release): Change function name. (riscv_print_operand): Remove unneeded %F case. * config/riscv/sync.md: Remove unneeded fences. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 16 +++++----------- gcc/config/riscv/sync.md | 12 ++++++------ 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d46781d8981..9eba03ac189 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4312,11 +4312,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ +/* Return true if the .RL suffix should be added to an AMO to implement the + release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) { @@ -4342,7 +4342,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4504,19 +4503,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'A': if (riscv_memmodel_needs_amo_acquire (model) - && riscv_memmodel_needs_release_fence (model)) + && riscv_memmodel_needs_amo_release (model)) fputs (".aqrl", file); else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); - else if (riscv_memmodel_needs_release_fence (model)) + else if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 1acb78a9ae4..9a3b57bd09f 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -91,9 +91,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" + "amo.%A2\tzero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -105,9 +105,9 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" + "amo.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "subword_atomic_fetch_strong_" [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem @@ -247,9 +247,9 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" + "amoswap.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_expand "atomic_exchange" [(match_operand:SHORT 0 "register_operand") ;; old value at mem From patchwork Thu Apr 27 16:22:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 88315 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp390374vqo; Thu, 27 Apr 2023 09:29:16 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5iSzJmRKXfoJpC7A5oAA6QAXeV5OYRVapNH7XFdt+FO5C+G2lB/Cl3DG9sVCkaOXdUtnEI X-Received: by 2002:a17:907:6e16:b0:953:4987:4b8 with SMTP id sd22-20020a1709076e1600b00953498704b8mr2341704ejc.47.1682612956054; Thu, 27 Apr 2023 09:29:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682612956; cv=none; d=google.com; s=arc-20160816; b=C+6NmQWnNzJHGj4EGEQ5FyU4JqmbVQK00vDvIUMu8fQvGsofMZ9dEQj4+lUsf4ojQs Bl5xZJ+cLSpJEWDWolwCILLWrwC2qPIXzGhZ6XBjEz/shHDdoYMHs2V+gCPtTLaEUK7x dC8j5XDu4zqNN2dBx011BIQr86D1pRAD+t5lDjaVbkc2Lf8Mze4Nx0E7Xwx4Xo4rMNO2 +oLp4edju3/ScKw8ZDsq6m5mG2449czssYEswMim18vufxTtLPXJcQe4Vey6yV7HBj/2 jOAG+DfpJdTcLvmCvqYmJTnOxUb2LFKGXCnfwt4FPs71u1dgkgaUh+gyxInA/9Fqvk/J P0cQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=jj5QT1yI1Yn4DschSmlhYBQXITm427STmY5/fgnqXfU=; b=wZnN0lNH2INdEFr73Rhnx5dVzPDVTHArYbNmVrWpW7lSNcimS9/XJMJDTwI6UNkIBV xduqN0Ct6s7Bg/2guY0m8Mz7nVTYG4Lhqdtgmm0Qqzestv0fCEfNHG6Bu1QoVSrlhhUR DVegfC1hiUTNUpnlsPoMwxpM1Pbi9DOOsKp5Tnt4c1aB2e+0HcRrjsv9lk1IecSBnMbx w4WAAnf1GT0ElE/RhsnwLa2yp3DvuEANA3PyiXWa5CrwXRia2XiyP4X6T6dSpbCWVu96 xJSAprvRO6NySQKLmqV50MWNZHfpGRQTiO2xDbj9kaeRSo/xVEqgejgbPEziQ+NY8WZ2 Bikw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=0XsE7Kxs; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. 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Atomic compare and exchange ops provide success and failure memory models. C++17 and later place no restrictions on the relative strength of each model, so ensure we cover both by using a model that enforces the ordering of both given models. This change brings LR/SC ops in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_union_memmodels): Expose riscv_union_memmodels function to sync.md. * config/riscv/riscv.cc (riscv_union_memmodels): Add function to get the union of two memmodels in sync.md. (riscv_print_operand): Add %I and %J flags that output the optimal LR/SC flag bits for a given memory model. * config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl bits on SC op and replace with optimized %I, %J flags. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] --- v5 Changelog: * Also optimize subword LR/SC ops based on given memory model. --- gcc/config/riscv/riscv-protos.h | 3 + gcc/config/riscv/riscv.cc | 44 ++++++++++++ gcc/config/riscv/sync.md | 114 +++++++++++++++++++------------- 3 files changed, 114 insertions(+), 47 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index f87661bde2c..5fa9e1122ab 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_RISCV_PROTOS_H #define GCC_RISCV_PROTOS_H +#include "memmodel.h" + /* Symbol types we understand. The order of this list must match that of the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ enum riscv_symbol_type { @@ -81,6 +83,7 @@ extern bool riscv_v_ext_vector_mode_p (machine_mode); extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); +extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9eba03ac189..69e9b2aa548 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4289,6 +4289,36 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) fputc (')', file); } +/* Return the memory model that encapuslates both given models. */ + +enum memmodel +riscv_union_memmodels (enum memmodel model1, enum memmodel model2) +{ + model1 = memmodel_base (model1); + model2 = memmodel_base (model2); + + enum memmodel weaker = model1 <= model2 ? model1: model2; + enum memmodel stronger = model1 > model2 ? model1: model2; + + switch (stronger) + { + case MEMMODEL_SEQ_CST: + case MEMMODEL_ACQ_REL: + return stronger; + case MEMMODEL_RELEASE: + if (weaker == MEMMODEL_ACQUIRE || weaker == MEMMODEL_CONSUME) + return MEMMODEL_ACQ_REL; + else + return stronger; + case MEMMODEL_ACQUIRE: + case MEMMODEL_CONSUME: + case MEMMODEL_RELAXED: + return stronger; + default: + gcc_unreachable (); + } +} + /* Return true if the .AQ suffix should be added to an AMO to implement the acquire portion of memory model MODEL. */ @@ -4342,6 +4372,8 @@ riscv_memmodel_needs_amo_release (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. + 'I' Print the LR suffix for memory model OP. + 'J' Print the SC suffix for memory model OP. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4511,6 +4543,18 @@ riscv_print_operand (FILE *file, rtx op, int letter) fputs (".rl", file); break; + case 'I': + if (model == MEMMODEL_SEQ_CST) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) + fputs (".aq", file); + break; + + case 'J': + if (riscv_memmodel_needs_amo_release (model)) + fputs (".rl", file); + break; + case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 9a3b57bd09f..3e6345e83a3 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -116,21 +116,22 @@ (unspec_volatile:SI [(any_atomic:SI (match_dup 1) (match_operand:SI 2 "register_operand" "rI")) ;; value for op - (match_operand:SI 3 "register_operand" "rI")] ;; mask + (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP_SUBWORD)) - (match_operand:SI 4 "register_operand" "rI") ;; not_mask - (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1 - (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2 + (match_operand:SI 4 "register_operand" "rI") ;; mask + (match_operand:SI 5 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aqrl\t%0, %1\;" - "\t%5, %0, %2\;" - "and\t%5, %5, %3\;" - "and\t%6, %0, %4\;" - "or\t%6, %6, %5\;" - "sc.w.rl\t%5, %6, %1\;" - "bnez\t%5, 1b"; + "lr.w%I3\t%0, %1\;" + "\t%6, %0, %2\;" + "and\t%6, %6, %4\;" + "and\t%7, %0, %5\;" + "or\t%7, %7, %6\;" + "sc.w%J3\t%6, %7, %1\;" + "bnez\t%6, 1b"; } [(set (attr "length") (const_int 28))]) @@ -151,6 +152,7 @@ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; rtx value = operands[2]; + rtx model = operands[3]; rtx aligned_mem = gen_reg_rtx (SImode); rtx shift = gen_reg_rtx (SImode); rtx mask = gen_reg_rtx (SImode); @@ -162,7 +164,7 @@ riscv_lshift_subword (mode, value, shift, &shifted_value); emit_insn (gen_subword_atomic_fetch_strong_nand (old, aligned_mem, - shifted_value, + shifted_value, model, mask, not_mask)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, @@ -180,22 +182,23 @@ (unspec_volatile:SI [(not:SI (and:SI (match_dup 1) (match_operand:SI 2 "register_operand" "rI"))) ;; value for op - (match_operand:SI 3 "register_operand" "rI")] ;; mask + (match_operand:SI 3 "const_int_operand")] ;; mask UNSPEC_SYNC_OLD_OP_SUBWORD)) - (match_operand:SI 4 "register_operand" "rI") ;; not_mask - (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1 - (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2 + (match_operand:SI 4 "register_operand" "rI") ;; mask + (match_operand:SI 5 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aqrl\t%0, %1\;" - "and\t%5, %0, %2\;" - "not\t%5, %5\;" - "and\t%5, %5, %3\;" - "and\t%6, %0, %4\;" - "or\t%6, %6, %5\;" - "sc.w.rl\t%5, %6, %1\;" - "bnez\t%5, 1b"; + "lr.w%I3\t%0, %1\;" + "and\t%6, %0, %2\;" + "not\t%6, %6\;" + "and\t%6, %6, %4\;" + "and\t%7, %0, %5\;" + "or\t%7, %7, %6\;" + "sc.w%J3\t%6, %7, %1\;" + "bnez\t%6, 1b"; } [(set (attr "length") (const_int 32))]) @@ -216,6 +219,7 @@ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; rtx value = operands[2]; + rtx model = operands[3]; rtx aligned_mem = gen_reg_rtx (SImode); rtx shift = gen_reg_rtx (SImode); rtx mask = gen_reg_rtx (SImode); @@ -228,7 +232,8 @@ emit_insn (gen_subword_atomic_fetch_strong_ (old, aligned_mem, shifted_value, - mask, not_mask)); + model, mask, + not_mask)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, gen_lowpart (QImode, shift))); @@ -261,6 +266,7 @@ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; rtx value = operands[2]; + rtx model = operands[3]; rtx aligned_mem = gen_reg_rtx (SImode); rtx shift = gen_reg_rtx (SImode); rtx mask = gen_reg_rtx (SImode); @@ -272,7 +278,8 @@ riscv_lshift_subword (mode, value, shift, &shifted_value); emit_insn (gen_subword_atomic_exchange_strong (old, aligned_mem, - shifted_value, not_mask)); + shifted_value, model, + not_mask)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, gen_lowpart (QImode, shift))); @@ -286,18 +293,19 @@ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location (set (match_dup 1) (unspec_volatile:SI - [(match_operand:SI 2 "reg_or_0_operand" "rI") ;; value - (match_operand:SI 3 "reg_or_0_operand" "rI")] ;; not_mask + [(match_operand:SI 2 "reg_or_0_operand" "rI") ;; value + (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_EXCHANGE_SUBWORD)) - (clobber (match_scratch:SI 4 "=&r"))] ;; tmp_1 + (match_operand:SI 4 "reg_or_0_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 5 "=&r"))] ;; tmp_1 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aqrl\t%0, %1\;" - "and\t%4, %0, %3\;" - "or\t%4, %4, %2\;" - "sc.w.rl\t%4, %4, %1\;" - "bnez\t%4, 1b"; + "lr.w%I3\t%0, %1\;" + "and\t%5, %0, %4\;" + "or\t%5, %5, %2\;" + "sc.w%J3\t%5, %5, %1\;" + "bnez\t%5, 1b"; } [(set (attr "length") (const_int 20))]) @@ -313,10 +321,15 @@ (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" { + enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); + /* Find the union of the two memory models so we can satisfy both success + and failure memory models. */ + operands[5] = GEN_INT (riscv_union_memmodels (model_success, model_failure)); return "1:\;" - "lr..aqrl\t%0,%1\;" + "lr.%I5\t%0,%1\;" "bne\t%0,%z2,1f\;" - "sc..rl\t%6,%z3,%1\;" + "sc.%J5\t%6,%z3,%1\;" "bnez\t%6,1b\;" "1:"; } @@ -440,9 +453,15 @@ emit_move_insn (shifted_o, gen_rtx_AND (SImode, shifted_o, mask)); emit_move_insn (shifted_n, gen_rtx_AND (SImode, shifted_n, mask)); + enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); + /* Find the union of the two memory models so we can satisfy both success + and failure memory models. */ + rtx model = GEN_INT (riscv_union_memmodels (model_success, model_failure)); + emit_insn (gen_subword_atomic_cas_strong (old, aligned_mem, shifted_o, shifted_n, - mask, not_mask)); + model, mask, not_mask)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, gen_lowpart (QImode, shift))); @@ -459,19 +478,20 @@ (unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ") ;; expected value (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; desired value UNSPEC_COMPARE_AND_SWAP_SUBWORD)) - (match_operand:SI 4 "register_operand" "rI") ;; mask - (match_operand:SI 5 "register_operand" "rI") ;; not_mask - (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_1 + (match_operand:SI 4 "const_int_operand") ;; model + (match_operand:SI 5 "register_operand" "rI") ;; mask + (match_operand:SI 6 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_1 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aqrl\t%0, %1\;" - "and\t%6, %0, %4\;" - "bne\t%6, %z2, 1f\;" - "and\t%6, %0, %5\;" - "or\t%6, %6, %3\;" - "sc.w.rl\t%6, %6, %1\;" - "bnez\t%6, 1b\;" + "lr.w%I4\t%0, %1\;" + "and\t%7, %0, %5\;" + "bne\t%7, %z2, 1f\;" + "and\t%7, %0, %6\;" + "or\t%7, %7, %3\;" + "sc.w%J4\t%7, %7, %1\;" + "bnez\t%7, 1b\;" "1:"; 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Relax mem_thread_fence according to the memmodel given. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] * Remove helper functions --- gcc/config/riscv/sync.md | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 3e6345e83a3..ba132d8a1ce 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -45,14 +45,24 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw"; + else if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (model == MEMMODEL_ACQUIRE) + return "fence\tr,rw"; + else if (model == MEMMODEL_RELEASE) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations. 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Thu, 27 Apr 2023 09:24:22 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 10/11] RISC-V: Weaken atomic loads Date: Thu, 27 Apr 2023 09:23:00 -0700 Message-Id: <20230427162301.1151333-11-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347509245940482?= X-GMAIL-MSGID: =?utf-8?q?1764347509245940482?= This change brings atomic loads in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/sync.md (atomic_load): Implement atomic load mapping. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ba132d8a1ce..6e7c762ac57 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,7 @@ UNSPEC_SYNC_OLD_OP_SUBWORD UNSPEC_SYNC_EXCHANGE UNSPEC_SYNC_EXCHANGE_SUBWORD + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -66,8 +67,31 @@ ;; Atomic memory operations. -;; Implement atomic stores with conservative fences. Fall back to fences for -;; atomic loads. +(define_insn "atomic_load" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ATOMIC" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" + "l\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) + return "l\t%0,%1\;" + "fence\tr,rw"; + else + return "l\t%0,%1"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 12))]) + +;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. 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Thu, 27 Apr 2023 09:24:24 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 11/11] RISC-V: Table A.6 conformance tests Date: Thu, 27 Apr 2023 09:23:01 -0700 Message-Id: <20230427162301.1151333-12-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347648772061764?= X-GMAIL-MSGID: =?utf-8?q?1764347648772061764?= These tests cover basic cases to ensure the atomic mappings follow the strengthened Table A.6 mappings that are compatible with Table A.7. 2023-04-27 Patrick O'Neill gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-2.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-3.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-4.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-5.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-a-6-fence-1.c: New test. * gcc.target/riscv/amo-table-a-6-fence-2.c: New test. * gcc.target/riscv/amo-table-a-6-fence-3.c: New test. * gcc.target/riscv/amo-table-a-6-fence-4.c: New test. * gcc.target/riscv/amo-table-a-6-fence-5.c: New test. * gcc.target/riscv/amo-table-a-6-load-1.c: New test. * gcc.target/riscv/amo-table-a-6-load-2.c: New test. * gcc.target/riscv/amo-table-a-6-load-3.c: New test. * gcc.target/riscv/amo-table-a-6-store-1.c: New test. * gcc.target/riscv/amo-table-a-6-store-2.c: New test. * gcc.target/riscv/amo-table-a-6-store-compat-3.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill --- .../gcc.target/riscv/amo-table-a-6-amo-add-1.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-2.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-3.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-4.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-5.c | 8 ++++++++ .../riscv/amo-table-a-6-compare-exchange-1.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-2.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-3.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-4.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-5.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-6.c | 11 +++++++++++ .../riscv/amo-table-a-6-compare-exchange-7.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-1.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-fence-2.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-3.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-4.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-5.c | 10 ++++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c | 9 +++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c | 11 +++++++++++ .../gcc.target/riscv/amo-table-a-6-store-1.c | 9 +++++++++ .../gcc.target/riscv/amo-table-a-6-store-2.c | 11 +++++++++++ .../gcc.target/riscv/amo-table-a-6-store-compat-3.c | 11 +++++++++++ .../riscv/amo-table-a-6-subword-amo-add-1.c | 9 +++++++++ .../riscv/amo-table-a-6-subword-amo-add-2.c | 9 +++++++++ .../riscv/amo-table-a-6-subword-amo-add-3.c | 9 +++++++++ .../riscv/amo-table-a-6-subword-amo-add-4.c | 9 +++++++++ .../riscv/amo-table-a-6-subword-amo-add-5.c | 9 +++++++++ 28 files changed, 266 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c new file mode 100644 index 00000000000..cb044f78fcf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c new file mode 100644 index 00000000000..c8445321989 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aq\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c new file mode 100644 index 00000000000..dfec3020c91 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.rl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c new file mode 100644 index 00000000000..b9f90e199b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c new file mode 100644 index 00000000000..94c4bec933b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c new file mode 100644 index 00000000000..a9141cde48f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c new file mode 100644 index 00000000000..b1ebb20e2f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME, __ATOMIC_CONSUME); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c new file mode 100644 index 00000000000..47d8d02f7e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c new file mode 100644 index 00000000000..af6e1d69c75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c new file mode 100644 index 00000000000..ceb5660b6af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c new file mode 100644 index 00000000000..7b012fb1288 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* Mixed mappings need to be unioned. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c new file mode 100644 index 00000000000..5adec6f7a19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c new file mode 100644 index 00000000000..b8c28013ef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c new file mode 100644 index 00000000000..117f9036e39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c new file mode 100644 index 00000000000..4b6dd7a9aa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c new file mode 100644 index 00000000000..d40d3bc37db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence.tso" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c new file mode 100644 index 00000000000..71f76c27789 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c new file mode 100644 index 00000000000..8278198072e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c new file mode 100644 index 00000000000..84b6cc542ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c new file mode 100644 index 00000000000..3f15041d117 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c new file mode 100644 index 00000000000..c200bd1d11d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that store mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c new file mode 100644 index 00000000000..1cf366b5986 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that store mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c new file mode 100644 index 00000000000..288e1493156 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that store mapping are compatible with Table A.6 & A.7. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c new file mode 100644 index 00000000000..9efa25ddf26 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c new file mode 100644 index 00000000000..536f7e9228f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c new file mode 100644 index 00000000000..69c2324a1f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c new file mode 100644 index 00000000000..a0779b4c421 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c new file mode 100644 index 00000000000..f88901dc717 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +}