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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id y6-20020aa7ccc6000000b005069969e508si13618835edt.522.2023.04.27.07.31.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 07:31:51 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=AVEjUhXN; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 01EAC3858C74 for ; Thu, 27 Apr 2023 14:31:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 01EAC3858C74 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682605908; bh=15ZKKSoI0E22CBOE5xt5ObwJT8qwpbdrhIDQ7Yq9V2A=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=AVEjUhXNnmcHUsoeroclIEzi2WYCvIorZGJZUspW356o3WRiT4yEpD3cKXC6aYlSi 4sVzsNJ+5ySxCkkRYK6I/0weolVwVASMza2g+7u2NQ5aHJfRQJigI9IyU9Vaz2IjBJ sgeb1GrOBIkw2E3LuoZKXi5IwuAirWp1IqT8jRQ0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 997343858409 for ; Thu, 27 Apr 2023 14:30:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 997343858409 X-IronPort-AV: E=McAfee;i="6600,9927,10693"; a="347468190" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="347468190" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2023 07:30:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10693"; a="868745879" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="868745879" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga005.jf.intel.com with ESMTP; 27 Apr 2023 07:30:07 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id A6E2F1006F04; Thu, 27 Apr 2023 22:30:06 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR Date: Thu, 27 Apr 2023 22:30:05 +0800 Message-Id: <20230427143005.1781966-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764340175866824896?= X-GMAIL-MSGID: =?utf-8?q?1764340175866824896?= From: Pan Li When some RVV integer compare operators act on the same vector registers without mask. They can be simplified to VMCLR. This PATCH allow the ne, lt, ltu, gt, gtu to perform such kind of the simplification by adding one new define_split. Given we have: vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl) { return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl); } Before this patch: vsetvli zero,a2,e8,m8,ta,ma vl8re8.v v24,0(a1) vmslt.vv v8,v24,v24 vsetvli a5,zero,e8,m8,ta,ma vsm.v v8,0(a0) ret After this patch: vsetvli zero,a2,e8,mf8,ta,ma vmclr.m v24 <- optimized to vmclr.m vsetvli zero,a5,e8,mf8,ta,ma vsm.v v24,0(a0) ret As above, we may have one instruction eliminated and require less vector registers. gcc/ChangeLog: * config/riscv/predicates.md (comparison_simplify_to_clear_operator): Add new predicate of the simplification operators. * config/riscv/vector.md: Add new define split to perform the simplification. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: New test. Signed-off-by: Pan Li Co-authored-by: kito-cheng --- gcc/config/riscv/predicates.md | 6 + gcc/config/riscv/vector.md | 34 ++ .../rvv/base/integer_compare_insn_shortcut.c | 291 ++++++++++++++++++ 3 files changed, 331 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index e5adf06fa25..1626665825b 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -328,6 +328,12 @@ (define_predicate "ltge_operator" (define_predicate "comparison_except_ltge_operator" (match_code "eq,ne,le,leu,gt,gtu")) +;; Some comparison operator with same operands can be simpiled to clear. +;; For example, op[0] = ne (op[1], op[1]) => op[0] = clr (op[0]). We sort +;; similar comparison operators here. +(define_predicate "comparison_simplify_to_clear_operator" + (match_code "ne,lt,ltu,gt,gtu")) + (define_predicate "comparison_except_eqge_operator" (match_code "le,leu,gt,gtu,lt,ltu")) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index b3d23441679..47b97dfe69d 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7689,3 +7689,37 @@ (define_insn "@pred_fault_load" "vleff.v\t%0,%3%p1" [(set_attr "type" "vldff") (set_attr "mode" "")]) + +;; ----------------------------------------------------------------------------- +;; ---- Integer Compare Instructions Simplification +;; ----------------------------------------------------------------------------- +;; Simplify to VMCLR.m Includes: +;; - 1. VMSNE +;; - 2. VMSLT +;; - 3. VMSLTU +;; - 4. VMSGT +;; - 5. VMSGTU +;; ----------------------------------------------------------------------------- +(define_split + [(set (match_operand: 0 "register_operand") + (if_then_else: + (unspec: + [(match_operand: 1 "vector_all_trues_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (match_operator: 3 "comparison_simplify_to_clear_operator" + [(match_operand:VI 4 "register_operand") + (match_operand:VI 5 "vector_arith_operand")]) + (match_operand: 2 "vector_merge_operand")))] + "TARGET_VECTOR && reload_completed && operands[4] == operands[5]" + [(const_int 0)] + { + emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX (mode), + RVV_VUNDEF (mode), CONST0_RTX (mode), + operands[6], operands[8])); + DONE; + } +) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c new file mode 100644 index 00000000000..8954adad09d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c @@ -0,0 +1,291 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ + +#include "riscv_vector.h" + +vbool1_t test_shortcut_for_riscv_vmseq_case_0(vint8m8_t v1, size_t vl) { + return __riscv_vmseq_vv_i8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmseq_case_1(vint8m4_t v1, size_t vl) { + return __riscv_vmseq_vv_i8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmseq_case_2(vint8m2_t v1, size_t vl) { + return __riscv_vmseq_vv_i8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmseq_case_3(vint8m1_t v1, size_t vl) { + return __riscv_vmseq_vv_i8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmseq_case_4(vint8mf2_t v1, size_t vl) { + return __riscv_vmseq_vv_i8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmseq_case_5(vint8mf4_t v1, size_t vl) { + return __riscv_vmseq_vv_i8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmseq_case_6(vint8mf8_t v1, size_t vl) { + return __riscv_vmseq_vv_i8mf8_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmsne_case_0(vint8m8_t v1, size_t vl) { + return __riscv_vmsne_vv_i8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmsne_case_1(vint8m4_t v1, size_t vl) { + return __riscv_vmsne_vv_i8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmsne_case_2(vint8m2_t v1, size_t vl) { + return __riscv_vmsne_vv_i8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmsne_case_3(vint8m1_t v1, size_t vl) { + return __riscv_vmsne_vv_i8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmsne_case_4(vint8mf2_t v1, size_t vl) { + return __riscv_vmsne_vv_i8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmsne_case_5(vint8mf4_t v1, size_t vl) { + return __riscv_vmsne_vv_i8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmsne_case_6(vint8mf8_t v1, size_t vl) { + return __riscv_vmsne_vv_i8mf8_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl) { + return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmslt_case_1(vint8m4_t v1, size_t vl) { + return __riscv_vmslt_vv_i8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmslt_case_2(vint8m2_t v1, size_t vl) { + return __riscv_vmslt_vv_i8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmslt_case_3(vint8m1_t v1, size_t vl) { + return __riscv_vmslt_vv_i8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmslt_case_4(vint8mf2_t v1, size_t vl) { + return __riscv_vmslt_vv_i8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmslt_case_5(vint8mf4_t v1, size_t vl) { + return __riscv_vmslt_vv_i8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmslt_case_6(vint8mf8_t v1, size_t vl) { + return __riscv_vmslt_vv_i8mf8_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmsltu_case_0(vuint8m8_t v1, size_t vl) { + return __riscv_vmsltu_vv_u8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmsltu_case_1(vuint8m4_t v1, size_t vl) { + return __riscv_vmsltu_vv_u8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmsltu_case_2(vuint8m2_t v1, size_t vl) { + return __riscv_vmsltu_vv_u8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmsltu_case_3(vuint8m1_t v1, size_t vl) { + return __riscv_vmsltu_vv_u8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmsltu_case_4(vuint8mf2_t v1, size_t vl) { + return __riscv_vmsltu_vv_u8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmsltu_case_5(vuint8mf4_t v1, size_t vl) { + return __riscv_vmsltu_vv_u8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmsltu_case_6(vuint8mf8_t v1, size_t vl) { + return __riscv_vmsltu_vv_u8mf8_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmsle_case_0(vint8m8_t v1, size_t vl) { + return __riscv_vmsle_vv_i8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmsle_case_1(vint8m4_t v1, size_t vl) { + return __riscv_vmsle_vv_i8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmsle_case_2(vint8m2_t v1, size_t vl) { + return __riscv_vmsle_vv_i8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmsle_case_3(vint8m1_t v1, size_t vl) { + return __riscv_vmsle_vv_i8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmsle_case_4(vint8mf2_t v1, size_t vl) { + return __riscv_vmsle_vv_i8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmsle_case_5(vint8mf4_t v1, size_t vl) { + return __riscv_vmsle_vv_i8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmsle_case_6(vint8mf8_t v1, size_t vl) { + return __riscv_vmsle_vv_i8mf8_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmsleu_case_0(vuint8m8_t v1, size_t vl) { + return __riscv_vmsleu_vv_u8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmsleu_case_1(vuint8m4_t v1, size_t vl) { + return __riscv_vmsleu_vv_u8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmsleu_case_2(vuint8m2_t v1, size_t vl) { + return __riscv_vmsleu_vv_u8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmsleu_case_3(vuint8m1_t v1, size_t vl) { + return __riscv_vmsleu_vv_u8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmsleu_case_4(vuint8mf2_t v1, size_t vl) { + return __riscv_vmsleu_vv_u8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmsleu_case_5(vuint8mf4_t v1, size_t vl) { + return __riscv_vmsleu_vv_u8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmsleu_case_6(vuint8mf8_t v1, size_t vl) { + return __riscv_vmsleu_vv_u8mf8_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmsgt_case_0(vint8m8_t v1, size_t vl) { + return __riscv_vmsgt_vv_i8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmsgt_case_1(vint8m4_t v1, size_t vl) { + return __riscv_vmsgt_vv_i8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmsgt_case_2(vint8m2_t v1, size_t vl) { + return __riscv_vmsgt_vv_i8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmsgt_case_3(vint8m1_t v1, size_t vl) { + return __riscv_vmsgt_vv_i8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmsgt_case_4(vint8mf2_t v1, size_t vl) { + return __riscv_vmsgt_vv_i8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmsgt_case_5(vint8mf4_t v1, size_t vl) { + return __riscv_vmsgt_vv_i8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmsgt_case_6(vint8mf8_t v1, size_t vl) { + return __riscv_vmsgt_vv_i8mf8_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmsgtu_case_0(vuint8m8_t v1, size_t vl) { + return __riscv_vmsgtu_vv_u8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmsgtu_case_1(vuint8m4_t v1, size_t vl) { + return __riscv_vmsgtu_vv_u8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmsgtu_case_2(vuint8m2_t v1, size_t vl) { + return __riscv_vmsgtu_vv_u8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmsgtu_case_3(vuint8m1_t v1, size_t vl) { + return __riscv_vmsgtu_vv_u8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmsgtu_case_4(vuint8mf2_t v1, size_t vl) { + return __riscv_vmsgtu_vv_u8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmsgtu_case_5(vuint8mf4_t v1, size_t vl) { + return __riscv_vmsgtu_vv_u8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmsgtu_case_6(vuint8mf8_t v1, size_t vl) { + return __riscv_vmsgtu_vv_u8mf8_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmsge_case_0(vint8m8_t v1, size_t vl) { + return __riscv_vmsge_vv_i8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmsge_case_1(vint8m4_t v1, size_t vl) { + return __riscv_vmsge_vv_i8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmsge_case_2(vint8m2_t v1, size_t vl) { + return __riscv_vmsge_vv_i8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmsge_case_3(vint8m1_t v1, size_t vl) { + return __riscv_vmsge_vv_i8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmsge_case_4(vint8mf2_t v1, size_t vl) { + return __riscv_vmsge_vv_i8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmsge_case_5(vint8mf4_t v1, size_t vl) { + return __riscv_vmsge_vv_i8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmsge_case_6(vint8mf8_t v1, size_t vl) { + return __riscv_vmsge_vv_i8mf8_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmsgeu_case_0(vuint8m8_t v1, size_t vl) { + return __riscv_vmsgeu_vv_u8m8_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmsgeu_case_1(vuint8m4_t v1, size_t vl) { + return __riscv_vmsgeu_vv_u8m4_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmsgeu_case_2(vuint8m2_t v1, size_t vl) { + return __riscv_vmsgeu_vv_u8m2_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmsgeu_case_3(vuint8m1_t v1, size_t vl) { + return __riscv_vmsgeu_vv_u8m1_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmsgeu_case_4(vuint8mf2_t v1, size_t vl) { + return __riscv_vmsgeu_vv_u8mf2_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmsgeu_case_5(vuint8mf4_t v1, size_t vl) { + return __riscv_vmsgeu_vv_u8mf4_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmsgeu_case_6(vuint8mf8_t v1, size_t vl) { + return __riscv_vmsgeu_vv_u8mf8_b64(v1, v1, vl); +} + +/* { dg-final { scan-assembler-times {vmseq\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ +/* { dg-final { scan-assembler-times {vmsle\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ +/* { dg-final { scan-assembler-times {vmsleu\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ +/* { dg-final { scan-assembler-times {vmsge\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ +/* { dg-final { scan-assembler-times {vmsgeu\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ +/* { dg-final { scan-assembler-times {vmclr\.m\sv[0-9]} 35 } } */