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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ne37-20020a1709077ba500b0095f6517b962si2958787ejc.602.2023.04.27.07.30.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 07:30:51 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=rWdXe1fh; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A570C3858D37 for ; Thu, 27 Apr 2023 14:30:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A570C3858D37 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682605849; bh=s3ic2qatnanYVIPudvS52sa/Q02k/ADkqKENarW6/eI=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=rWdXe1fhIcfpqJdC/PjSqa3OPgqg/cPiiT61ldqDifiAAGpiAHAHZZAtN8lMymDcH f6UiraiIfaHFpNLCjlsDXA3dW8iWRPlD/G+Xz3DDBiwL3uU985uvAjyv7b4+yp86sC c1/KHwYGMBKnlWTY36Wac4UFIORfIzt3jP3Zkw18= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by sourceware.org (Postfix) with ESMTPS id E293A3858D33 for ; Thu, 27 Apr 2023 14:30:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E293A3858D33 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-63b620188aeso9927192b3a.0 for ; Thu, 27 Apr 2023 07:30:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682605801; x=1685197801; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=spzf4aOFOX+gpGEPnr760t+7y1W+jYGiMFWtMl9TpsI=; b=Enmiy3uNBMCzyycj0o5rIkulufb2eShTVZVbiWKEID+2lZjQ9Hl8XkUtgDps5tDcwp 4tLU9oiJqAZi9fnAyiYwwXF8hebh+Zo5Dxj9yyafXUR/g1JdAw3JTX+A64qMKuqtka3z 5hrSwBbvu5cD5thK9lE0KPJ7S9HNaiyNYCGUGmzDfkN3PeVLE3ZjqX3hLpsTAF8xB2ny WYllgj+dEC71rAU0qoGgyVgJPAmOZIc8IR1BWRr76jFrl/KEHKzkvMsol4oVPsceWgah QN5KIYlx3aKDoHCxQcpoiCbyJpxWBINqNVJXY9YDIW27tKoWGu8qbnHpf3sZc1PNxlKK bMJw== X-Gm-Message-State: AC+VfDwzauNV+m8C2dQFYlcSObfI8QEpw7P3tbCcR7oqVnNWGIUAJ2i+ FsGII7Mzq+tBIPK0PxXng5iNA3mWuuXm4DmzVLAtzjWhVfQ= X-Received: by 2002:a17:902:db04:b0:1a6:d46b:dfb5 with SMTP id m4-20020a170902db0400b001a6d46bdfb5mr2158437plx.26.1682605801320; Thu, 27 Apr 2023 07:30:01 -0700 (PDT) MIME-Version: 1.0 Date: Thu, 27 Apr 2023 18:29:24 +0400 Message-ID: Subject: RISC-V: Added support clmul[r,h] instructions for Zbc extension. To: gcc-patches@gcc.gnu.org X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HTML_MESSAGE, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Karen Sargsyan via Gcc-patches From: Karen Sargsyan Reply-To: Karen Sargsyan Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764340112570919456?= X-GMAIL-MSGID: =?utf-8?q?1764340112570919456?= clmul[h] instructions were added only for the ZBKC extension. This patch includes them in the ZBC extension too. Besides, added support of 'clmulr' instructions for ZBC extension. gcc/ChangeLog: * config/riscv/bitmanip.md: Added clmulr instruction. * config/riscv/riscv-builtins.cc (AVAIL): Add new. * config/riscv/riscv.md: (UNSPEC_CLMULR): Add new unspec type. * config/riscv/riscv-cmo.def: Added built-in function for clmulr. * config/riscv/crypto.md: Move clmul[h] instructions to bitmanip.md. * config/riscv/riscv-scalar-crypto.def: Move clmul[h] built-in functions to riscv-cmo.def. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbc32.c: New test. * gcc.target/riscv/zbc64.c: New test. diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 44ad350c747..10ffb2d3f51 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -696,3 +696,32 @@ operands[8] = GEN_INT (setbit); operands[9] = GEN_INT (clearbit); }) + +;; ZBKC or ZBC extension +(define_insn "riscv_clmul_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMUL))] + "TARGET_ZBKC || TARGET_ZBC" + "clmul\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + +(define_insn "riscv_clmulh_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMULH))] + "TARGET_ZBKC || TARGET_ZBC" + "clmulh\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + +;; ZBC extension +(define_insn "riscv_clmulr_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMULR))] + "TARGET_ZBC" + "clmulr\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index 777aa529005..e4b7f0190df 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -26,10 +26,6 @@ UNSPEC_PACKH UNSPEC_PACKW - ;; Zbkc unspecs - UNSPEC_CLMUL - UNSPEC_CLMULH - ;; Zbkx unspecs UNSPEC_XPERM8 UNSPEC_XPERM4 @@ -126,26 +122,6 @@ "packw\t%0,%1,%2" [(set_attr "type" "crypto")]) -;; ZBKC extension - -(define_insn "riscv_clmul_" - [(set (match_operand:X 0 "register_operand" "=r") - (unspec:X [(match_operand:X 1 "register_operand" "r") - (match_operand:X 2 "register_operand" "r")] - UNSPEC_CLMUL))] - "TARGET_ZBKC" - "clmul\t%0,%1,%2" - [(set_attr "type" "crypto")]) - -(define_insn "riscv_clmulh_" - [(set (match_operand:X 0 "register_operand" "=r") - (unspec:X [(match_operand:X 1 "register_operand" "r") - (match_operand:X 2 "register_operand" "r")] - UNSPEC_CLMULH))] - "TARGET_ZBKC" - "clmulh\t%0,%1,%2" - [(set_attr "type" "crypto")]) - ;; ZBKX extension (define_insn "riscv_xperm4_" diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index b1c4b7547d7..79681d75962 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -105,8 +105,6 @@ AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT) AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT) -AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT) -AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT) AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT) AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT) AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT) @@ -120,6 +118,10 @@ AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT) AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT) AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT) AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT) +AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) && !TARGET_64BIT) +AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT) +AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT) +AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def index 9fe5094ce1a..b92044dc6ff 100644 --- a/gcc/config/riscv/riscv-cmo.def +++ b/gcc/config/riscv/riscv-cmo.def @@ -15,3 +15,13 @@ RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV // zicbop RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32), RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, prefetchi64), + +// zbkc or zbc +RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, clmul_zbkc32_or_zbc32), +RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, clmul_zbkc64_or_zbc64), +RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, clmul_zbkc32_or_zbc32), +RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, clmul_zbkc64_or_zbc64), + +// zbc +RISCV_BUILTIN (clmulr_si, "clmulr", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, clmulr_zbc32), +RISCV_BUILTIN (clmulr_di, "clmulr", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, clmulr_zbc64), diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def index 139793c6360..c2caed5151d 100644 --- a/gcc/config/riscv/riscv-scalar-crypto.def +++ b/gcc/config/riscv/riscv-scalar-crypto.def @@ -32,12 +32,6 @@ RISCV_BUILTIN (unzip, "unzip", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_z RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zbkb64), -// ZBKC -RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32), -RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64), -RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32), -RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64), - // ZBKX RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 0c69407ac09..dc758b15dd1 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -65,6 +65,11 @@ ;; OR-COMBINE UNSPEC_ORC_B + + ;; Zbc unspecs + UNSPEC_CLMUL + UNSPEC_CLMULH + UNSPEC_CLMULR ]) (define_c_enum "unspecv" [ diff --git a/gcc/testsuite/gcc.target/riscv/zbc32.c b/gcc/testsuite/gcc.target/riscv/zbc32.c new file mode 100644 index 00000000000..08705c4a687 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbc32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbc -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include + +int32_t foo1(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_clmul(rs1, rs2); +} + +int32_t foo2(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_clmulh(rs1, rs2); +} + +int32_t foo3(int32_t rs1, int32_t rs2) +{ + return __builtin_riscv_clmulr(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ +/* { dg-final { scan-assembler-times "clmulr" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbc64.c b/gcc/testsuite/gcc.target/riscv/zbc64.c new file mode 100644 index 00000000000..a19f42b2883 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbc64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_clmul(rs1, rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_clmulh(rs1, rs2); +} + +int64_t foo3(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_clmulr(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ +/* { dg-final { scan-assembler-times "clmulr" 1 } } */