From patchwork Thu Apr 27 10:43:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 88199 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp188256vqo; Thu, 27 Apr 2023 04:12:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6iymonf1DxCthPS4LTyMuIGJbD605HLCfYs8BnktHf5vzjbuT5ja98af4MZuYxSZ99+TXK X-Received: by 2002:a05:6a00:248b:b0:63f:ffd:5360 with SMTP id c11-20020a056a00248b00b0063f0ffd5360mr1954886pfv.21.1682593958246; Thu, 27 Apr 2023 04:12:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682593958; cv=none; d=google.com; s=arc-20160816; b=dNq7grwOM/SyFnt6jUGbdzxOcVozAe6zq6pLwCkngyoVhHpLvIKGfAo+HXbJl8tXTf v1XlwzXtsIZX/PIYeBcExfLN7BvuscXyRB/FvH7MJx09LcgfzeJIiN1o0n1jW6s9u3JO bveAMhimfFS0rBL5B9sAw+r6tvso5QOa53IIC9n7/vTwQNLFV2kXOQt36rYQd9lu9SHC qkvZBl5SeX3cUKJBvU7q8TmrPqzYpnhgQRKlLucAuodQlr691K92cwceq++f27U7mc5g uCuDsJ3veRspngS8fWJzMf0pRRqLFSYVhRd7U453uPPd7t9QVHeJaQHQq69k9Pf3ERIJ 5QUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=/hrH2upqOAtjMtLKI93Cg+V7JxMLgpW28ekXAbEO4xc=; b=rKmx3Ha8MshdEvLp6hfC88mGQtjKERdmGUCJqBp4FUlXUD3do27HW4KoMLQgYH4Y/h GQ4eY2rUZAKrN82Nbq3YzP0QR5rvm9J1/kas7Vm77K3KNWz3R9sfZfHOei4kNQ5zfjVt tdBoHLN9X8REvn0wwAOUHsbTNCcahphKQXATylZdwrFuNBBBW0u6SiMjxxHiNI12pzMW tDOjnSbG6d8gZwTDK1HsDnZJxaM9P4NZrS18Nxo57FA5F1LVfSMgJrcACUB6GNG+dich iZ5ibqzQZ51YgZYWiC3Io7eohv3VKkjRMsttyM7T5IQfOKRfq23Z6+AJlhKb6qiEt1K5 BTHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=2bt6Ah9d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i16-20020a056a00005000b0063aea82b7b9si18116950pfk.405.2023.04.27.04.12.17; Thu, 27 Apr 2023 04:12:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=2bt6Ah9d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243370AbjD0KsK (ORCPT + 99 others); Thu, 27 Apr 2023 06:48:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243448AbjD0KsF (ORCPT ); Thu, 27 Apr 2023 06:48:05 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85F995256; Thu, 27 Apr 2023 03:48:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1682592483; x=1714128483; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=DJAw9VNz1ZsUBRAPmSWDnMHm4RxRMWbc9EwxSgNFsyA=; b=2bt6Ah9diZX4DTTTzlc7YnQnFXGyt/6Kf4Na4tefrB6wRUrwmeS+lD22 pUguPvIZfIUiOFwM2NQAIIJk+MvqcBCC8Qu6eNBmN8EZvYZKSzZ7p31e8 4FYK12JKU4Nfb47LnsDmB3McGUWTVg3ttFZJ1bGpzZlPWAfO8nomqg6cv TXGj3UC83cdFkBVrwk2Dj2rg/viKMJVZCQqHwpHkYOn952D3fD9Ew7Rki jnt9mCAkNsHMB1BJsZ5l9wovueDNJ02mjIecseyEixLvGnRr46dHvZjaI AC41mIFb9Ra9lGPVHpEGfocHiIG/ld92wJw7ybsN+kwVyRoqPShfAwBo+ A==; X-IronPort-AV: E=Sophos;i="5.99,230,1677567600"; d="scan'208";a="211435929" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Apr 2023 03:48:02 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 27 Apr 2023 03:48:01 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 27 Apr 2023 03:47:59 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , , , Subject: [PATCH v1] dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support Date: Thu, 27 Apr 2023 11:43:42 +0100 Message-ID: <20230427-fence-blurred-c92fb69d4137@wendy> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1731; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=DJAw9VNz1ZsUBRAPmSWDnMHm4RxRMWbc9EwxSgNFsyA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClegdfq/j3oPnKMb1NS3+TYBa7qN1tclAtfvXphfWnXyXx2 9/bsjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEykai4jw93ZultuPgqb/fbiv19RZ+ WthEL+JXDOi5AWWcEZrctuc5iR4c6uQ/7qxdpei0/3/YlSq1K7lPTYfsWKuy+bbCS5X3d/YgYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764327642084091560?= X-GMAIL-MSGID: =?utf-8?q?1764327642084091560?= The dt-binding was defined before the extraction of csr access and fence.i into their own extensions, and thus the presence of the I base extension implies Zicsr and Zifencei. There's no harm in adding them obviously, but for backwards compatibility with DTs that existed prior to that extraction, software is unable to differentiate between "i" and "i_zicsr_zifencei" without any further information. Signed-off-by: Conor Dooley Acked-by: Rob Herring --- CC: Conor Dooley CC: Rob Herring CC: Krzysztof Kozlowski CC: Paul Walmsley CC: Palmer Dabbelt CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org CC: linux-kernel@vger.kernel.org --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 4c7ce4a37052..a93bc7eae928 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -85,6 +85,12 @@ properties: User-Level ISA document, available from https://riscv.org/specifications/ + Due to revisions of the ISA specification, some deviations + have arisen over time. + Notably, riscv,isa was defined prior to the creation of the + Zicsr and Zifencei extensions and thus "i" implies + "zicsr_zifencei". + While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing.