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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id bg37-20020a05600c3ca500b003c706e177c1sm1758817wmb.14.2022.10.23.07.57.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:03 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/5] clk: ingenic: Make PLL clock "od" field optional Date: Sun, 23 Oct 2022 15:56:49 +0100 Message-Id: <20221023145653.177234-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747491081013354966?= X-GMAIL-MSGID: =?utf-8?q?1747491081013354966?= Add support for defining PLL clocks with od_bits = 0, meaning that OD is fixed to 1 and there is no OD field in the register. Signed-off-by: Aidan MacDonald --- drivers/clk/ingenic/cgu.c | 28 +++++++++++++++++++--------- drivers/clk/ingenic/cgu.h | 3 ++- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 861c50d6cb24..7dc2e2567d53 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -96,8 +96,11 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) m += pll_info->m_offset; n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); n += pll_info->n_offset; - od_enc = ctl >> pll_info->od_shift; - od_enc &= GENMASK(pll_info->od_bits - 1, 0); + + if (pll_info->od_bits > 0) { + od_enc = ctl >> pll_info->od_shift; + od_enc &= GENMASK(pll_info->od_bits - 1, 0); + } if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); @@ -108,12 +111,17 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) return parent_rate; } - for (od = 0; od < pll_info->od_max; od++) { - if (pll_info->od_encoding[od] == od_enc) - break; + if (pll_info->od_bits > 0) { + for (od = 0; od < pll_info->od_max; od++) { + if (pll_info->od_encoding[od] == od_enc) + break; + } + BUG_ON(od == pll_info->od_max); + od++; + } else { + /* OD is fixed to 1 if no OD field is present. */ + od = 1; } - BUG_ON(od == pll_info->od_max); - od++; return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, n * od); @@ -215,8 +223,10 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); ctl |= (n - pll_info->n_offset) << pll_info->n_shift; - ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); - ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; + if (pll_info->od_bits > 0) { + ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); + ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; + } writel(ctl, cgu->base + pll_info->reg); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 147b7df0d657..567142b584bb 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -33,7 +33,8 @@ * @od_shift: the number of bits to shift the post-VCO divider value by (ie. * the index of the lowest bit of the post-VCO divider value in * the PLL's control register) - * @od_bits: the size of the post-VCO divider field in bits + * @od_bits: the size of the post-VCO divider field in bits, or 0 if no + * OD field exists (then the OD is fixed to 1) * @od_max: the maximum post-VCO divider value * @od_encoding: a pointer to an array mapping post-VCO divider values to * their encoded values in the PLL control register, or -1 for From patchwork Sun Oct 23 14:56:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 8044 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp28099wru; Sun, 23 Oct 2022 08:01:45 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5nP6YBdbDsDUy+VGPSDNFcEkMZSLDT78Vewq5i3HxMjaxZFSCTLTMjmLHtRPvX82XZVROS X-Received: by 2002:a17:907:c15:b0:78d:9c3c:fb8f with SMTP id ga21-20020a1709070c1500b0078d9c3cfb8fmr24610760ejc.347.1666537305244; Sun, 23 Oct 2022 08:01:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666537305; cv=none; d=google.com; s=arc-20160816; b=Omzj4VMIRvd07kQR/L0yRACqIsSwF9xlL8ISfyHQFmYYAUBh6SwoiMk7ufRf3YwUbD Pz/YHmFgI1wvGDnEQaXPanETpNMKAunfr+N4mc0BC3JQqUEhKNcice9RA/CrDD7U3zg9 WtQ8t2bLj7sOZjiUCl108r0O0Tsetl08nIsEmYfz2LySktTUdfbgcC0LunyHswt5R6mb EdIsMT45j6jrdJ/+7rwuPlrkTd/bv/6v9i91g9Aab+R5Naw92VrEZXXLXPMKiqr+s31x NHx+SQadIuN9G63jxN5pivxS2aZ5lw6/AfOXhE3GQAGOf5oHIVacL0VwMq+l/UgQAQdP r8xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Qe13r2WOQcom5qgxJ09BQZ2VmoEe3B9Ta0b6mH3uDkQ=; b=cBSytaHebInS6nkYt7h93ZqPrILg3aJKsP9I9Do4ncwe1/NhP1sW19s7rtv7uUGZ01 7lW8IcI2xS81CwEeJCDyTyfohFVESLJy2YVPYOCcIBTeez3mMfReFcml6eGGjhVgZX8Y VnG3wXHuPYPy54HAbg1PNgKhlX+NIFadx25gkEFzerg/4D/JV5W9KtCsP+Vb/xT8bNTH mdexd36A4lGq3eNuKVZHVSC9ANxWYk03kMUQ7yEdzzbwxF0nT0TG8iDCx0iiuVwFkg9f ZzJMAec605aIXcBpin/qDWUOjwfRPPnOyTJbe6gW7EGYdxFbLRGsbAahy2SSCCeEOTbi +7Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=TsA5DcJq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id b13-20020a5d4d8d000000b0023660f6cecfsm3747605wru.80.2022.10.23.07.57.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:04 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/5] clk: ingenic: Make PLL clock enable_bit and stable_bit optional Date: Sun, 23 Oct 2022 15:56:50 +0100 Message-Id: <20221023145653.177234-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747491021374437904?= X-GMAIL-MSGID: =?utf-8?q?1747491021374437904?= When the enable bit is undefined, the clock is assumed to be always on and enable/disable is a no-op. When the stable bit is undefined, the PLL stable check is a no-op. Signed-off-by: Aidan MacDonald --- drivers/clk/ingenic/cgu.c | 14 +++++++++++++- drivers/clk/ingenic/cgu.h | 10 ++++++---- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 7dc2e2567d53..bbb55e8d8b55 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -190,6 +190,9 @@ static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu, { u32 ctl; + if (pll_info->stable_bit < 0) + return 0; + return readl_poll_timeout(cgu->base + pll_info->reg, ctl, ctl & BIT(pll_info->stable_bit), 0, 100 * USEC_PER_MSEC); @@ -231,7 +234,7 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, writel(ctl, cgu->base + pll_info->reg); /* If the PLL is enabled, verify that it's stable */ - if (ctl & BIT(pll_info->enable_bit)) + if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) ret = ingenic_pll_check_stable(cgu, pll_info); spin_unlock_irqrestore(&cgu->lock, flags); @@ -249,6 +252,9 @@ static int ingenic_pll_enable(struct clk_hw *hw) int ret; u32 ctl; + if (pll_info->enable_bit < 0) + return 0; + spin_lock_irqsave(&cgu->lock, flags); if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); @@ -279,6 +285,9 @@ static void ingenic_pll_disable(struct clk_hw *hw) unsigned long flags; u32 ctl; + if (pll_info->enable_bit < 0) + return; + spin_lock_irqsave(&cgu->lock, flags); ctl = readl(cgu->base + pll_info->reg); @@ -296,6 +305,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw) const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; u32 ctl; + if (pll_info->enable_bit < 0) + return true; + ctl = readl(cgu->base + pll_info->reg); return !!(ctl & BIT(pll_info->enable_bit)); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 567142b584bb..a5e44ca7f969 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -42,8 +42,10 @@ * @bypass_reg: the offset of the bypass control register within the CGU * @bypass_bit: the index of the bypass bit in the PLL control register, or * -1 if there is no bypass bit - * @enable_bit: the index of the enable bit in the PLL control register - * @stable_bit: the index of the stable bit in the PLL control register + * @enable_bit: the index of the enable bit in the PLL control register, or + * -1 if there is no enable bit (ie, the PLL is always on) + * @stable_bit: the index of the stable bit in the PLL control register, or + * -1 if there is no stable bit */ struct ingenic_cgu_pll_info { unsigned reg; @@ -54,8 +56,8 @@ struct ingenic_cgu_pll_info { u8 od_shift, od_bits, od_max; unsigned bypass_reg; s8 bypass_bit; - u8 enable_bit; - u8 stable_bit; + s8 enable_bit; + s8 stable_bit; void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *m, unsigned int *n, unsigned int *od); From patchwork Sun Oct 23 14:56:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 8043 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp27791wru; Sun, 23 Oct 2022 08:01:07 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7t/BXDmQpDlg1YB91Hu2Hfo1CyJjpz+BY1fktI4okDsiP4/Meb//311DBPxvEZVnazwLzJ X-Received: by 2002:a05:6402:3484:b0:45d:2f59:fae1 with SMTP id v4-20020a056402348400b0045d2f59fae1mr26487682edc.237.1666537267068; Sun, 23 Oct 2022 08:01:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666537267; cv=none; d=google.com; s=arc-20160816; b=mrcD3L9cQ3jBZtMa1zHBfDT0FE0PKitsonVMGdv/D5OKKOy5Lftu34YoX+hmrz/8Gi rHqfsLabeqFv8psvakW5QvBa/7bOauMAMNXvELf+hWbCn/yzFF8oCS8VACk6ZqMy2ijY ZdB9e70KmDq4qbZx5kOWJTDq/J7QY5nrLb0NzHGsDg98mQB5/lltOV3brU5TkItheUGv m/ZwA9tpJFJTeaiGrVjDr23efACONkruNK2abiCF/M3vIlYdVwSTdXyazaKQ9ttyn1iz kNepNlZRhiXgQHs9sNYnl21qM8zFdHvLl58Gcj1B54JsfBx/hkYOMgWq3EwbOaaWB2G1 YVsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Megb+EEQ+42EwfPZKfmRdUWZPZjTpyMy4vvWz7+p9e0=; b=kTdew9NFF7T/EK3RFHKO2CGIzEQW273lATUGRfgPGdP2bO7szBj3fhkVwmdCAMF3KS bbGz7pGTOz1aERQrgScRJnKcerZFGuV28G1ZRBO542A8XDd4pN52lTQ5c0JWXFXskmAP FXmObrCyK7PG98OFwH3aTxRRXY3QEUwlNCkY+VzESkHoXBeh0f38kSVUvf4pRijjoeeg a4yf/dt9q7wYOftNgvLgu3m90eKu2bn4Itv+s73ZCkWIrCbtr/8Quoy7d4St+y2TZjTq dJykaIWRugxihexkveyR1XaulTUEfrDMvx60MRQoVL3Jbia3DhRy3j4DBSV6yzEgPvAq /qdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=oItMR1ON; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id r6-20020a5d52c6000000b00228dbf15072sm23603166wrv.62.2022.10.23.07.57.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:05 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/5] clk: ingenic: Add .set_rate_hook() for PLL clocks Date: Sun, 23 Oct 2022 15:56:51 +0100 Message-Id: <20221023145653.177234-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747490981478146553?= X-GMAIL-MSGID: =?utf-8?q?1747490981478146553?= The set rate hook is called immediately after updating the clock register but before the spinlock is released. This allows another register to be updated alongside the main one, which is needed to handle the I2S divider on some SoCs. Signed-off-by: Aidan MacDonald --- drivers/clk/ingenic/cgu.c | 3 +++ drivers/clk/ingenic/cgu.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index bbb55e8d8b55..574d5fe10fdf 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -233,6 +233,9 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, writel(ctl, cgu->base + pll_info->reg); + if (pll_info->set_rate_hook) + pll_info->set_rate_hook(pll_info, rate, parent_rate); + /* If the PLL is enabled, verify that it's stable */ if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) ret = ingenic_pll_check_stable(cgu, pll_info); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index a5e44ca7f969..99da9bd86e63 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -46,6 +46,8 @@ * -1 if there is no enable bit (ie, the PLL is always on) * @stable_bit: the index of the stable bit in the PLL control register, or * -1 if there is no stable bit + * @set_rate_hook: hook called immediately after updating the CGU register, + * before releasing the spinlock */ struct ingenic_cgu_pll_info { unsigned reg; @@ -61,6 +63,8 @@ struct ingenic_cgu_pll_info { void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *m, unsigned int *n, unsigned int *od); + void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate); }; /** From patchwork Sun Oct 23 14:56:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 8047 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp29088wru; Sun, 23 Oct 2022 08:03:48 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5S8zCaBXB8THIv5KFg9BIUUbzKfNBHK9UIQWjPFOxMFHSOpVRlTJ4PqcWFVjRhL1FuwAbS X-Received: by 2002:aa7:c40b:0:b0:45d:4492:a8cb with SMTP id j11-20020aa7c40b000000b0045d4492a8cbmr26120384edq.217.1666537428252; Sun, 23 Oct 2022 08:03:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666537428; cv=none; d=google.com; s=arc-20160816; b=Gt06AWCBu0QWQTG9FaeYD51DGpAdNI603CzN5ptNJGYCUsQ/3aheGR5qhh6s6O20gr Uj4jRq6ydC8jOz05fAhly/676Xm4gwY03T8oukeLaLGQpXxlzm1n8rohKPnxD4wJIDOY yxIzVEhA1+/5ruHDmDx/rB8SkJG4dpQpyBNAqN1fZYb6c6TQDeWMG08JRf/I0xYt/CNG 4hc0ozBFodSVphEt3UgZ/lcH14wMoIUWuyWZXYgtPCa9r7jVIb6iXjlthvk9xXCjvreP YWjw5cUZ9RQsGE+4XNwXfAu5QZ5YQotzSNqWc4KbLItmHErGX2wQX7Op4Zgwj3yOD2Fl sSMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZNepXipGDeJQVdil2MM/OA4hZBASj3NiREHHvlf/RXY=; b=hJZ5dCVVfZpjKnd+Ad2+pUho5TGDFZa3Y5gd7gc7VXbIOvUaItpGma9moaACufxTVJ x+athjeTPULFPBfIE0r79KwPWxu0hcUG7xFzdD7txhhKBrWyXLHqXLyAquRqmdnva8x+ fGp9slKQh/23HZxj0sIREAUurpKKpvaJAY7tzHTHg+LS9mKjn30gV4n4ZqLIvbUd8LWD Njm3MI8krONogUJsYkkrQRPqsS4AO1exqBBU7eJ3EXaSN5wjP2s3aschBn511XdWjlV3 JhKc0wD3ygkoi47EAIZTm58HUr++Vc9c28vgOcYcD9IHLyMB++UHcEnVy8+IbRL1atLQ zTCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=N5ocY8LP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id j8-20020adfd208000000b00235da296623sm9139763wrh.31.2022.10.23.07.57.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:06 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/5] dt-bindings: ingenic,x1000-cgu: Add audio clocks Date: Sun, 23 Oct 2022 15:56:52 +0100 Message-Id: <20221023145653.177234-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747491150116944219?= X-GMAIL-MSGID: =?utf-8?q?1747491150116944219?= Add bindings for audio-related clocks on the Ingenic X1000 SoC. Signed-off-by: Aidan MacDonald Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/ingenic,x1000-cgu.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/ingenic,x1000-cgu.h b/include/dt-bindings/clock/ingenic,x1000-cgu.h index f187e0719fd3..78daf44b3514 100644 --- a/include/dt-bindings/clock/ingenic,x1000-cgu.h +++ b/include/dt-bindings/clock/ingenic,x1000-cgu.h @@ -50,5 +50,9 @@ #define X1000_CLK_PDMA 35 #define X1000_CLK_EXCLK_DIV512 36 #define X1000_CLK_RTC 37 +#define X1000_CLK_AIC 38 +#define X1000_CLK_I2SPLLMUX 39 +#define X1000_CLK_I2SPLL 40 +#define X1000_CLK_I2S 41 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ From patchwork Sun Oct 23 14:56:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 8045 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp28316wru; Sun, 23 Oct 2022 08:02:08 -0700 (PDT) X-Google-Smtp-Source: AMsMyM66QpTgiqsthqajS0ZBRyraTz2vYKDnp2BNVEC1UmyDa0ixh1xFh66eL62adZ1ZOAZU5UdH X-Received: by 2002:a17:907:6e93:b0:78d:dff1:71e3 with SMTP id sh19-20020a1709076e9300b0078ddff171e3mr22701715ejc.94.1666537328665; Sun, 23 Oct 2022 08:02:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666537328; cv=none; d=google.com; s=arc-20160816; b=YB2PI2LL/jO+O15wGK91cEJ2IaSdUjRA3Tyyyu8OwCqyxW3iMMlhZSpt2GqTRvn2LL n6+ewp0SX0LzStJOibPHz/IGf7BsQq7nFa7lrEryEDiO8x+LZ08yeJHPh4DP49IPMz8j uwFkBw/bov2Cw+F0KC3p3Qw1t8WGMLhnjHUp7h5H1BClmAXIBhjnqCrndvpunbHhi24e yGWBUHoQgArPPrwa0bMNeS//kam0LR9gEGhafyWlBiC4mdRozUPfY5vh+V4TjF4ITX0T vugfh87lDx2JYUb5NCUyqyXb8xK6OWyf17kUowfVVJWClzNGaow7evRA1sFUz/t1QGf5 5cLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rFj+0g9zC945JfgR9vxO7Ms2xSVk7a3nRyoILt5SjhM=; b=nsR2aoLy+2JfbuMsz9CHJUr8pBXpkvY/QsHahofwkeuXkT/m2RiZt5HsAhALTeeo1m lpvIuPeFTcJtIJytr0SsuXl+LMV6mdFQ/3Yd32mBC5FltMbHtMiPVjaggAA5mgUJ5diL fWNF21/7VakF6tRPipJbTQXRdsl+mtg+OERR2eJTlspPCCSj9zPJ3fCPJ4vR4S8OULWo 2ZaXH7CD8YfvSqZDI1mj6IFIqYE4pZQmMYaxorVieh8iStvHHmjB0SZb8J058v0aoHll 2LHxbHON21ei6Pqv1jACv1lnmF+N9UTBTn6y1Ki3sHzlf21G7VbK38IlEzwRO3mNV6qL OU0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=HjAWWLBr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id hg16-20020a05600c539000b003c6b70a4d69sm8345331wmb.42.2022.10.23.07.57.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:57:08 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] clk: ingenic: Add X1000 audio clocks Date: Sun, 23 Oct 2022 15:56:53 +0100 Message-Id: <20221023145653.177234-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> References: <20221023145653.177234-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747491046137928512?= X-GMAIL-MSGID: =?utf-8?q?1747491046137928512?= The X1000's CGU supplies the I2S system clock to the AIC module and ultimately the audio codec, represented by the "i2s" clock. It is a simple mux which can either pass through EXCLK or a PLL multiplied by a fractional divider (the "i2s_pll" clock). The AIC contains a separate 1/N divider controlled by the I2S driver, which generates the bit clock from the system clock. The frame clock is always fixed to 1/64th of the bit clock. Signed-off-by: Aidan MacDonald --- drivers/clk/ingenic/x1000-cgu.c | 69 +++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index b2ce3fb83f54..341276e5e1ef 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include @@ -168,6 +169,37 @@ static const struct clk_ops x1000_otg_phy_ops = { .is_enabled = x1000_usb_phy_is_enabled, }; +static void +x1000_i2spll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate, + unsigned int *pm, unsigned int *pn, unsigned int *pod) +{ + const unsigned long m_max = GENMASK(pll_info->m_bits - 1, 0); + const unsigned long n_max = GENMASK(pll_info->n_bits - 1, 0); + unsigned long m, n; + + rational_best_approximation(rate, parent_rate, m_max, n_max, &m, &n); + + /* n should not be less than 2*m */ + if (n < 2 * m) + n = 2 * m; + + *pm = m; + *pn = n; + *pod = 1; +} + +static void +x1000_i2spll_set_rate_hook(const struct ingenic_cgu_pll_info *pll_info, + unsigned long rate, unsigned long parent_rate) +{ + /* + * For some reason, the I2S divider doesn't work properly after + * updating I2SCDR unless I2SCDR1 is read & written back. + */ + writel(readl(cgu->base + CGU_REG_I2SCDR1), cgu->base + CGU_REG_I2SCDR1); +} + static const s8 pll_od_encoding[8] = { 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, }; @@ -319,6 +351,37 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 25 }, }, + [X1000_CLK_I2SPLLMUX] = { + "i2s_pll_mux", CGU_CLK_MUX, + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 }, + .mux = { CGU_REG_I2SCDR, 31, 1 }, + }, + + [X1000_CLK_I2SPLL] = { + "i2s_pll", CGU_CLK_PLL, + .parents = { X1000_CLK_I2SPLLMUX, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_I2SCDR, + .rate_multiplier = 1, + .m_shift = 13, + .m_bits = 9, + .n_shift = 0, + .n_bits = 13, + .calc_m_n_od = x1000_i2spll_calc_m_n_od, + .set_rate_hook = x1000_i2spll_set_rate_hook, + }, + }, + + [X1000_CLK_I2S] = { + "i2s", CGU_CLK_MUX, + .parents = { X1000_CLK_EXCLK, -1, -1, X1000_CLK_I2SPLL }, + /* + * NOTE: the mux is at bit 30; bit 29 enables the M/N divider. + * Therefore, the divider is disabled when EXCLK is selected. + */ + .mux = { CGU_REG_I2SCDR, 29, 2 }, + }, + [X1000_CLK_LCD] = { "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL }, @@ -426,6 +489,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { .gate = { CGU_REG_CLKGR, 9 }, }, + [X1000_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { X1000_CLK_EXCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + [X1000_CLK_UART0] = { "uart0", CGU_CLK_GATE, .parents = { X1000_CLK_EXCLK, -1, -1, -1 },