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Wed, 26 Apr 2023 14:22:45 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rep.dot.nop@gmail.com, jeffreyalaw@gmail.com, schwab@linux-m68k.org, Patrick O'Neill Subject: [PATCH v2] RISC-V: Fix sync.md and riscv.cc whitespace errors Date: Wed, 26 Apr 2023 14:21:06 -0700 Message-Id: <20230426212106.1134636-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230426205349.1131469-1-patrick@rivosinc.com> References: <20230426205349.1131469-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764273651267499555?= X-GMAIL-MSGID: =?utf-8?q?1764275463997106392?= This patch fixes whitespace errors introduced with https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html 2023-04-26 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc: Fix whitespace. * config/riscv/sync.md: Fix whitespace. Signed-off-by: Patrick O'Neill --- Patch was checked with contrib/check_GNU_style.py Whitespace changes in this patch are 2 flavors: * Add space between function name and () * 2 spaces between end of comment and */ --- v2 Changelog: * Ignored checker warning for space before [] in rtl --- gcc/config/riscv/riscv.cc | 6 +++--- gcc/config/riscv/sync.md | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0f890469d7a..1529855a2b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7193,7 +7193,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask, emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask, gen_lowpart (QImode, *shift))); - emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask)); + emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask)); } /* Leftshift a subword within an SImode register. */ @@ -7206,8 +7206,8 @@ riscv_lshift_subword (machine_mode mode, rtx value, rtx shift, emit_move_insn (value_reg, simplify_gen_subreg (SImode, value, mode, 0)); - emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, - gen_lowpart (QImode, shift))); + emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, + gen_lowpart (QImode, shift))); } /* Initialize the GCC target structure. */ diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 83be6431cb6..19274528262 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -128,10 +128,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_nand to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -193,10 +193,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_ to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -367,7 +367,7 @@ { rtx difference = gen_rtx_MINUS (SImode, val, exp); compare = gen_reg_rtx (SImode); - emit_move_insn (compare, difference); + emit_move_insn (compare, difference); } if (word_mode != SImode) @@ -393,10 +393,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_cas_strong to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -461,7 +461,7 @@ "TARGET_ATOMIC" { /* We have no QImode atomics, so use the address LSBs to form a mask, - then use an aligned SImode atomic. */ + then use an aligned SImode atomic. */ rtx result = operands[0]; rtx mem = operands[1]; rtx model = operands[2];