From patchwork Wed Apr 26 12:37:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 87849 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp208743vqo; Wed, 26 Apr 2023 05:39:20 -0700 (PDT) X-Google-Smtp-Source: AKy350YPt16q/U66o7MQHO9WVkw47Ve4nmVNHD+UTTwnQ5ylmOdjSuqNOKMpW5Mbzi7IMeRV90A4 X-Received: by 2002:aa7:c758:0:b0:505:34c:eb38 with SMTP id c24-20020aa7c758000000b00505034ceb38mr17273534eds.11.1682512760380; Wed, 26 Apr 2023 05:39:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682512760; cv=none; d=google.com; s=arc-20160816; b=K0U13m/uTXjy4oNpTWv3ThF1haCgS4pze6DRQtaCf9BigIy1zOr0KNJ4mSHdqiDnc5 CKrb3DjumHDOKtmGk9cmhuUrSRvpRn3qPrgNyoqGcBk/mQAxEwy1Ef+1sLzv84ueJfAt VYw3khzCOzqQZj655KVJfy/eu9L9cqLPO/0HdlU/cTCq87PP212VJrcTfeis8nrObKjr onlHGo8DY+Hu3iQqOzQzHAH/CW5Q2YYnEP+nwwwpYh9J7fRJXJQls+pD9PIt/NHzM4ND I2eLtSm6XuU+qV3ue1EvlFVfWXTHkz5l75ajB21FP7bNkDJPB06FJfscwEAWD8nkEvsT 9bqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=Km7s8ziGHjvECv+KMY0dbjkEPfqQs7Wwl/f636/xjo8=; b=kK6DgefKOtrGm+/CXbbjkbdxvZ4venJ67+s4KO58QqDB6Qr1d0bSX/R4fjYon9mA+/ 1QZyl5eKuacHxHbRgmlCO+nmhVlGlGSBvEzyngk7tyzKLTpEUwQpqsz+TNclgbiCIA7n LkbpeApKak68uR/bB12H/rJkgzqHf3CqlcGpJCGvpnKWZ/dtaYGWlD2pqfqFmXsTdOQO ikSdQShP8jQnGSmFXZpXypz7YGCJ3u5Fa/RVEbF5fUY52a0/S8KAXHNPkop7kfFObmRC nRr9entvhqQy8nIEgmKnCCpd10OymxiJWV5dDygptXlqPiEFxLYkF7vHbnEOWl0bzbDZ 2bFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Vi13nOyd; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id bf12-20020a0564021a4c00b005048392d9e5si12440561edb.670.2023.04.26.05.39.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 05:39:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Vi13nOyd; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4ADC43858C1F for ; Wed, 26 Apr 2023 12:39:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4ADC43858C1F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682512759; bh=Km7s8ziGHjvECv+KMY0dbjkEPfqQs7Wwl/f636/xjo8=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=Vi13nOydmhJMa/klaj4zs2u/xQsC7X7pvv+CZPN2fu6oh18Opx8R1hVVU8sqBVpsD HvM+51RjUHEbTMnet9vvx/aWnt1NKltleJdChfCS8+p7URzPBk+2rQDLqQCyW50Lh/ uiJOPiB0v9GQ/Ywj0uFab17V2CklmhbQ8S6LtfFQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 583273858C53 for ; Wed, 26 Apr 2023 12:38:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 583273858C53 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="433375177" X-IronPort-AV: E=Sophos;i="5.99,228,1677571200"; d="scan'208";a="433375177" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 05:38:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="763302537" X-IronPort-AV: E=Sophos;i="5.99,228,1677571200"; d="scan'208";a="763302537" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga004.fm.intel.com with ESMTP; 26 Apr 2023 05:38:08 -0700 Received: from yanzhang-dev.sh.intel.com (yanzhang-dev.sh.intel.com [10.239.82.176]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 10A091005677; Wed, 26 Apr 2023 20:38:08 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISCV: Add vector psabi checking. Date: Wed, 26 Apr 2023 20:37:43 +0800 Message-Id: <20230426123743.3210243-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "yanzhang.wang--- via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: yanzhang.wang@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764242500504141903?= X-GMAIL-MSGID: =?utf-8?q?1764242500504141903?= From: Yanzhang Wang This patch adds support to check function's argument or return is vector type and throw warning if yes. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_scalable_vector_type_p): (riscv_arg_has_vector): (riscv_pass_in_vector_p): (riscv_get_arg_info): gcc/testsuite/ChangeLog: * gcc.target/riscv/vector-abi-1.c: New test. * gcc.target/riscv/vector-abi-2.c: New test. * gcc.target/riscv/vector-abi-3.c: New test. * gcc.target/riscv/vector-abi-4.c: New test. * gcc.target/riscv/vector-abi-5.c: New test. Signed-off-by: Yanzhang Wang Co-authored-by: Kito Cheng --- gcc/config/riscv/riscv.cc | 73 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 ++++ gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 14 ++++ gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 ++++ gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 ++++ gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 ++++ 6 files changed, 146 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 76eee4a55e9..06e9fe7d924 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3728,6 +3728,76 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1, GEN_INT (offset2)))); } +/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and + intrinsic vector type. Because we can't get the decl for the params. */ + +static bool +riscv_scalable_vector_type_p (const_tree type) +{ + tree size = TYPE_SIZE (type); + if (size && TREE_CODE (size) == INTEGER_CST) + return false; + + /* For the data type like vint32m1_t, the size code is POLY_INT_CST. */ + return true; +} + +static bool +riscv_arg_has_vector (const_tree type) +{ + bool is_vector = false; + + switch (TREE_CODE (type)) + { + case RECORD_TYPE: + if (!COMPLETE_TYPE_P (type)) + break; + + for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f)) + if (TREE_CODE (f) == FIELD_DECL) + { + tree field_type = TREE_TYPE (f); + if (!TYPE_P (field_type)) + break; + + /* Ignore it if it's fixed length vector. */ + if (VECTOR_TYPE_P (field_type)) + is_vector = riscv_scalable_vector_type_p (field_type); + else + is_vector = riscv_arg_has_vector (field_type); + } + + break; + + case VECTOR_TYPE: + is_vector = riscv_scalable_vector_type_p (type); + break; + + default: + is_vector = false; + break; + } + + return is_vector; +} + +/* Pass the type to check whether it's a vector type or contains vector type. + Only check the value type and no checking for vector pointer type. */ + +static void +riscv_pass_in_vector_p (const_tree type) +{ + static int warned = 0; + + if (type && riscv_arg_has_vector (type) && !warned) + { + warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in " + "experimental stage and may changes in the upcoming version of " + "GCC."); + warned = 1; + } +} + /* Fill INFO with information about a single argument, and return an RTL pattern to pass or return the argument. CUM is the cumulative state for earlier arguments. MODE is the mode of this argument and @@ -3812,6 +3882,9 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, } } + /* Only check existing of vector type. */ + riscv_pass_in_vector_p (type); + /* Work out the size of the argument. */ num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode).to_constant (); num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c new file mode 100644 index 00000000000..114ee6de483 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +void +fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */ + +void +bar () +{ + vint32m1_t a; + fun (a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c new file mode 100644 index 00000000000..fd4569535cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +vint32m1_t +fun (vint32m1_t* a) { return *a; } /* { dg-warning "the vector type" } */ + +void +bar () +{ + vint32m1_t a; + fun (&a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c new file mode 100644 index 00000000000..844a5db4027 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +vint32m1_t* +fun (vint32m1_t* a) { return a; } /* { dg-bogus "the vector type" } */ + +void +bar () +{ + vint32m1_t a; + fun (&a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c new file mode 100644 index 00000000000..a5dc2dffaac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +typedef int v4si __attribute__ ((vector_size (16))); + +v4si +fun (v4si a) { return a; } /* { dg-bogus "the vector type" } */ + +void +bar () +{ + v4si a; + fun (a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c new file mode 100644 index 00000000000..1fe83c8fc87 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +typedef int v4si __attribute__ ((vector_size (16))); +struct A { int a; v4si b; }; + +void +fun (struct A a) {} /* { dg-bogus "the vector type" } */ + +void +bar () +{ + struct A a; + fun (a); +}