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Any individual config can be identified by PHY_ID_MATCH_EXACT in the respective structure. Signed-off-by: Harini Katakam --- v2: New patch drivers/net/phy/mscc/mscc_main.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index 62bf99e45af1..75d9582e5784 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -2656,19 +2656,7 @@ static struct phy_driver vsc85xx_driver[] = { module_phy_driver(vsc85xx_driver); static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { - { PHY_ID_VSC8504, 0xfffffff0, }, - { PHY_ID_VSC8514, 0xfffffff0, }, - { PHY_ID_VSC8530, 0xfffffff0, }, - { PHY_ID_VSC8531, 0xfffffff0, }, - { PHY_ID_VSC8540, 0xfffffff0, }, - { PHY_ID_VSC8541, 0xfffffff0, }, - { PHY_ID_VSC8552, 0xfffffff0, }, - { PHY_ID_VSC856X, 0xfffffff0, }, - { PHY_ID_VSC8572, 0xfffffff0, }, - { PHY_ID_VSC8574, 0xfffffff0, }, - { PHY_ID_VSC8575, 0xfffffff0, }, - { PHY_ID_VSC8582, 0xfffffff0, }, - { PHY_ID_VSC8584, 0xfffffff0, }, + { PHY_ID_MATCH_VENDOR(0xfffffff0) }, { } }; From patchwork Wed Apr 26 10:43:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harini Katakam X-Patchwork-Id: 87805 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp146940vqo; Wed, 26 Apr 2023 03:47:55 -0700 (PDT) X-Google-Smtp-Source: AKy350bmWfwL9SC9GeVTcYASGUe7vkKCEyA8Fe0zb0my09VLTrDC+II56oXKsOnYeOVg/dA8vOCE X-Received: by 2002:a17:903:40cb:b0:1a6:9e53:950e with SMTP id t11-20020a17090340cb00b001a69e53950emr20691814pld.41.1682506075601; Wed, 26 Apr 2023 03:47:55 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1682506075; cv=pass; d=google.com; s=arc-20160816; b=DyI3uIj7L0jF2TMdiUavOobZgKprB5xU14TLTg2OfQX+nyOelHuXnVCXWHy9mGzwl2 IhWSHX1CJWkFrRTQOXKUP83icjOF7vqdem/HzNbYMfIH/3p6gEWK32KWI9M56c7wwXCh MfMclIj2f5yDNoh547t1OiBYrzpoqyzOvj5AM1U1sqKeJUzJ22zLEeSGjXHBZt9OY5pa vXqS/RZaT8+UYhjcw0DzX95QFbPOri5IZTtQ9kJOfi6/0LOO4B3ewTBk1sakjyS2zSr7 ybLNOxV5u8YBBj+nTSt4ZCme0h55uewnTkZqwtpEz5kzvAdMNtVuuJpqJWemtvKqwZSu Vz9g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=1qWFyWDzv9iEIsKXgIuj5QvKwFPFeS/UsWsmsBVK7+Y=; b=sjNkhaDhUFSjUMP9BbtPWEwmS9VdmsZ49UeAGxF0xXPLbUeHctGxr12XIiYsSk0BSE rbONFrzjzR9PUzFWnewyl//2nQeksuDv5rVkZcKawheIJs0rKAW00K44JSek920fwd0F 9KWkPIG5zwzy7X+BJ4Xygvnvfl3xYhrYTsuJMLyduz3XgUoROQhT3sJDI7yxr9t0D36q TItyUS5e5WF5rbBQt0AxGQ/kvFsaR+ZrgyBTgaLCtU+FbT+ZbTCf2gqsKNJCr7opnQp/ i+x3LAMGSqViBKqC3wkg7nCXgMUspQgk6uglKtsBM67gkH7BX4FtxVM0u2xrdJmPJPo5 feGw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=gRek+SAW; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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The current default value in the Linux driver, when the phy-mode is rgmii-id, is 2ns for both. These properties take priority if specified. Signed-off-by: Harini Katakam Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- v2: - Updated DT binding description and commit for optional delay tuning to be clearer on the precedence - Updated dt property name to include vendor instead of phy device name Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt index 0a3647fe331b..2b779bc3096b 100644 --- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt +++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt @@ -33,6 +33,8 @@ Optional properties: VSC8531_DUPLEX_COLLISION (8). - load-save-gpios : GPIO used for the load/save operation of the PTP hardware clock (PHC). +- mscc,rx-delay : RGMII RX delay. Allowed values are 0.2 - 3.4 ns. +- mscc,tx-delay : RGMII TX delay. Allowed values are 0.2 - 3.4 ns. Table: 1 - Edge rate change From patchwork Wed Apr 26 10:43:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harini Katakam X-Patchwork-Id: 87806 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp147067vqo; Wed, 26 Apr 2023 03:48:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5/drLzcHoO7vvkC1YreULFXe6Bz64lrKJHfIITUuCT91ZEqNwfkRedqSIXyFQs0fKxB9Q3 X-Received: by 2002:a05:6a21:339a:b0:f0:4a5e:b686 with SMTP id yy26-20020a056a21339a00b000f04a5eb686mr2163450pzb.29.1682506097037; Wed, 26 Apr 2023 03:48:17 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1682506097; cv=pass; d=google.com; s=arc-20160816; b=gLF6ts2dd321gqgAiPbo3CwJK7bUT/g7KTSuyBrU4y30LbJTxLdvdi/A/45Cu7yV6d bWeZA+nzeYutMNRifIZRGehte7HKKaEQvKyw7HgLqdlgLUQT5jGpj0xGV/OFWpOyudcX oA+lZMzmZoMqOVEZWttfOqx9Q6RIpbNukfQS1dw3/POPYu/3pGp6G3H0JlPjUs2hfdnV 7L8cQAvHbgkXVwWUm+Ub7rV6QZ0hqnvZZQXX8fIphwlyXmETMMhNnv9tjLSZ5Scw89W3 1ZzrcRzqUAWOXVAYXj2UZKEuU6NO3kYCrdlU+bYy7z2xNaqWh2LJ8MN7gkAs+dicoFdo YdvQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=QyuNeOLwppd5nT2AJUzdSQ3CApNXJ/zLRwIoTahw6eM=; b=mKHP9TlI9EFmjAfXmwvESYim4W+Ei0wx2o3Jd64N3oFMYZyFYYzOZmroPT/ZMKrHxn 6v/BIfdJdPczMKARJ2U8Vh1f2qJ7s6m7REFd8u2qSyscsVqo1Dl/tPxQgnh4BegTmxe6 puyB3Y/vrgORdfBGsqzevxp0O2oM0vS9QU78zWYVFl4suQVgJ/sfT6fMq1DRGVOQC5mV Wr4GlG70aH4byh0OklWQHQg2M747hmUwtcxqeM0sULEXrE/i/oCW2n22V3fpPrxJGT8L jVxBX6esbbw/fuHtsh/63aja8sbAdNpVco3ywwJwg27KxHIjRrCQJUDO0+0n11P0pF+w /ylw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=ljPmumTh; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Wed, 26 Apr 2023 05:43:34 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 26 Apr 2023 05:43:34 -0500 Received: from xhdharinik40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Wed, 26 Apr 2023 05:43:29 -0500 From: Harini Katakam To: , , , , , , , , , , , CC: , , , , , , Subject: [PATCH net-next v2 3/3] phy: mscc: Add support for VSC8531_02 with RGMII tuning Date: Wed, 26 Apr 2023 16:13:13 +0530 Message-ID: <20230426104313.28950-4-harini.katakam@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230426104313.28950-1-harini.katakam@amd.com> References: <20230426104313.28950-1-harini.katakam@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT077:EE_|MN2PR12MB4207:EE_ X-MS-Office365-Filtering-Correlation-Id: 392f4ec5-f7c0-4799-dc3e-08db46431630 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2023 10:43:35.0548 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 392f4ec5-f7c0-4799-dc3e-08db46431630 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT077.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4207 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764235512987797992?= X-GMAIL-MSGID: =?utf-8?q?1764235512987797992?= From: Harini Katakam Add support for VSC8531_02 (Rev 2) device. Add support for optional RGMII RX and TX delay tuning via devicetree. The hierarchy is: - Retain the defaul 0.2ns delay when RGMII tuning is not set. - Retain the default 2ns delay when RGMII tuning is set and DT delay property is NOT specified. - Use the DT delay value when RGMII tuning is set and a DT delay property is specified. Signed-off-by: Harini Katakam Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- v2: - Switch both VSC8531 and VSC8531-02 to use exact phy id match as they share the same model number - Ensure RCT - Improve optional property read drivers/net/phy/mscc/mscc.h | 3 +++ drivers/net/phy/mscc/mscc_main.c | 40 ++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index a50235fdf7d9..5a26eba0ace0 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -281,6 +281,7 @@ enum rgmii_clock_delay { #define PHY_ID_VSC8514 0x00070670 #define PHY_ID_VSC8530 0x00070560 #define PHY_ID_VSC8531 0x00070570 +#define PHY_ID_VSC8531_02 0x00070572 #define PHY_ID_VSC8540 0x00070760 #define PHY_ID_VSC8541 0x00070770 #define PHY_ID_VSC8552 0x000704e0 @@ -373,6 +374,8 @@ struct vsc8531_private { * package. */ unsigned int base_addr; + u32 rx_delay; + u32 tx_delay; #if IS_ENABLED(CONFIG_MACSEC) /* MACsec fields: diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index 75d9582e5784..80cc90a23d57 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -525,6 +525,7 @@ static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl, { u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1; u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1; + struct vsc8531_private *vsc8531 = phydev->priv; u16 reg_val = 0; int rc; @@ -532,10 +533,10 @@ static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl, if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) - reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos; + reg_val |= vsc8531->rx_delay << rgmii_rx_delay_pos; if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) - reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos; + reg_val |= vsc8531->tx_delay << rgmii_tx_delay_pos; rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, rgmii_cntl, @@ -1812,6 +1813,15 @@ static int vsc85xx_config_init(struct phy_device *phydev) { int rc, i, phy_id; struct vsc8531_private *vsc8531 = phydev->priv; + struct device_node *of_node = phydev->mdio.dev.of_node; + + vsc8531->rx_delay = RGMII_CLK_DELAY_2_0_NS; + rc = of_property_read_u32(of_node, "mscc,rx-delay", + &vsc8531->rx_delay); + + vsc8531->tx_delay = RGMII_CLK_DELAY_2_0_NS; + rc = of_property_read_u32(of_node, "mscc,tx-delay", + &vsc8531->tx_delay); rc = vsc85xx_default_config(phydev); if (rc) @@ -2413,9 +2423,8 @@ static struct phy_driver vsc85xx_driver[] = { .get_stats = &vsc85xx_get_stats, }, { - .phy_id = PHY_ID_VSC8531, + PHY_ID_MATCH_EXACT(PHY_ID_VSC8531), .name = "Microsemi VSC8531", - .phy_id_mask = 0xfffffff0, /* PHY_GBIT_FEATURES */ .soft_reset = &genphy_soft_reset, .config_init = &vsc85xx_config_init, @@ -2436,6 +2445,29 @@ static struct phy_driver vsc85xx_driver[] = { .get_strings = &vsc85xx_get_strings, .get_stats = &vsc85xx_get_stats, }, +{ + PHY_ID_MATCH_EXACT(PHY_ID_VSC8531_02), + .name = "Microsemi VSC8531-02", + /* PHY_GBIT_FEATURES */ + .soft_reset = &genphy_soft_reset, + .config_init = &vsc85xx_config_init, + .config_aneg = &vsc85xx_config_aneg, + .read_status = &vsc85xx_read_status, + .handle_interrupt = vsc85xx_handle_interrupt, + .config_intr = &vsc85xx_config_intr, + .suspend = &genphy_suspend, + .resume = &genphy_resume, + .probe = &vsc85xx_probe, + .set_wol = &vsc85xx_wol_set, + .get_wol = &vsc85xx_wol_get, + .get_tunable = &vsc85xx_get_tunable, + .set_tunable = &vsc85xx_set_tunable, + .read_page = &vsc85xx_phy_read_page, + .write_page = &vsc85xx_phy_write_page, + .get_sset_count = &vsc85xx_get_sset_count, + .get_strings = &vsc85xx_get_strings, + .get_stats = &vsc85xx_get_stats, +}, { .phy_id = PHY_ID_VSC8540, .name = "Microsemi FE VSC8540 SyncE",